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1// SPDX-License-Identifier: GPL-2.02/*3 * Renesas RZ/V2H(P) CPG driver4 *5 * Copyright (C) 2024 Renesas Electronics Corp.6 */7 8#include <linux/clk-provider.h>9#include <linux/device.h>10#include <linux/init.h>11#include <linux/kernel.h>12 13#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>14 15#include "rzv2h-cpg.h"16 17enum clk_ids {18 /* Core Clock Outputs exported to DT */19 LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,20 21 /* External Input Clocks */22 CLK_AUDIO_EXTAL,23 CLK_RTXIN,24 CLK_QEXTAL,25 26 /* PLL Clocks */27 CLK_PLLCM33,28 CLK_PLLCLN,29 CLK_PLLDTY,30 CLK_PLLCA55,31 32 /* Internal Core Clocks */33 CLK_PLLCM33_DIV16,34 CLK_PLLCLN_DIV2,35 CLK_PLLCLN_DIV8,36 CLK_PLLCLN_DIV16,37 CLK_PLLDTY_ACPU,38 CLK_PLLDTY_ACPU_DIV4,39 40 /* Module Clocks */41 MOD_CLK_BASE,42};43 44static const struct clk_div_table dtable_2_64[] = {45 {0, 2},46 {1, 4},47 {2, 8},48 {3, 16},49 {4, 64},50 {0, 0},51};52 53static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {54 /* External Clock Inputs */55 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),56 DEF_INPUT("rtxin", CLK_RTXIN),57 DEF_INPUT("qextal", CLK_QEXTAL),58 59 /* PLL Clocks */60 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),61 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),62 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),63 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),64 65 /* Internal Core Clocks */66 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),67 68 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),69 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),70 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),71 72 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),73 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),74 75 /* Core Clocks */76 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),77 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),78};79 80static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {81 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),82 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),83 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),84 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),85 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),86 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),87 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),88 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),89 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),90 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),91 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),92 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),93 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),94 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),95 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),96 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),97 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),98 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),99 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),100 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),101 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),102 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),103 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),104 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),105 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),106 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),107 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),108 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),109 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),110 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),111 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),112 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),113 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),114 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),115 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),116 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),117 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),118 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),119};120 121static const struct rzv2h_reset r9a09g057_resets[] __initconst = {122 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */123 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */124 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */125 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */126 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */127 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */128 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */129 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */130 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */131 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */132 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */133 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */134 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */135 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */136 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */137 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */138 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */139 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */140 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */141 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */142 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */143 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */144 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */145 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */146 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */147};148 149const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {150 /* Core Clocks */151 .core_clks = r9a09g057_core_clks,152 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks),153 .last_dt_core_clk = LAST_DT_CORE_CLK,154 .num_total_core_clks = MOD_CLK_BASE,155 156 /* Module Clocks */157 .mod_clks = r9a09g057_mod_clks,158 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks),159 .num_hw_mod_clks = 25 * 16,160 161 /* Resets */162 .resets = r9a09g057_resets,163 .num_resets = ARRAY_SIZE(r9a09g057_resets),164};165