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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Renesas Clock Pulse Generator / Module Standby and Software Reset4 *5 * Copyright (C) 2015 Glider bvba6 */7 8#ifndef __CLK_RENESAS_CPG_MSSR_H__9#define __CLK_RENESAS_CPG_MSSR_H__10 11 /*12 * Definitions of CPG Core Clocks13 *14 * These include:15 * - Clock outputs exported to DT16 * - External input clocks17 * - Internal CPG clocks18 */19 20struct cpg_core_clk {21 /* Common */22 const char *name;23 unsigned int id;24 unsigned int type;25 /* Depending on type */26 unsigned int parent; /* Core Clocks only */27 unsigned int div;28 unsigned int mult;29 unsigned int offset;30};31 32enum clk_types {33 /* Generic */34 CLK_TYPE_IN, /* External Clock Input */35 CLK_TYPE_FF, /* Fixed Factor Clock */36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */38 CLK_TYPE_FR, /* Fixed Rate Clock */39 40 /* Custom definitions start here */41 CLK_TYPE_CUSTOM,42};43 44#define DEF_TYPE(_name, _id, _type...) \45 { .name = _name, .id = _id, .type = _type }46#define DEF_BASE(_name, _id, _type, _parent...) \47 DEF_TYPE(_name, _id, _type, .parent = _parent)48 49#define DEF_INPUT(_name, _id) \50 DEF_TYPE(_name, _id, CLK_TYPE_IN)51#define DEF_FIXED(_name, _id, _parent, _div, _mult) \52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)53#define DEF_DIV6P1(_name, _id, _parent, _offset) \54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)55#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)57#define DEF_RATE(_name, _id, _rate) \58 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)59 60 /*61 * Definitions of Module Clocks62 */63 64struct mssr_mod_clk {65 const char *name;66 unsigned int id;67 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */68};69 70/* Convert from sparse base-100 to packed index space */71#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))72 73#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))74 75#define DEF_MOD(_name, _mod, _parent...) \76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }77 78/* Convert from sparse base-10 to packed index space */79#define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))80 81#define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))82 83#define DEF_MOD_STB(_name, _mod, _parent...) \84 { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }85 86struct device_node;87 88enum clk_reg_layout {89 CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,90 CLK_REG_LAYOUT_RZ_A,91 CLK_REG_LAYOUT_RCAR_GEN4,92};93 94 /**95 * SoC-specific CPG/MSSR Description96 *97 * @early_core_clks: Array of Early Core Clock definitions98 * @num_early_core_clks: Number of entries in early_core_clks[]99 * @early_mod_clks: Array of Early Module Clock definitions100 * @num_early_mod_clks: Number of entries in early_mod_clks[]101 *102 * @core_clks: Array of Core Clock definitions103 * @num_core_clks: Number of entries in core_clks[]104 * @last_dt_core_clk: ID of the last Core Clock exported to DT105 * @num_total_core_clks: Total number of Core Clocks (exported + internal)106 *107 * @mod_clks: Array of Module Clock definitions108 * @num_mod_clks: Number of entries in mod_clks[]109 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware110 *111 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that112 * should not be disabled without a knowledgeable driver113 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout115 *116 * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power117 * Management, in addition to Module Clocks118 * @num_core_pm_clks: Number of entries in core_pm_clks[]119 *120 * @init: Optional callback to perform SoC-specific initialization121 * @cpg_clk_register: Optional callback to handle special Core Clock types122 */123 124struct cpg_mssr_info {125 /* Early Clocks */126 const struct cpg_core_clk *early_core_clks;127 unsigned int num_early_core_clks;128 const struct mssr_mod_clk *early_mod_clks;129 unsigned int num_early_mod_clks;130 131 /* Core Clocks */132 const struct cpg_core_clk *core_clks;133 unsigned int num_core_clks;134 unsigned int last_dt_core_clk;135 unsigned int num_total_core_clks;136 enum clk_reg_layout reg_layout;137 138 /* Module Clocks */139 const struct mssr_mod_clk *mod_clks;140 unsigned int num_mod_clks;141 unsigned int num_hw_mod_clks;142 143 /* Critical Module Clocks that should not be disabled */144 const unsigned int *crit_mod_clks;145 unsigned int num_crit_mod_clks;146 147 /* Core Clocks suitable for PM, in addition to the Module Clocks */148 const unsigned int *core_pm_clks;149 unsigned int num_core_pm_clks;150 151 /* Callbacks */152 int (*init)(struct device *dev);153 struct clk *(*cpg_clk_register)(struct device *dev,154 const struct cpg_core_clk *core,155 const struct cpg_mssr_info *info,156 struct clk **clks, void __iomem *base,157 struct raw_notifier_head *notifiers);158};159 160extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;161extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;162extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;163extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;164extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;165extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;166extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;167extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;168extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;169extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;170extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;171extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;172extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;173extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;174extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;175extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;176extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;177extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;178extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;179extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;180extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;181extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;182extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;183extern const struct cpg_mssr_info r8a779h0_cpg_mssr_info;184 185void __init cpg_mssr_early_init(struct device_node *np,186 const struct cpg_mssr_info *info);187 188 /*189 * Helpers for fixing up clock tables depending on SoC revision190 */191extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,192 unsigned int num_mod_clks,193 const unsigned int *clks, unsigned int n);194#endif195