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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * RZ/G2L Clock Pulse Generator4 *5 * Copyright (C) 2021 Renesas Electronics Corp.6 *7 */8 9#ifndef __RENESAS_RZG2L_CPG_H__10#define __RENESAS_RZG2L_CPG_H__11 12#include <linux/notifier.h>13 14#define CPG_SIPLL5_STBY (0x140)15#define CPG_SIPLL5_CLK1 (0x144)16#define CPG_SIPLL5_CLK3 (0x14C)17#define CPG_SIPLL5_CLK4 (0x150)18#define CPG_SIPLL5_CLK5 (0x154)19#define CPG_SIPLL5_MON (0x15C)20#define CPG_PL1_DDIV (0x200)21#define CPG_PL2_DDIV (0x204)22#define CPG_PL3A_DDIV (0x208)23#define CPG_PL6_DDIV (0x210)24#define CPG_CLKSTATUS (0x280)25#define CPG_PL3_SSEL (0x408)26#define CPG_PL6_SSEL (0x414)27#define CPG_PL6_ETH_SSEL (0x418)28#define CPG_PL5_SDIV (0x420)29#define CPG_RST_MON (0x680)30#define CPG_BUS_ACPU_MSTOP (0xB60)31#define CPG_BUS_MCPU1_MSTOP (0xB64)32#define CPG_BUS_MCPU2_MSTOP (0xB68)33#define CPG_BUS_PERI_COM_MSTOP (0xB6C)34#define CPG_BUS_PERI_CPU_MSTOP (0xB70)35#define CPG_BUS_PERI_DDR_MSTOP (0xB74)36#define CPG_BUS_REG0_MSTOP (0xB7C)37#define CPG_BUS_REG1_MSTOP (0xB80)38#define CPG_BUS_TZCDDR_MSTOP (0xB84)39#define CPG_MHU_MSTOP (0xB88)40#define CPG_BUS_MCPU3_MSTOP (0xB90)41#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)42#define CPG_OTHERFUNC1_REG (0xBE8)43 44#define CPG_SIPLL5_STBY_RESETB BIT(0)45#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)46#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)47#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20)48#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF)49#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)50 51#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16)52 53#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16)54#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24)55 56#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)57#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)58 59/* n = 0/1/2 for PLL1/4/6 */60#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))61#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))62 63#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)64 65#define DDIV_PACK(offset, bitpos, size) \66 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))67#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)68#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)69#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2)70#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)71#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)72#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)73#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)74 75#define SEL_PLL_PACK(offset, bitpos, size) \76 (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))77 78#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)79#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)80#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)81#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)82 83#define EXTAL_FREQ_IN_MEGA_HZ (24)84 85/**86 * Definitions of CPG Core Clocks87 *88 * These include:89 * - Clock outputs exported to DT90 * - External input clocks91 * - Internal CPG clocks92 */93struct cpg_core_clk {94 const char *name;95 unsigned int id;96 unsigned int parent;97 unsigned int div;98 unsigned int mult;99 unsigned int type;100 unsigned int conf;101 unsigned int sconf;102 const struct clk_div_table *dtable;103 const u32 *mtable;104 const unsigned long invalid_rate;105 const unsigned long max_rate;106 const char * const *parent_names;107 notifier_fn_t notifier;108 u32 flag;109 u32 mux_flags;110 int num_parents;111};112 113enum clk_types {114 /* Generic */115 CLK_TYPE_IN, /* External Clock Input */116 CLK_TYPE_FF, /* Fixed Factor Clock */117 CLK_TYPE_SAM_PLL,118 CLK_TYPE_G3S_PLL,119 120 /* Clock with divider */121 CLK_TYPE_DIV,122 CLK_TYPE_G3S_DIV,123 124 /* Clock with clock source selector */125 CLK_TYPE_MUX,126 127 /* Clock with SD clock source selector */128 CLK_TYPE_SD_MUX,129 130 /* Clock for SIPLL5 */131 CLK_TYPE_SIPLL5,132 133 /* Clock for PLL5_4 clock source selector */134 CLK_TYPE_PLL5_4_MUX,135 136 /* Clock for DSI divider */137 CLK_TYPE_DSI_DIV,138 139};140 141#define DEF_TYPE(_name, _id, _type...) \142 { .name = _name, .id = _id, .type = _type }143#define DEF_BASE(_name, _id, _type, _parent...) \144 DEF_TYPE(_name, _id, _type, .parent = _parent)145#define DEF_SAMPLL(_name, _id, _parent, _conf) \146 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)147#define DEF_G3S_PLL(_name, _id, _parent, _conf) \148 DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)149#define DEF_INPUT(_name, _id) \150 DEF_TYPE(_name, _id, CLK_TYPE_IN)151#define DEF_FIXED(_name, _id, _parent, _mult, _div) \152 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)153#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \154 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \155 .parent = _parent, .dtable = _dtable, \156 .flag = CLK_DIVIDER_HIWORD_MASK)157#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \158 DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \159 .parent = _parent, .dtable = _dtable, \160 .flag = CLK_DIVIDER_READ_ONLY)161#define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \162 _max_rate, _clk_flags, _notif) \163 DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \164 .parent = _parent, .dtable = _dtable, \165 .invalid_rate = _invalid_rate, \166 .max_rate = _max_rate, .flag = (_clk_flags), \167 .notifier = _notif)168#define DEF_MUX(_name, _id, _conf, _parent_names) \169 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \170 .parent_names = _parent_names, \171 .num_parents = ARRAY_SIZE(_parent_names), \172 .mux_flags = CLK_MUX_HIWORD_MASK)173#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \174 DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \175 .parent_names = _parent_names, \176 .num_parents = ARRAY_SIZE(_parent_names), \177 .mux_flags = CLK_MUX_READ_ONLY)178#define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \179 DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \180 .parent_names = _parent_names, \181 .num_parents = ARRAY_SIZE(_parent_names), \182 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier)183#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \184 DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)185#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \186 DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \187 .parent_names = _parent_names, \188 .num_parents = ARRAY_SIZE(_parent_names))189#define DEF_DSI_DIV(_name, _id, _parent, _flag) \190 DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)191 192/**193 * struct rzg2l_mod_clk - Module Clocks definitions194 *195 * @name: handle between common and hardware-specific interfaces196 * @id: clock index in array containing all Core and Module Clocks197 * @parent: id of parent clock198 * @off: register offset199 * @bit: ON/MON bit200 * @is_coupled: flag to indicate coupled clock201 */202struct rzg2l_mod_clk {203 const char *name;204 unsigned int id;205 unsigned int parent;206 u16 off;207 u8 bit;208 bool is_coupled;209};210 211#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \212 { \213 .name = _name, \214 .id = MOD_CLK_BASE + (_id), \215 .parent = (_parent), \216 .off = (_off), \217 .bit = (_bit), \218 .is_coupled = (_is_coupled), \219 }220 221#define DEF_MOD(_name, _id, _parent, _off, _bit) \222 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)223 224#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \225 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)226 227/**228 * struct rzg2l_reset - Reset definitions229 *230 * @off: register offset231 * @bit: reset bit232 * @monbit: monitor bit in CPG_RST_MON register, -1 if none233 */234struct rzg2l_reset {235 u16 off;236 u8 bit;237 s8 monbit;238};239 240#define DEF_RST_MON(_id, _off, _bit, _monbit) \241 [_id] = { \242 .off = (_off), \243 .bit = (_bit), \244 .monbit = (_monbit) \245 }246#define DEF_RST(_id, _off, _bit) \247 DEF_RST_MON(_id, _off, _bit, -1)248 249/**250 * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure251 * @off: register offset252 * @mask: register mask253 */254struct rzg2l_cpg_reg_conf {255 u16 off;256 u16 mask;257};258 259#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })260 261/**262 * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure263 * @mstop: MSTOP register configuration264 */265struct rzg2l_cpg_pm_domain_conf {266 struct rzg2l_cpg_reg_conf mstop;267};268 269/**270 * struct rzg2l_cpg_pm_domain_init_data - PM domain init data271 * @name: PM domain name272 * @conf: PM domain configuration273 * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)274 * @id: PM domain ID (similar to the ones defined in275 * include/dt-bindings/clock/<soc-id>-cpg.h)276 */277struct rzg2l_cpg_pm_domain_init_data {278 const char * const name;279 struct rzg2l_cpg_pm_domain_conf conf;280 u32 flags;281 u16 id;282};283 284#define DEF_PD(_name, _id, _mstop_conf, _flags) \285 { \286 .name = (_name), \287 .id = (_id), \288 .conf = { \289 .mstop = (_mstop_conf), \290 }, \291 .flags = (_flags), \292 }293 294/* Power domain flags. */295#define RZG2L_PD_F_ALWAYS_ON BIT(0)296#define RZG2L_PD_F_NONE (0)297 298/**299 * struct rzg2l_cpg_info - SoC-specific CPG Description300 *301 * @core_clks: Array of Core Clock definitions302 * @num_core_clks: Number of entries in core_clks[]303 * @last_dt_core_clk: ID of the last Core Clock exported to DT304 * @num_total_core_clks: Total number of Core Clocks (exported + internal)305 *306 * @mod_clks: Array of Module Clock definitions307 * @num_mod_clks: Number of entries in mod_clks[]308 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware309 *310 * @resets: Array of Module Reset definitions311 * @num_resets: Number of entries in resets[]312 *313 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that314 * should not be disabled without a knowledgeable driver315 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]316 * @pm_domains: PM domains init data array317 * @num_pm_domains: Number of PM domains318 * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers319 */320struct rzg2l_cpg_info {321 /* Core Clocks */322 const struct cpg_core_clk *core_clks;323 unsigned int num_core_clks;324 unsigned int last_dt_core_clk;325 unsigned int num_total_core_clks;326 327 /* Module Clocks */328 const struct rzg2l_mod_clk *mod_clks;329 unsigned int num_mod_clks;330 unsigned int num_hw_mod_clks;331 332 /* No PM Module Clocks */333 const unsigned int *no_pm_mod_clks;334 unsigned int num_no_pm_mod_clks;335 336 /* Resets */337 const struct rzg2l_reset *resets;338 unsigned int num_resets;339 340 /* Critical Module Clocks that should not be disabled */341 const unsigned int *crit_mod_clks;342 unsigned int num_crit_mod_clks;343 344 /* Power domain. */345 const struct rzg2l_cpg_pm_domain_init_data *pm_domains;346 unsigned int num_pm_domains;347 348 bool has_clk_mon_regs;349};350 351extern const struct rzg2l_cpg_info r9a07g043_cpg_info;352extern const struct rzg2l_cpg_info r9a07g044_cpg_info;353extern const struct rzg2l_cpg_info r9a07g054_cpg_info;354extern const struct rzg2l_cpg_info r9a08g045_cpg_info;355extern const struct rzg2l_cpg_info r9a09g011_cpg_info;356 357int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);358int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data);359 360#endif361