191 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Renesas RZ/V2H(P) Clock Pulse Generator4 *5 * Copyright (C) 2024 Renesas Electronics Corp.6 */7 8#ifndef __RENESAS_RZV2H_CPG_H__9#define __RENESAS_RZV2H_CPG_H__10 11/**12 * struct ddiv - Structure for dynamic switching divider13 *14 * @offset: register offset15 * @shift: position of the divider bit16 * @width: width of the divider17 * @monbit: monitor bit in CPG_CLKSTATUS0 register18 */19struct ddiv {20 unsigned int offset:11;21 unsigned int shift:4;22 unsigned int width:4;23 unsigned int monbit:5;24};25 26#define DDIV_PACK(_offset, _shift, _width, _monbit) \27 ((struct ddiv){ \28 .offset = _offset, \29 .shift = _shift, \30 .width = _width, \31 .monbit = _monbit \32 })33 34#define CPG_CDDIV0 (0x400)35 36#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)37 38/**39 * Definitions of CPG Core Clocks40 *41 * These include:42 * - Clock outputs exported to DT43 * - External input clocks44 * - Internal CPG clocks45 */46struct cpg_core_clk {47 const char *name;48 unsigned int id;49 unsigned int parent;50 unsigned int div;51 unsigned int mult;52 unsigned int type;53 union {54 unsigned int conf;55 struct ddiv ddiv;56 } cfg;57 const struct clk_div_table *dtable;58 u32 flag;59};60 61enum clk_types {62 /* Generic */63 CLK_TYPE_IN, /* External Clock Input */64 CLK_TYPE_FF, /* Fixed Factor Clock */65 CLK_TYPE_PLL,66 CLK_TYPE_DDIV, /* Dynamic Switching Divider */67};68 69/* BIT(31) indicates if CLK1/2 are accessible or not */70#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))71#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)72#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))73#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))74 75#define DEF_TYPE(_name, _id, _type...) \76 { .name = _name, .id = _id, .type = _type }77#define DEF_BASE(_name, _id, _type, _parent...) \78 DEF_TYPE(_name, _id, _type, .parent = _parent)79#define DEF_PLL(_name, _id, _parent, _conf) \80 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)81#define DEF_INPUT(_name, _id) \82 DEF_TYPE(_name, _id, CLK_TYPE_IN)83#define DEF_FIXED(_name, _id, _parent, _mult, _div) \84 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)85#define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \86 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \87 .cfg.ddiv = _ddiv_packed, \88 .parent = _parent, \89 .dtable = _dtable, \90 .flag = CLK_DIVIDER_HIWORD_MASK)91 92/**93 * struct rzv2h_mod_clk - Module Clocks definitions94 *95 * @name: handle between common and hardware-specific interfaces96 * @parent: id of parent clock97 * @critical: flag to indicate the clock is critical98 * @on_index: control register index99 * @on_bit: ON bit100 * @mon_index: monitor register index101 * @mon_bit: monitor bit102 */103struct rzv2h_mod_clk {104 const char *name;105 u16 parent;106 bool critical;107 u8 on_index;108 u8 on_bit;109 s8 mon_index;110 u8 mon_bit;111};112 113#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _monindex, _monbit) \114 { \115 .name = (_name), \116 .parent = (_parent), \117 .critical = (_critical), \118 .on_index = (_onindex), \119 .on_bit = (_onbit), \120 .mon_index = (_monindex), \121 .mon_bit = (_monbit), \122 }123 124#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \125 DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit)126 127#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \128 DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit)129 130/**131 * struct rzv2h_reset - Reset definitions132 *133 * @reset_index: reset register index134 * @reset_bit: reset bit135 * @mon_index: monitor register index136 * @mon_bit: monitor bit137 */138struct rzv2h_reset {139 u8 reset_index;140 u8 reset_bit;141 u8 mon_index;142 u8 mon_bit;143};144 145#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \146 { \147 .reset_index = (_resindex), \148 .reset_bit = (_resbit), \149 .mon_index = (_monindex), \150 .mon_bit = (_monbit), \151 }152 153#define DEF_RST(_resindex, _resbit, _monindex, _monbit) \154 DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)155 156/**157 * struct rzv2h_cpg_info - SoC-specific CPG Description158 *159 * @core_clks: Array of Core Clock definitions160 * @num_core_clks: Number of entries in core_clks[]161 * @last_dt_core_clk: ID of the last Core Clock exported to DT162 * @num_total_core_clks: Total number of Core Clocks (exported + internal)163 *164 * @mod_clks: Array of Module Clock definitions165 * @num_mod_clks: Number of entries in mod_clks[]166 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware167 *168 * @resets: Array of Module Reset definitions169 * @num_resets: Number of entries in resets[]170 */171struct rzv2h_cpg_info {172 /* Core Clocks */173 const struct cpg_core_clk *core_clks;174 unsigned int num_core_clks;175 unsigned int last_dt_core_clk;176 unsigned int num_total_core_clks;177 178 /* Module Clocks */179 const struct rzv2h_mod_clk *mod_clks;180 unsigned int num_mod_clks;181 unsigned int num_hw_mod_clks;182 183 /* Resets */184 const struct rzv2h_reset *resets;185 unsigned int num_resets;186};187 188extern const struct rzv2h_cpg_info r9a09g057_cpg_info;189 190#endif /* __RENESAS_RZV2H_CPG_H__ */191