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1# SPDX-License-Identifier: GPL-2.02#3# Rockchip Clock specific Makefile4#5 6obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o7 8clk-rockchip-y += clk.o9clk-rockchip-y += clk-pll.o10clk-rockchip-y += clk-cpu.o11clk-rockchip-y += clk-half-divider.o12clk-rockchip-y += clk-inverter.o13clk-rockchip-y += clk-mmc-phase.o14clk-rockchip-y += clk-muxgrf.o15clk-rockchip-y += clk-ddr.o16clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o17 18obj-$(CONFIG_CLK_PX30) += clk-px30.o19obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o20obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o21obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o22obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o23obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o24obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o25obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o26obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o27obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o28obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o29obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o30obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o31obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o32obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o33