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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MundoReader S.L.4 * Author: Heiko Stuebner <heiko@sntech.de>5 *6 * based on clk/samsung/clk-cpu.c7 * Copyright (c) 2014 Samsung Electronics Co., Ltd.8 * Author: Thomas Abraham <thomas.ab@samsung.com>9 *10 * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.11 * The CPU clock is typically derived from a hierarchy of clock12 * blocks which includes mux and divider blocks. There are a number of other13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI14 * clock for CPU domain. The rates of these auxiliary clocks are related to the15 * CPU clock rate and this relation is usually specified in the hardware manual16 * of the SoC or supplied after the SoC characterization.17 *18 * The below implementation of the CPU clock allows the rate changes of the CPU19 * clock and the corresponding rate changes of the auxillary clocks of the CPU20 * domain. The platform clock driver provides a clock register configuration21 * for each configurable rate which is then used to program the clock hardware22 * registers to acheive a fast co-oridinated rate change for all the CPU domain23 * clocks.24 *25 * On a rate change request for the CPU clock, the rate change is propagated26 * upto the PLL supplying the clock to the CPU domain clock blocks. While the27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an28 * alternate clock source. If required, the alternate clock source is divided29 * down in order to keep the output clock rate within the previous OPP limits.30 */31 32#include <linux/of.h>33#include <linux/slab.h>34#include <linux/io.h>35#include <linux/clk.h>36#include <linux/clk-provider.h>37#include "clk.h"38 39/**40 * struct rockchip_cpuclk: information about clock supplied to a CPU core.41 * @hw: handle between ccf and cpu clock.42 * @alt_parent: alternate parent clock to use when switching the speed43 * of the primary parent clock.44 * @reg_base: base register for cpu-clock values.45 * @clk_nb: clock notifier registered for changes in clock speed of the46 * primary parent clock.47 * @rate_count: number of rates in the rate_table48 * @rate_table: pll-rates and their associated dividers49 * @reg_data: cpu-specific register settings50 * @lock: clock lock51 */52struct rockchip_cpuclk {53 struct clk_hw hw;54 struct clk *alt_parent;55 void __iomem *reg_base;56 struct notifier_block clk_nb;57 unsigned int rate_count;58 struct rockchip_cpuclk_rate_table *rate_table;59 const struct rockchip_cpuclk_reg_data *reg_data;60 spinlock_t *lock;61};62 63#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)64#define to_rockchip_cpuclk_nb(nb) \65 container_of(nb, struct rockchip_cpuclk, clk_nb)66 67static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(68 struct rockchip_cpuclk *cpuclk, unsigned long rate)69{70 const struct rockchip_cpuclk_rate_table *rate_table =71 cpuclk->rate_table;72 int i;73 74 for (i = 0; i < cpuclk->rate_count; i++) {75 if (rate == rate_table[i].prate)76 return &rate_table[i];77 }78 79 return NULL;80}81 82static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,83 unsigned long parent_rate)84{85 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);88 89 clksel0 >>= reg_data->div_core_shift[0];90 clksel0 &= reg_data->div_core_mask[0];91 return parent_rate / (clksel0 + 1);92}93 94static const struct clk_ops rockchip_cpuclk_ops = {95 .recalc_rate = rockchip_cpuclk_recalc_rate,96};97 98static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,99 const struct rockchip_cpuclk_rate_table *rate)100{101 int i;102 103 /* alternate parent is active now. set the dividers */104 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];106 107 if (!clksel->reg)108 continue;109 110 pr_debug("%s: setting reg 0x%x to 0x%x\n",111 __func__, clksel->reg, clksel->val);112 writel(clksel->val, cpuclk->reg_base + clksel->reg);113 }114}115 116static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,117 const struct rockchip_cpuclk_rate_table *rate)118{119 int i;120 121 /* alternate parent is active now. set the pre_muxs */122 for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];124 125 if (!clksel->reg)126 break;127 128 pr_debug("%s: setting reg 0x%x to 0x%x\n",129 __func__, clksel->reg, clksel->val);130 writel(clksel->val, cpuclk->reg_base + clksel->reg);131 }132}133 134static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,135 const struct rockchip_cpuclk_rate_table *rate)136{137 int i;138 139 /* alternate parent is active now. set the muxs */140 for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {141 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];142 143 if (!clksel->reg)144 break;145 146 pr_debug("%s: setting reg 0x%x to 0x%x\n",147 __func__, clksel->reg, clksel->val);148 writel(clksel->val, cpuclk->reg_base + clksel->reg);149 }150}151 152static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,153 struct clk_notifier_data *ndata)154{155 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;156 const struct rockchip_cpuclk_rate_table *rate;157 unsigned long alt_prate, alt_div;158 unsigned long flags;159 int i = 0;160 161 /* check validity of the new rate */162 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);163 if (!rate) {164 pr_err("%s: Invalid rate : %lu for cpuclk\n",165 __func__, ndata->new_rate);166 return -EINVAL;167 }168 169 alt_prate = clk_get_rate(cpuclk->alt_parent);170 171 spin_lock_irqsave(cpuclk->lock, flags);172 173 /*174 * If the old parent clock speed is less than the clock speed175 * of the alternate parent, then it should be ensured that at no point176 * the armclk speed is more than the old_rate until the dividers are177 * set.178 */179 if (alt_prate > ndata->old_rate) {180 /* calculate dividers */181 alt_div = DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;182 if (alt_div > reg_data->div_core_mask[0]) {183 pr_warn("%s: limiting alt-divider %lu to %d\n",184 __func__, alt_div, reg_data->div_core_mask[0]);185 alt_div = reg_data->div_core_mask[0];186 }187 188 /*189 * Change parents and add dividers in a single transaction.190 *191 * NOTE: we do this in a single transaction so we're never192 * dividing the primary parent by the extra dividers that were193 * needed for the alt.194 */195 pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",196 __func__, alt_div, alt_prate, ndata->old_rate);197 198 for (i = 0; i < reg_data->num_cores; i++) {199 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],200 reg_data->div_core_shift[i]),201 cpuclk->reg_base + reg_data->core_reg[i]);202 }203 }204 205 rockchip_cpuclk_set_pre_muxs(cpuclk, rate);206 207 /* select alternate parent */208 if (reg_data->mux_core_reg)209 writel(HIWORD_UPDATE(reg_data->mux_core_alt,210 reg_data->mux_core_mask,211 reg_data->mux_core_shift),212 cpuclk->reg_base + reg_data->mux_core_reg);213 else214 writel(HIWORD_UPDATE(reg_data->mux_core_alt,215 reg_data->mux_core_mask,216 reg_data->mux_core_shift),217 cpuclk->reg_base + reg_data->core_reg[0]);218 219 spin_unlock_irqrestore(cpuclk->lock, flags);220 return 0;221}222 223static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,224 struct clk_notifier_data *ndata)225{226 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;227 const struct rockchip_cpuclk_rate_table *rate;228 unsigned long flags;229 int i = 0;230 231 rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);232 if (!rate) {233 pr_err("%s: Invalid rate : %lu for cpuclk\n",234 __func__, ndata->new_rate);235 return -EINVAL;236 }237 238 spin_lock_irqsave(cpuclk->lock, flags);239 240 if (ndata->old_rate < ndata->new_rate)241 rockchip_cpuclk_set_dividers(cpuclk, rate);242 243 /*244 * post-rate change event, re-mux to primary parent and remove dividers.245 *246 * NOTE: we do this in a single transaction so we're never dividing the247 * primary parent by the extra dividers that were needed for the alt.248 */249 250 if (reg_data->mux_core_reg)251 writel(HIWORD_UPDATE(reg_data->mux_core_main,252 reg_data->mux_core_mask,253 reg_data->mux_core_shift),254 cpuclk->reg_base + reg_data->mux_core_reg);255 else256 writel(HIWORD_UPDATE(reg_data->mux_core_main,257 reg_data->mux_core_mask,258 reg_data->mux_core_shift),259 cpuclk->reg_base + reg_data->core_reg[0]);260 261 rockchip_cpuclk_set_post_muxs(cpuclk, rate);262 263 /* remove dividers */264 for (i = 0; i < reg_data->num_cores; i++) {265 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],266 reg_data->div_core_shift[i]),267 cpuclk->reg_base + reg_data->core_reg[i]);268 }269 270 if (ndata->old_rate > ndata->new_rate)271 rockchip_cpuclk_set_dividers(cpuclk, rate);272 273 spin_unlock_irqrestore(cpuclk->lock, flags);274 return 0;275}276 277/*278 * This clock notifier is called when the frequency of the parent clock279 * of cpuclk is to be changed. This notifier handles the setting up all280 * the divider clocks, remux to temporary parent and handling the safe281 * frequency levels when using temporary parent.282 */283static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,284 unsigned long event, void *data)285{286 struct clk_notifier_data *ndata = data;287 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);288 int ret = 0;289 290 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",291 __func__, event, ndata->old_rate, ndata->new_rate);292 if (event == PRE_RATE_CHANGE)293 ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);294 else if (event == POST_RATE_CHANGE)295 ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);296 297 return notifier_from_errno(ret);298}299 300struct clk *rockchip_clk_register_cpuclk(const char *name,301 const char *const *parent_names, u8 num_parents,302 const struct rockchip_cpuclk_reg_data *reg_data,303 const struct rockchip_cpuclk_rate_table *rates,304 int nrates, void __iomem *reg_base, spinlock_t *lock)305{306 struct rockchip_cpuclk *cpuclk;307 struct clk_init_data init;308 struct clk *clk, *cclk;309 int ret;310 311 if (num_parents < 2) {312 pr_err("%s: needs at least two parent clocks\n", __func__);313 return ERR_PTR(-EINVAL);314 }315 316 cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);317 if (!cpuclk)318 return ERR_PTR(-ENOMEM);319 320 init.name = name;321 init.parent_names = &parent_names[reg_data->mux_core_main];322 init.num_parents = 1;323 init.ops = &rockchip_cpuclk_ops;324 325 /* only allow rate changes when we have a rate table */326 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;327 328 /* disallow automatic parent changes by ccf */329 init.flags |= CLK_SET_RATE_NO_REPARENT;330 331 init.flags |= CLK_GET_RATE_NOCACHE;332 333 cpuclk->reg_base = reg_base;334 cpuclk->lock = lock;335 cpuclk->reg_data = reg_data;336 cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;337 cpuclk->hw.init = &init;338 339 cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);340 if (!cpuclk->alt_parent) {341 pr_err("%s: could not lookup alternate parent: (%d)\n",342 __func__, reg_data->mux_core_alt);343 ret = -EINVAL;344 goto free_cpuclk;345 }346 347 ret = clk_prepare_enable(cpuclk->alt_parent);348 if (ret) {349 pr_err("%s: could not enable alternate parent\n",350 __func__);351 goto free_cpuclk;352 }353 354 clk = __clk_lookup(parent_names[reg_data->mux_core_main]);355 if (!clk) {356 pr_err("%s: could not lookup parent clock: (%d) %s\n",357 __func__, reg_data->mux_core_main,358 parent_names[reg_data->mux_core_main]);359 ret = -EINVAL;360 goto free_alt_parent;361 }362 363 ret = clk_notifier_register(clk, &cpuclk->clk_nb);364 if (ret) {365 pr_err("%s: failed to register clock notifier for %s\n",366 __func__, name);367 goto free_alt_parent;368 }369 370 if (nrates > 0) {371 cpuclk->rate_count = nrates;372 cpuclk->rate_table = kmemdup_array(rates, nrates, sizeof(*rates),373 GFP_KERNEL);374 if (!cpuclk->rate_table) {375 ret = -ENOMEM;376 goto unregister_notifier;377 }378 }379 380 cclk = clk_register(NULL, &cpuclk->hw);381 if (IS_ERR(cclk)) {382 pr_err("%s: could not register cpuclk %s\n", __func__, name);383 ret = PTR_ERR(cclk);384 goto free_rate_table;385 }386 387 return cclk;388 389free_rate_table:390 kfree(cpuclk->rate_table);391unregister_notifier:392 clk_notifier_unregister(clk, &cpuclk->clk_nb);393free_alt_parent:394 clk_disable_unprepare(cpuclk->alt_parent);395free_cpuclk:396 kfree(cpuclk);397 return ERR_PTR(ret);398}399