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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright 2014 Google, Inc4 * Author: Alexandru M Stan <amstan@chromium.org>5 */6 7#include <linux/slab.h>8#include <linux/clk.h>9#include <linux/clk-provider.h>10#include <linux/io.h>11#include <linux/kernel.h>12#include "clk.h"13 14struct rockchip_mmc_clock {15 struct clk_hw hw;16 void __iomem *reg;17 int shift;18 int cached_phase;19 struct notifier_block clk_rate_change_nb;20};21 22#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)23 24#define RK3288_MMC_CLKGEN_DIV 225 26static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,27 unsigned long parent_rate)28{29 return parent_rate / RK3288_MMC_CLKGEN_DIV;30}31 32#define ROCKCHIP_MMC_DELAY_SEL BIT(10)33#define ROCKCHIP_MMC_DEGREE_MASK 0x334#define ROCKCHIP_MMC_DELAYNUM_OFFSET 235#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)36 37#define PSECS_PER_SEC 1000000000000LL38 39/*40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to41 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.42 */43#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 6044 45static int rockchip_mmc_get_phase(struct clk_hw *hw)46{47 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);48 unsigned long rate = clk_hw_get_rate(hw);49 u32 raw_value;50 u16 degrees;51 u32 delay_num = 0;52 53 /* Constant signal, no measurable phase shift */54 if (!rate)55 return 0;56 57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);58 59 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;60 61 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {62 /* degrees/delaynum * 1000000 */63 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *64 36 * (rate / 10000);65 66 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);67 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;68 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);69 }70 71 return degrees % 360;72}73 74static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)75{76 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);77 unsigned long rate = clk_hw_get_rate(hw);78 u8 nineties, remainder;79 u8 delay_num;80 u32 raw_value;81 u32 delay;82 83 /*84 * The below calculation is based on the output clock from85 * MMC host to the card, which expects the phase clock inherits86 * the clock rate from its parent, namely the output clock87 * provider of MMC host. However, things may go wrong if88 * (1) It is orphan.89 * (2) It is assigned to the wrong parent.90 *91 * This check help debug the case (1), which seems to be the92 * most likely problem we often face and which makes it difficult93 * for people to debug unstable mmc tuning results.94 */95 if (!rate) {96 pr_err("%s: invalid clk rate\n", __func__);97 return -EINVAL;98 }99 100 nineties = degrees / 90;101 remainder = (degrees % 90);102 103 /*104 * Due to the inexact nature of the "fine" delay, we might105 * actually go non-monotonic. We don't go _too_ monotonic106 * though, so we should be OK. Here are options of how we may107 * work:108 *109 * Ideally we end up with:110 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0111 *112 * On one extreme (if delay is actually 44ps):113 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0114 * The other (if delay is actually 77ps):115 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90116 *117 * It's possible we might make a delay that is up to 25118 * degrees off from what we think we're making. That's OK119 * though because we should be REALLY far from any bad range.120 */121 122 /*123 * Convert to delay; do a little extra work to make sure we124 * don't overflow 32-bit / 64-bit numbers.125 */126 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */127 delay *= remainder;128 delay = DIV_ROUND_CLOSEST(delay,129 (rate / 1000) * 36 *130 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));131 132 delay_num = (u8) min_t(u32, delay, 255);133 134 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;135 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;136 raw_value |= nineties;137 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),138 mmc_clock->reg);139 140 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",141 clk_hw_get_name(hw), degrees, delay_num,142 mmc_clock->reg, raw_value>>(mmc_clock->shift),143 rockchip_mmc_get_phase(hw)144 );145 146 return 0;147}148 149static const struct clk_ops rockchip_mmc_clk_ops = {150 .recalc_rate = rockchip_mmc_recalc,151 .get_phase = rockchip_mmc_get_phase,152 .set_phase = rockchip_mmc_set_phase,153};154 155#define to_rockchip_mmc_clock(x) \156 container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)157static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,158 unsigned long event, void *data)159{160 struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);161 struct clk_notifier_data *ndata = data;162 163 /*164 * rockchip_mmc_clk is mostly used by mmc controllers to sample165 * the intput data, which expects the fixed phase after the tuning166 * process. However if the clock rate is changed, the phase is stale167 * and may break the data sampling. So here we try to restore the phase168 * for that case, except that169 * (1) cached_phase is invaild since we inevitably cached it when the170 * clock provider be reparented from orphan to its real parent in the171 * first place. Otherwise we may mess up the initialization of MMC cards172 * since we only set the default sample phase and drive phase later on.173 * (2) the new coming rate is higher than the older one since mmc driver174 * set the max-frequency to match the boards' ability but we can't go175 * over the heads of that, otherwise the tests smoke out the issue.176 */177 if (ndata->old_rate <= ndata->new_rate)178 return NOTIFY_DONE;179 180 if (event == PRE_RATE_CHANGE)181 mmc_clock->cached_phase =182 rockchip_mmc_get_phase(&mmc_clock->hw);183 else if (mmc_clock->cached_phase != -EINVAL &&184 event == POST_RATE_CHANGE)185 rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);186 187 return NOTIFY_DONE;188}189 190struct clk *rockchip_clk_register_mmc(const char *name,191 const char *const *parent_names, u8 num_parents,192 void __iomem *reg, int shift)193{194 struct clk_init_data init;195 struct rockchip_mmc_clock *mmc_clock;196 struct clk *clk;197 int ret;198 199 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);200 if (!mmc_clock)201 return ERR_PTR(-ENOMEM);202 203 init.name = name;204 init.flags = 0;205 init.num_parents = num_parents;206 init.parent_names = parent_names;207 init.ops = &rockchip_mmc_clk_ops;208 209 mmc_clock->hw.init = &init;210 mmc_clock->reg = reg;211 mmc_clock->shift = shift;212 213 clk = clk_register(NULL, &mmc_clock->hw);214 if (IS_ERR(clk)) {215 ret = PTR_ERR(clk);216 goto err_register;217 }218 219 mmc_clock->clk_rate_change_nb.notifier_call =220 &rockchip_mmc_clk_rate_notify;221 ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);222 if (ret)223 goto err_notifier;224 225 return clk;226err_notifier:227 clk_unregister(clk);228err_register:229 kfree(mmc_clock);230 return ERR_PTR(ret);231}232