995 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (c) 2014 MundoReader S.L.4 * Author: Heiko Stuebner <heiko@sntech.de>5 */6 7#include <linux/clk-provider.h>8#include <linux/io.h>9#include <linux/of.h>10#include <linux/of_address.h>11#include <linux/syscore_ops.h>12#include <dt-bindings/clock/rk3288-cru.h>13#include "clk.h"14 15#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)16#define RK3288_GRF_SOC_STATUS1 0x28417 18enum rk3288_variant {19 RK3288_CRU,20 RK3288W_CRU,21};22 23enum rk3288_plls {24 apll, dpll, cpll, gpll, npll,25};26 27static struct rockchip_pll_rate_table rk3288_pll_rates[] = {28 RK3066_PLL_RATE(2208000000, 1, 92, 1),29 RK3066_PLL_RATE(2184000000, 1, 91, 1),30 RK3066_PLL_RATE(2160000000, 1, 90, 1),31 RK3066_PLL_RATE(2136000000, 1, 89, 1),32 RK3066_PLL_RATE(2112000000, 1, 88, 1),33 RK3066_PLL_RATE(2088000000, 1, 87, 1),34 RK3066_PLL_RATE(2064000000, 1, 86, 1),35 RK3066_PLL_RATE(2040000000, 1, 85, 1),36 RK3066_PLL_RATE(2016000000, 1, 84, 1),37 RK3066_PLL_RATE(1992000000, 1, 83, 1),38 RK3066_PLL_RATE(1968000000, 1, 82, 1),39 RK3066_PLL_RATE(1944000000, 1, 81, 1),40 RK3066_PLL_RATE(1920000000, 1, 80, 1),41 RK3066_PLL_RATE(1896000000, 1, 79, 1),42 RK3066_PLL_RATE(1872000000, 1, 78, 1),43 RK3066_PLL_RATE(1848000000, 1, 77, 1),44 RK3066_PLL_RATE(1824000000, 1, 76, 1),45 RK3066_PLL_RATE(1800000000, 1, 75, 1),46 RK3066_PLL_RATE(1776000000, 1, 74, 1),47 RK3066_PLL_RATE(1752000000, 1, 73, 1),48 RK3066_PLL_RATE(1728000000, 1, 72, 1),49 RK3066_PLL_RATE(1704000000, 1, 71, 1),50 RK3066_PLL_RATE(1680000000, 1, 70, 1),51 RK3066_PLL_RATE(1656000000, 1, 69, 1),52 RK3066_PLL_RATE(1632000000, 1, 68, 1),53 RK3066_PLL_RATE(1608000000, 1, 67, 1),54 RK3066_PLL_RATE(1560000000, 1, 65, 1),55 RK3066_PLL_RATE(1512000000, 1, 63, 1),56 RK3066_PLL_RATE(1488000000, 1, 62, 1),57 RK3066_PLL_RATE(1464000000, 1, 61, 1),58 RK3066_PLL_RATE(1440000000, 1, 60, 1),59 RK3066_PLL_RATE(1416000000, 1, 59, 1),60 RK3066_PLL_RATE(1392000000, 1, 58, 1),61 RK3066_PLL_RATE(1368000000, 1, 57, 1),62 RK3066_PLL_RATE(1344000000, 1, 56, 1),63 RK3066_PLL_RATE(1320000000, 1, 55, 1),64 RK3066_PLL_RATE(1296000000, 1, 54, 1),65 RK3066_PLL_RATE(1272000000, 1, 53, 1),66 RK3066_PLL_RATE(1248000000, 1, 52, 1),67 RK3066_PLL_RATE(1224000000, 1, 51, 1),68 RK3066_PLL_RATE(1200000000, 1, 50, 1),69 RK3066_PLL_RATE(1188000000, 2, 99, 1),70 RK3066_PLL_RATE(1176000000, 1, 49, 1),71 RK3066_PLL_RATE(1128000000, 1, 47, 1),72 RK3066_PLL_RATE(1104000000, 1, 46, 1),73 RK3066_PLL_RATE(1008000000, 1, 84, 2),74 RK3066_PLL_RATE( 912000000, 1, 76, 2),75 RK3066_PLL_RATE( 891000000, 8, 594, 2),76 RK3066_PLL_RATE( 888000000, 1, 74, 2),77 RK3066_PLL_RATE( 816000000, 1, 68, 2),78 RK3066_PLL_RATE( 798000000, 2, 133, 2),79 RK3066_PLL_RATE( 792000000, 1, 66, 2),80 RK3066_PLL_RATE( 768000000, 1, 64, 2),81 RK3066_PLL_RATE( 742500000, 8, 495, 2),82 RK3066_PLL_RATE( 696000000, 1, 58, 2),83 RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),84 RK3066_PLL_RATE( 600000000, 1, 50, 2),85 RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),86 RK3066_PLL_RATE( 552000000, 1, 46, 2),87 RK3066_PLL_RATE( 504000000, 1, 84, 4),88 RK3066_PLL_RATE( 500000000, 3, 125, 2),89 RK3066_PLL_RATE( 456000000, 1, 76, 4),90 RK3066_PLL_RATE( 428000000, 1, 107, 6),91 RK3066_PLL_RATE( 408000000, 1, 68, 4),92 RK3066_PLL_RATE( 400000000, 3, 100, 2),93 RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),94 RK3066_PLL_RATE( 384000000, 2, 128, 4),95 RK3066_PLL_RATE( 360000000, 1, 60, 4),96 RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),97 RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),98 RK3066_PLL_RATE( 312000000, 1, 52, 4),99 RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),100 RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),101 RK3066_PLL_RATE( 300000000, 1, 75, 6),102 RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),103 RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),104 RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),105 RK3066_PLL_RATE( 273600000, 1, 114, 10),106 RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),107 RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),108 RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),109 RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),110 RK3066_PLL_RATE( 252000000, 1, 84, 8),111 RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),112 RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),113 RK3066_PLL_RATE( 238000000, 1, 119, 12),114 RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),115 RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),116 RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),117 RK3066_PLL_RATE( 195428571, 1, 114, 14),118 RK3066_PLL_RATE( 160000000, 1, 80, 12),119 RK3066_PLL_RATE( 157500000, 1, 105, 16),120 RK3066_PLL_RATE( 126000000, 1, 84, 16),121 { /* sentinel */ },122};123 124#define RK3288_DIV_ACLK_CORE_M0_MASK 0xf125#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0126#define RK3288_DIV_ACLK_CORE_MP_MASK 0xf127#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4128#define RK3288_DIV_L2RAM_MASK 0x7129#define RK3288_DIV_L2RAM_SHIFT 0130#define RK3288_DIV_ATCLK_MASK 0x1f131#define RK3288_DIV_ATCLK_SHIFT 4132#define RK3288_DIV_PCLK_DBGPRE_MASK 0x1f133#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9134 135#define RK3288_CLKSEL0(_core_m0, _core_mp) \136 { \137 .reg = RK3288_CLKSEL_CON(0), \138 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \139 RK3288_DIV_ACLK_CORE_M0_SHIFT) | \140 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \141 RK3288_DIV_ACLK_CORE_MP_SHIFT), \142 }143#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \144 { \145 .reg = RK3288_CLKSEL_CON(37), \146 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \147 RK3288_DIV_L2RAM_SHIFT) | \148 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \149 RK3288_DIV_ATCLK_SHIFT) | \150 HIWORD_UPDATE(_pclk_dbg_pre, \151 RK3288_DIV_PCLK_DBGPRE_MASK, \152 RK3288_DIV_PCLK_DBGPRE_SHIFT), \153 }154 155#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \156 { \157 .prate = _prate, \158 .divs = { \159 RK3288_CLKSEL0(_core_m0, _core_mp), \160 RK3288_CLKSEL37(_l2ram, _atclk, _pdbg), \161 }, \162 }163 164static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {165 RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),166 RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),167 RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),168 RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),169 RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),170 RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),171 RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),172 RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),173 RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),174 RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),175 RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),176 RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),177 RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),178 RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),179};180 181static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {182 .core_reg[0] = RK3288_CLKSEL_CON(0),183 .div_core_shift[0] = 8,184 .div_core_mask[0] = 0x1f,185 .num_cores = 1,186 .mux_core_alt = 1,187 .mux_core_main = 0,188 .mux_core_shift = 15,189 .mux_core_mask = 0x1,190};191 192PNAME(mux_pll_p) = { "xin24m", "xin32k" };193PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };194PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };195PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };196 197PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };198PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };199PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };200PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };201PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };202 203PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };204PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };205PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };206PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };207PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };208PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };209PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };210PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };211PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };212PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };213PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };214PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };215PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };216PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };217PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };218 219PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };220PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",221 "sclk_otgphy0_480m" };222PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };223PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };224 225static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {226 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),227 RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),228 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),229 RK3288_MODE_CON, 4, 5, 0, NULL),230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),231 RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),233 RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),234 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),235 RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),236};237 238static struct clk_div_table div_hclk_cpu_t[] = {239 { .val = 0, .div = 1 },240 { .val = 1, .div = 2 },241 { .val = 3, .div = 4 },242 { /* sentinel */},243};244 245#define MFLAGS CLK_MUX_HIWORD_MASK246#define DFLAGS CLK_DIVIDER_HIWORD_MASK247#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)248#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK249 250static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =251 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,252 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);253 254static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =255 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,256 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);257 258static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =259 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,260 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);261 262static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =263 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,264 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);265 266static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =267 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,268 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);269 270static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =271 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,272 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);273 274static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =275 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,276 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);277 278static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =279 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,280 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);281 282static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {283 /*284 * Clock-Architecture Diagram 1285 */286 287 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,288 RK3288_CLKGATE_CON(0), 1, GFLAGS),289 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,290 RK3288_CLKGATE_CON(0), 2, GFLAGS),291 292 COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,293 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,294 RK3288_CLKGATE_CON(12), 0, GFLAGS),295 COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,296 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,297 RK3288_CLKGATE_CON(12), 1, GFLAGS),298 COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,299 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,300 RK3288_CLKGATE_CON(12), 2, GFLAGS),301 COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,302 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,303 RK3288_CLKGATE_CON(12), 3, GFLAGS),304 COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,305 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,306 RK3288_CLKGATE_CON(12), 4, GFLAGS),307 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,308 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,309 RK3288_CLKGATE_CON(12), 5, GFLAGS),310 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,311 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,312 RK3288_CLKGATE_CON(12), 6, GFLAGS),313 COMPOSITE_NOMUX(0, "atclk", "armclk", 0,314 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,315 RK3288_CLKGATE_CON(12), 7, GFLAGS),316 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,317 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,318 RK3288_CLKGATE_CON(12), 8, GFLAGS),319 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,320 RK3288_CLKGATE_CON(12), 9, GFLAGS),321 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,322 RK3288_CLKGATE_CON(12), 10, GFLAGS),323 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,324 RK3288_CLKGATE_CON(12), 11, GFLAGS),325 326 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,327 RK3288_CLKGATE_CON(0), 8, GFLAGS),328 GATE(0, "gpll_ddr", "gpll", 0,329 RK3288_CLKGATE_CON(0), 9, GFLAGS),330 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,331 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,332 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),333 334 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,335 RK3288_CLKGATE_CON(0), 10, GFLAGS),336 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,337 RK3288_CLKGATE_CON(0), 11, GFLAGS),338 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,339 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),340 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,341 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),342 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,343 RK3288_CLKGATE_CON(0), 3, GFLAGS),344 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,345 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,346 RK3288_CLKGATE_CON(0), 5, GFLAGS),347 COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,348 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,349 RK3288_CLKGATE_CON(0), 4, GFLAGS),350 GATE(0, "c2c_host", "aclk_cpu_src", 0,351 RK3288_CLKGATE_CON(13), 8, GFLAGS),352 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,353 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,354 RK3288_CLKGATE_CON(5), 4, GFLAGS),355 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,356 RK3288_CLKGATE_CON(0), 7, GFLAGS),357 358 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),359 360 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,361 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,362 RK3288_CLKGATE_CON(4), 1, GFLAGS),363 COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,364 RK3288_CLKSEL_CON(8), 0,365 RK3288_CLKGATE_CON(4), 2, GFLAGS,366 &rk3288_i2s_fracmux),367 COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,368 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,369 RK3288_CLKGATE_CON(4), 0, GFLAGS),370 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,371 RK3288_CLKGATE_CON(4), 3, GFLAGS),372 373 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,374 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),375 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,376 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,377 RK3288_CLKGATE_CON(4), 4, GFLAGS),378 COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,379 RK3288_CLKSEL_CON(9), 0,380 RK3288_CLKGATE_CON(4), 5, GFLAGS,381 &rk3288_spdif_fracmux),382 GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,383 RK3288_CLKGATE_CON(4), 6, GFLAGS),384 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,385 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,386 RK3288_CLKGATE_CON(4), 7, GFLAGS),387 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,388 RK3288_CLKSEL_CON(41), 0,389 RK3288_CLKGATE_CON(4), 8, GFLAGS,390 &rk3288_spdif_8ch_fracmux),391 GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,392 RK3288_CLKGATE_CON(4), 9, GFLAGS),393 394 GATE(0, "sclk_acc_efuse", "xin24m", 0,395 RK3288_CLKGATE_CON(0), 12, GFLAGS),396 397 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,398 RK3288_CLKGATE_CON(1), 0, GFLAGS),399 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,400 RK3288_CLKGATE_CON(1), 1, GFLAGS),401 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,402 RK3288_CLKGATE_CON(1), 2, GFLAGS),403 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,404 RK3288_CLKGATE_CON(1), 3, GFLAGS),405 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,406 RK3288_CLKGATE_CON(1), 4, GFLAGS),407 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,408 RK3288_CLKGATE_CON(1), 5, GFLAGS),409 410 /*411 * Clock-Architecture Diagram 2412 */413 414 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,415 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,416 RK3288_CLKGATE_CON(3), 9, GFLAGS),417 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,418 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,419 RK3288_CLKGATE_CON(3), 11, GFLAGS),420 MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,421 RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),422 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,423 RK3288_CLKGATE_CON(9), 0, GFLAGS),424 425 FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,426 RK3288_CLKGATE_CON(3), 10, GFLAGS),427 428 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,429 RK3288_CLKGATE_CON(9), 1, GFLAGS),430 431 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,432 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,433 RK3288_CLKGATE_CON(3), 0, GFLAGS),434 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,435 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,436 RK3288_CLKGATE_CON(3), 2, GFLAGS),437 438 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,439 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,440 RK3288_CLKGATE_CON(3), 5, GFLAGS),441 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,442 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,443 RK3288_CLKGATE_CON(3), 4, GFLAGS),444 445 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,446 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,447 RK3288_CLKGATE_CON(3), 1, GFLAGS),448 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,449 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,450 RK3288_CLKGATE_CON(3), 3, GFLAGS),451 452 COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,453 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,454 RK3288_CLKGATE_CON(3), 12, GFLAGS),455 COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,456 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,457 RK3288_CLKGATE_CON(3), 13, GFLAGS),458 459 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,460 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,461 RK3288_CLKGATE_CON(3), 14, GFLAGS),462 COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,463 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,464 RK3288_CLKGATE_CON(3), 15, GFLAGS),465 466 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,467 RK3288_CLKGATE_CON(5), 12, GFLAGS),468 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,469 RK3288_CLKGATE_CON(5), 11, GFLAGS),470 471 COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,472 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,473 RK3288_CLKGATE_CON(13), 13, GFLAGS),474 DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,475 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),476 477 COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,478 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,479 RK3288_CLKGATE_CON(13), 14, GFLAGS),480 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,481 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,482 RK3288_CLKGATE_CON(13), 15, GFLAGS),483 484 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,485 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,486 RK3288_CLKGATE_CON(3), 7, GFLAGS),487 COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,488 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),489 490 DIV(0, "pclk_pd_alive", "gpll", 0,491 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),492 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,493 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,494 RK3288_CLKGATE_CON(5), 8, GFLAGS),495 496 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,497 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,498 RK3288_CLKGATE_CON(5), 7, GFLAGS),499 500 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,501 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,502 RK3288_CLKGATE_CON(2), 0, GFLAGS),503 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,504 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,505 RK3288_CLKGATE_CON(2), 3, GFLAGS),506 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,507 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,508 RK3288_CLKGATE_CON(2), 2, GFLAGS),509 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,510 RK3288_CLKGATE_CON(2), 1, GFLAGS),511 512 /*513 * Clock-Architecture Diagram 3514 */515 516 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,517 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,518 RK3288_CLKGATE_CON(2), 9, GFLAGS),519 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,520 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,521 RK3288_CLKGATE_CON(2), 10, GFLAGS),522 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,523 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,524 RK3288_CLKGATE_CON(2), 11, GFLAGS),525 526 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,527 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,528 RK3288_CLKGATE_CON(13), 0, GFLAGS),529 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,530 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,531 RK3288_CLKGATE_CON(13), 1, GFLAGS),532 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,533 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,534 RK3288_CLKGATE_CON(13), 2, GFLAGS),535 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,536 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,537 RK3288_CLKGATE_CON(13), 3, GFLAGS),538 539 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0, 1),540 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),541 542 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1),543 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),544 545 MMC(SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1),546 MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),547 548 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),549 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),550 551 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,552 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,553 RK3288_CLKGATE_CON(4), 11, GFLAGS),554 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,555 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,556 RK3288_CLKGATE_CON(4), 10, GFLAGS),557 558 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,559 RK3288_CLKGATE_CON(13), 4, GFLAGS),560 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,561 RK3288_CLKGATE_CON(13), 5, GFLAGS),562 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,563 RK3288_CLKGATE_CON(13), 6, GFLAGS),564 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,565 RK3288_CLKGATE_CON(13), 7, GFLAGS),566 567 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,568 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,569 RK3288_CLKGATE_CON(2), 7, GFLAGS),570 571 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,572 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,573 RK3288_CLKGATE_CON(2), 8, GFLAGS),574 575 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,576 RK3288_CLKGATE_CON(5), 13, GFLAGS),577 578 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,579 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,580 RK3288_CLKGATE_CON(5), 5, GFLAGS),581 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,582 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,583 RK3288_CLKGATE_CON(5), 6, GFLAGS),584 585 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,586 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,587 RK3288_CLKGATE_CON(1), 8, GFLAGS),588 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,589 RK3288_CLKSEL_CON(17), 0,590 RK3288_CLKGATE_CON(1), 9, GFLAGS,591 &rk3288_uart0_fracmux),592 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,593 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),594 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,595 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,596 RK3288_CLKGATE_CON(1), 10, GFLAGS),597 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,598 RK3288_CLKSEL_CON(18), 0,599 RK3288_CLKGATE_CON(1), 11, GFLAGS,600 &rk3288_uart1_fracmux),601 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,602 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,603 RK3288_CLKGATE_CON(1), 12, GFLAGS),604 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,605 RK3288_CLKSEL_CON(19), 0,606 RK3288_CLKGATE_CON(1), 13, GFLAGS,607 &rk3288_uart2_fracmux),608 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,609 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,610 RK3288_CLKGATE_CON(1), 14, GFLAGS),611 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,612 RK3288_CLKSEL_CON(20), 0,613 RK3288_CLKGATE_CON(1), 15, GFLAGS,614 &rk3288_uart3_fracmux),615 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,616 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,617 RK3288_CLKGATE_CON(2), 12, GFLAGS),618 COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,619 RK3288_CLKSEL_CON(7), 0,620 RK3288_CLKGATE_CON(2), 13, GFLAGS,621 &rk3288_uart4_fracmux),622 623 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,624 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,625 RK3288_CLKGATE_CON(2), 5, GFLAGS),626 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,627 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),628 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,629 RK3288_CLKGATE_CON(5), 3, GFLAGS),630 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,631 RK3288_CLKGATE_CON(5), 2, GFLAGS),632 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,633 RK3288_CLKGATE_CON(5), 0, GFLAGS),634 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,635 RK3288_CLKGATE_CON(5), 1, GFLAGS),636 637 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,638 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,639 RK3288_CLKGATE_CON(2), 6, GFLAGS),640 MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,641 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),642 INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",643 RK3288_CLKSEL_CON(22), 7, IFLAGS),644 645 GATE(0, "jtag", "ext_jtag", 0,646 RK3288_CLKGATE_CON(4), 14, GFLAGS),647 648 COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,649 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,650 RK3288_CLKGATE_CON(5), 14, GFLAGS),651 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,652 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,653 RK3288_CLKGATE_CON(3), 6, GFLAGS),654 GATE(0, "hsicphy12m_xin12m", "xin12m", 0,655 RK3288_CLKGATE_CON(13), 9, GFLAGS),656 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,657 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),658 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,659 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),660 661 /*662 * Clock-Architecture Diagram 4663 */664 665 /* aclk_cpu gates */666 GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),667 GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),668 GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),669 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),670 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),671 GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),672 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),673 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),674 675 /* hclk_cpu gates */676 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),677 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),678 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),679 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),680 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),681 682 /* pclk_cpu gates */683 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),684 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),685 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),686 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),687 GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),688 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),689 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),690 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),691 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),692 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),693 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),694 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),695 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),696 697 /* ddrctrl [DDR Controller PHY clock] gates */698 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),699 GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),700 701 /* ddrphy gates */702 GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),703 GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),704 705 /* aclk_peri gates */706 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),707 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),708 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),709 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),710 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),711 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),712 713 /* hclk_peri gates */714 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),715 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),716 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),717 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),718 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),719 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),720 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),721 GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),722 GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),723 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),724 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),725 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),726 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),727 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),728 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),729 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),730 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),731 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),732 733 /* pclk_peri gates */734 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),735 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),736 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),737 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),738 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),739 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),740 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),741 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),742 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),743 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),744 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),745 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),746 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),747 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),748 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),749 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),750 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),751 752 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),753 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),754 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),755 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),756 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),757 758 /* sclk_gpu gates */759 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),760 761 /* pclk_pd_alive gates */762 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),763 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),764 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),765 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),766 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),767 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),768 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),769 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),770 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),771 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),772 773 /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */774 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),775 776 /* pclk_pd_pmu gates */777 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),778 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),779 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),780 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),781 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),782 783 /* hclk_vio gates */784 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),785 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),786 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),787 GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),788 GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),789 GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),790 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),791 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),792 GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),793 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),794 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),795 GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),796 GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),797 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),798 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),799 GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),800 801 /* aclk_vio0 gates */802 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),803 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),804 GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),805 GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),806 807 /* aclk_vio1 gates */808 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),809 GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),810 GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),811 812 /* aclk_rga_pre gates */813 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),814 GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),815 816 /*817 * Other ungrouped clocks.818 */819 820 GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),821 INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),822 GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),823 INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),824};825 826static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {827 DIV(0, "hclk_vio", "aclk_vio1", 0,828 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),829};830 831static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {832 DIV(0, "hclk_vio", "aclk_vio0", 0,833 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),834};835 836static const char *const rk3288_critical_clocks[] __initconst = {837 "aclk_cpu",838 "aclk_peri",839 "aclk_peri_niu",840 "aclk_vio0_niu",841 "aclk_vio1_niu",842 "aclk_rga_niu",843 "hclk_peri",844 "hclk_vio_niu",845 "pclk_alive_niu",846 "pclk_pd_pmu",847 "pclk_pmu_niu",848 "pmu_hclk_otg0",849 /* pwm-regulators on some boards, so handoff-critical later */850 "pclk_rkpwm",851};852 853static void __iomem *rk3288_cru_base;854 855/*856 * Some CRU registers will be reset in maskrom when the system857 * wakes up from fastboot.858 * So save them before suspend, restore them after resume.859 */860static const int rk3288_saved_cru_reg_ids[] = {861 RK3288_MODE_CON,862 RK3288_CLKSEL_CON(0),863 RK3288_CLKSEL_CON(1),864 RK3288_CLKSEL_CON(10),865 RK3288_CLKSEL_CON(33),866 RK3288_CLKSEL_CON(37),867 868 /* We turn aclk_dmac1 on for suspend; this will restore it */869 RK3288_CLKGATE_CON(10),870};871 872static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];873 874static int rk3288_clk_suspend(void)875{876 int i, reg_id;877 878 for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {879 reg_id = rk3288_saved_cru_reg_ids[i];880 881 rk3288_saved_cru_regs[i] =882 readl_relaxed(rk3288_cru_base + reg_id);883 }884 885 /*886 * Going into deep sleep (specifically setting PMU_CLR_DMA in887 * RK3288_PMU_PWRMODE_CON1) appears to fail unless888 * "aclk_dmac1" is on.889 */890 writel_relaxed(1 << (12 + 16),891 rk3288_cru_base + RK3288_CLKGATE_CON(10));892 893 /*894 * Switch PLLs other than DPLL (for SDRAM) to slow mode to895 * avoid crashes on resume. The Mask ROM on the system will896 * put APLL, CPLL, and GPLL into slow mode at resume time897 * anyway (which is why we restore them), but we might not898 * even make it to the Mask ROM if this isn't done at suspend899 * time.900 *901 * NOTE: only APLL truly matters here, but we'll do them all.902 */903 904 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);905 906 return 0;907}908 909static void rk3288_clk_resume(void)910{911 int i, reg_id;912 913 for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {914 reg_id = rk3288_saved_cru_reg_ids[i];915 916 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,917 rk3288_cru_base + reg_id);918 }919}920 921static void rk3288_clk_shutdown(void)922{923 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);924}925 926static struct syscore_ops rk3288_clk_syscore_ops = {927 .suspend = rk3288_clk_suspend,928 .resume = rk3288_clk_resume,929};930 931static void __init rk3288_common_init(struct device_node *np,932 enum rk3288_variant soc)933{934 struct rockchip_clk_provider *ctx;935 unsigned long clk_nr_clks;936 937 rk3288_cru_base = of_iomap(np, 0);938 if (!rk3288_cru_base) {939 pr_err("%s: could not map cru region\n", __func__);940 return;941 }942 943 clk_nr_clks = rockchip_clk_find_max_clk_id(rk3288_clk_branches,944 ARRAY_SIZE(rk3288_clk_branches)) + 1;945 ctx = rockchip_clk_init(np, rk3288_cru_base, clk_nr_clks);946 if (IS_ERR(ctx)) {947 pr_err("%s: rockchip clk init failed\n", __func__);948 iounmap(rk3288_cru_base);949 return;950 }951 952 rockchip_clk_register_plls(ctx, rk3288_pll_clks,953 ARRAY_SIZE(rk3288_pll_clks),954 RK3288_GRF_SOC_STATUS1);955 rockchip_clk_register_branches(ctx, rk3288_clk_branches,956 ARRAY_SIZE(rk3288_clk_branches));957 958 if (soc == RK3288W_CRU)959 rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,960 ARRAY_SIZE(rk3288w_hclkvio_branch));961 else962 rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,963 ARRAY_SIZE(rk3288_hclkvio_branch));964 965 rockchip_clk_protect_critical(rk3288_critical_clocks,966 ARRAY_SIZE(rk3288_critical_clocks));967 968 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",969 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),970 &rk3288_cpuclk_data, rk3288_cpuclk_rates,971 ARRAY_SIZE(rk3288_cpuclk_rates));972 973 rockchip_register_softrst(np, 12,974 rk3288_cru_base + RK3288_SOFTRST_CON(0),975 ROCKCHIP_SOFTRST_HIWORD_MASK);976 977 rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,978 rk3288_clk_shutdown);979 register_syscore_ops(&rk3288_clk_syscore_ops);980 981 rockchip_clk_of_add_provider(np, ctx);982}983 984static void __init rk3288_clk_init(struct device_node *np)985{986 rk3288_common_init(np, RK3288_CRU);987}988CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);989 990static void __init rk3288w_clk_init(struct device_node *np)991{992 rk3288_common_init(np, RK3288W_CRU);993}994CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);995