1819 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd.4 * Author: Elaine Zhang <zhangqing@rock-chips.com>5 */6 7#include <linux/clk-provider.h>8#include <linux/of.h>9#include <linux/of_address.h>10#include <linux/platform_device.h>11#include <linux/syscore_ops.h>12#include <linux/mfd/syscon.h>13#include <dt-bindings/clock/rockchip,rk3576-cru.h>14#include "clk.h"15 16#define RK3576_GRF_SOC_STATUS0 0x60017#define RK3576_PMU0_GRF_OSC_CON6 0x1818 19enum rk3576_plls {20 bpll, lpll, vpll, aupll, cpll, gpll, ppll,21};22 23static struct rockchip_pll_rate_table rk3576_pll_rates[] = {24 /* _mhz, _p, _m, _s, _k */25 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),26 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),27 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),28 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),29 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),30 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),31 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),32 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),33 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),34 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),35 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),36 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),37 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),38 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),39 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),40 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),41 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),42 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),43 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),44 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),45 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),46 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),47 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),48 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),49 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),50 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),51 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),52 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),53 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),54 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),55 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),56 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),57 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),58 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),59 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),60 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),61 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),62 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),63 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),64 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),65 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),66 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),67 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),68 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),69 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),70 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),71 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),72 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),73 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),74 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),75 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),76 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),77 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),78 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),79 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),80 RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),81 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),82 RK3588_PLL_RATE(900000000, 2, 300, 2, 0),83 RK3588_PLL_RATE(816000000, 2, 272, 2, 0),84 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),85 RK3588_PLL_RATE(786000000, 1, 131, 2, 0),86 RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),87 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),88 RK3588_PLL_RATE(600000000, 2, 200, 2, 0),89 RK3588_PLL_RATE(594000000, 2, 198, 2, 0),90 RK3588_PLL_RATE(408000000, 2, 272, 3, 0),91 RK3588_PLL_RATE(312000000, 2, 208, 3, 0),92 RK3588_PLL_RATE(216000000, 2, 288, 4, 0),93 RK3588_PLL_RATE(96000000, 2, 256, 5, 0),94 { /* sentinel */ },95};96 97static struct rockchip_pll_rate_table rk3576_ppll_rates[] = {98 /* _mhz, _p, _m, _s, _k */99 RK3588_PLL_RATE(1300000000, 3, 325, 2, 0),100 { /* sentinel */ },101};102 103#define RK3576_ACLK_M_BIGCORE_DIV_MASK 0x1f104#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0105#define RK3576_ACLK_M_LITCORE_DIV_MASK 0x1f106#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8107#define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0x1f108#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0109#define RK3576_ACLK_CCI_DIV_MASK 0x1f110#define RK3576_ACLK_CCI_DIV_SHIFT 7111#define RK3576_ACLK_CCI_MUX_MASK 0x3112#define RK3576_ACLK_CCI_MUX_SHIFT 12113 114#define RK3576_BIGCORE_CLKSEL2(_amcore) \115{ \116 .reg = RK3576_BIGCORE_CLKSEL_CON(2), \117 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \118 RK3576_ACLK_M_BIGCORE_DIV_SHIFT), \119}120 121#define RK3576_LITCORE_CLKSEL1(_amcore) \122{ \123 .reg = RK3576_LITCORE_CLKSEL_CON(1), \124 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \125 RK3576_ACLK_M_LITCORE_DIV_SHIFT), \126}127 128#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \129{ \130 .reg = RK3576_LITCORE_CLKSEL_CON(2), \131 .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \132 RK3576_PCLK_DBG_LITCORE_DIV_SHIFT), \133}134 135#define RK3576_CCI_CLKSEL4(_ccisel, _div) \136{ \137 .reg = RK3576_CCI_CLKSEL_CON(4), \138 .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \139 RK3576_ACLK_CCI_MUX_SHIFT) | \140 HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \141 RK3576_ACLK_CCI_DIV_SHIFT), \142}143 144#define RK3576_CPUBCLK_RATE(_prate, _amcore) \145{ \146 .prate = _prate##U, \147 .divs = { \148 RK3576_BIGCORE_CLKSEL2(_amcore), \149 }, \150}151 152#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \153{ \154 .prate = _prate##U, \155 .divs = { \156 RK3576_LITCORE_CLKSEL1(_amcore), \157 RK3576_LITCORE_CLKSEL2(_pclkdbg), \158 }, \159 .pre_muxs = { \160 RK3576_CCI_CLKSEL4(2, 2), \161 }, \162 .post_muxs = { \163 RK3576_CCI_CLKSEL4(_ccisel, 2), \164 }, \165}166 167static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] __initdata = {168 RK3576_CPUBCLK_RATE(2496000000, 2),169 RK3576_CPUBCLK_RATE(2400000000, 2),170 RK3576_CPUBCLK_RATE(2304000000, 2),171 RK3576_CPUBCLK_RATE(2208000000, 2),172 RK3576_CPUBCLK_RATE(2184000000, 2),173 RK3576_CPUBCLK_RATE(2088000000, 2),174 RK3576_CPUBCLK_RATE(2040000000, 2),175 RK3576_CPUBCLK_RATE(2016000000, 2),176 RK3576_CPUBCLK_RATE(1992000000, 2),177 RK3576_CPUBCLK_RATE(1896000000, 2),178 RK3576_CPUBCLK_RATE(1800000000, 2),179 RK3576_CPUBCLK_RATE(1704000000, 2),180 RK3576_CPUBCLK_RATE(1608000000, 2),181 RK3576_CPUBCLK_RATE(1584000000, 2),182 RK3576_CPUBCLK_RATE(1560000000, 2),183 RK3576_CPUBCLK_RATE(1536000000, 2),184 RK3576_CPUBCLK_RATE(1512000000, 2),185 RK3576_CPUBCLK_RATE(1488000000, 2),186 RK3576_CPUBCLK_RATE(1464000000, 2),187 RK3576_CPUBCLK_RATE(1440000000, 2),188 RK3576_CPUBCLK_RATE(1416000000, 2),189 RK3576_CPUBCLK_RATE(1392000000, 2),190 RK3576_CPUBCLK_RATE(1368000000, 2),191 RK3576_CPUBCLK_RATE(1344000000, 2),192 RK3576_CPUBCLK_RATE(1320000000, 2),193 RK3576_CPUBCLK_RATE(1296000000, 2),194 RK3576_CPUBCLK_RATE(1272000000, 2),195 RK3576_CPUBCLK_RATE(1248000000, 2),196 RK3576_CPUBCLK_RATE(1224000000, 2),197 RK3576_CPUBCLK_RATE(1200000000, 2),198 RK3576_CPUBCLK_RATE(1104000000, 2),199 RK3576_CPUBCLK_RATE(1008000000, 2),200 RK3576_CPUBCLK_RATE(912000000, 2),201 RK3576_CPUBCLK_RATE(816000000, 2),202 RK3576_CPUBCLK_RATE(696000000, 2),203 RK3576_CPUBCLK_RATE(600000000, 2),204 RK3576_CPUBCLK_RATE(408000000, 2),205 RK3576_CPUBCLK_RATE(312000000, 2),206 RK3576_CPUBCLK_RATE(216000000, 2),207 RK3576_CPUBCLK_RATE(96000000, 2),208};209 210static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = {211 .core_reg[0] = RK3576_BIGCORE_CLKSEL_CON(1),212 .div_core_shift[0] = 7,213 .div_core_mask[0] = 0x1f,214 .num_cores = 1,215 .mux_core_alt = 1,216 .mux_core_main = 0,217 .mux_core_shift = 12,218 .mux_core_mask = 0x3,219};220 221static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] __initdata = {222 RK3576_CPULCLK_RATE(2400000000, 2, 6, 3),223 RK3576_CPULCLK_RATE(2304000000, 2, 6, 3),224 RK3576_CPULCLK_RATE(2208000000, 2, 6, 3),225 RK3576_CPULCLK_RATE(2184000000, 2, 6, 3),226 RK3576_CPULCLK_RATE(2088000000, 2, 6, 3),227 RK3576_CPULCLK_RATE(2040000000, 2, 6, 3),228 RK3576_CPULCLK_RATE(2016000000, 2, 6, 3),229 RK3576_CPULCLK_RATE(1992000000, 2, 6, 3),230 RK3576_CPULCLK_RATE(1896000000, 2, 6, 3),231 RK3576_CPULCLK_RATE(1800000000, 2, 6, 3),232 RK3576_CPULCLK_RATE(1704000000, 2, 6, 3),233 RK3576_CPULCLK_RATE(1608000000, 2, 6, 3),234 RK3576_CPULCLK_RATE(1584000000, 2, 6, 3),235 RK3576_CPULCLK_RATE(1560000000, 2, 6, 3),236 RK3576_CPULCLK_RATE(1536000000, 2, 6, 3),237 RK3576_CPULCLK_RATE(1512000000, 2, 6, 3),238 RK3576_CPULCLK_RATE(1488000000, 2, 6, 3),239 RK3576_CPULCLK_RATE(1464000000, 2, 6, 3),240 RK3576_CPULCLK_RATE(1440000000, 2, 6, 3),241 RK3576_CPULCLK_RATE(1416000000, 2, 6, 3),242 RK3576_CPULCLK_RATE(1392000000, 2, 6, 3),243 RK3576_CPULCLK_RATE(1368000000, 2, 6, 3),244 RK3576_CPULCLK_RATE(1344000000, 2, 6, 3),245 RK3576_CPULCLK_RATE(1320000000, 2, 6, 3),246 RK3576_CPULCLK_RATE(1296000000, 2, 6, 3),247 RK3576_CPULCLK_RATE(1272000000, 2, 6, 3),248 RK3576_CPULCLK_RATE(1248000000, 2, 6, 3),249 RK3576_CPULCLK_RATE(1224000000, 2, 6, 3),250 RK3576_CPULCLK_RATE(1200000000, 2, 6, 2),251 RK3576_CPULCLK_RATE(1104000000, 2, 6, 2),252 RK3576_CPULCLK_RATE(1008000000, 2, 6, 2),253 RK3576_CPULCLK_RATE(912000000, 2, 6, 2),254 RK3576_CPULCLK_RATE(816000000, 2, 6, 2),255 RK3576_CPULCLK_RATE(696000000, 2, 6, 2),256 RK3576_CPULCLK_RATE(600000000, 2, 6, 2),257 RK3576_CPULCLK_RATE(408000000, 2, 6, 2),258 RK3576_CPULCLK_RATE(312000000, 2, 6, 2),259 RK3576_CPULCLK_RATE(216000000, 2, 6, 2),260 RK3576_CPULCLK_RATE(96000000, 2, 6, 2),261};262 263static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = {264 .core_reg[0] = RK3576_LITCORE_CLKSEL_CON(0),265 .div_core_shift[0] = 7,266 .div_core_mask[0] = 0x1f,267 .num_cores = 1,268 .mux_core_alt = 1,269 .mux_core_main = 0,270 .mux_core_shift = 12,271 .mux_core_mask = 0x3,272};273 274#define MFLAGS CLK_MUX_HIWORD_MASK275#define DFLAGS CLK_DIVIDER_HIWORD_MASK276#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)277 278PNAME(mux_pll_p) = { "xin24m", "xin32k" };279PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" };280PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" };281PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" };282PNAME(gpll_24m_p) = { "gpll", "xin24m" };283PNAME(cpll_24m_p) = { "cpll", "xin24m" };284PNAME(gpll_cpll_p) = { "gpll", "cpll" };285PNAME(gpll_spll_p) = { "gpll", "spll" };286PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" };287PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };288PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };289PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" };290PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };291PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" };292PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" };293PNAME(gpll_cpll_lpll_bpll_p) = { "gpll", "cpll", "lpll_dummy", "bpll_dummy" };294PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", "bpll_dummy", "lpll_dummy" };295PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" };296PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" };297PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", "bpll_dummy", "lpll_dummy" };298PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", "lpll_dummy", "bpll_dummy" };299PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy", "lpll_dummy" };300PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", "bpll_dummy", "lpll_dummy" };301PNAME(gpll_spll_isppvtpll_bpll_lpll_p) = { "gpll", "spll", "isp_pvtpll", "bpll_dummy", "lpll_dummy" };302PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", "aupll", "lpll_dummy", "xin24m" };303PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", "vpll", "bpll_dummy", "lpll_dummy" };304PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", "bpll_dummy" };305PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", "gpll", "lpll" };306PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" };307PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2",308 "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2" };309PNAME(audio_frac_p) = { "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3" };310PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };311PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" };312PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" };313PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" };314PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };315PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" };316PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" };317PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" };318PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" };319PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", "clk_spll_div4", "clk_spll_div6", "xin24m" };320PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m" };321PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" };322PNAME(mclk_sai0_8ch_p) = { "mclk_sai0_8ch_src", "sai0_mclkin", "sai1_mclkin" };323PNAME(mclk_sai1_8ch_p) = { "mclk_sai1_8ch_src", "sai1_mclkin" };324PNAME(mclk_sai2_2ch_p) = { "mclk_sai2_2ch_src", "sai2_mclkin", "sai1_mclkin" };325PNAME(mclk_sai3_2ch_p) = { "mclk_sai3_2ch_src", "sai3_mclkin", "sai1_mclkin" };326PNAME(mclk_sai4_2ch_p) = { "mclk_sai4_2ch_src", "sai4_mclkin", "sai1_mclkin" };327PNAME(mclk_sai5_8ch_p) = { "mclk_sai5_8ch_src", "sai1_mclkin" };328PNAME(mclk_sai6_8ch_p) = { "mclk_sai6_8ch_src", "sai1_mclkin" };329PNAME(mclk_sai7_8ch_p) = { "mclk_sai7_8ch_src", "sai1_mclkin" };330PNAME(mclk_sai8_8ch_p) = { "mclk_sai8_8ch_src", "sai1_mclkin" };331PNAME(mclk_sai9_8ch_p) = { "mclk_sai9_8ch_src", "sai1_mclkin" };332PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" };333PNAME(clk_gmac1_ptp_ref_src_p) = { "gpll", "cpll", "gmac1_ptp_refclk_in" };334PNAME(clk_gmac0_ptp_ref_src_p) = { "gpll", "cpll", "gmac0_ptp_refclk_in" };335PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy",336 "dclk_ebc_frac", "xin24m" };337PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" };338PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" };339PNAME(dclk_vp2_p) = { "dclk_vp2_src", "clk_hdmiphy_pixel0" };340PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0",341 "clk_uart_frac_1", "clk_uart_frac_2"};342PNAME(clk_freq_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin",343 "sai3_mclkin", "sai4_mclkin", "sai_sclkin_freq"};344PNAME(clk_counter_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin",345 "sai3_mclkin", "sai4_mclkin", "sai_sclkin_counter"};346PNAME(sai_sclkin_freq_p) = { "sai0_sclk_in", "sai1_sclk_in", "sai2_sclk_in",347 "sai3_sclk_in", "sai4_sclk_in"};348PNAME(clk_ref_pcie0_phy_p) = { "clk_pcie_100m_src", "clk_pcie_100m_nduty_src",349 "xin24m"};350PNAME(hclk_vi_root_p) = { "clk_gpll_div6", "clk_cpll_div10",351 "aclk_vi_root_inter", "xin24m"};352PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", "clk_ref_mphy_26m"};353PNAME(mux_pmu200m_pmu100m_pmu50m_24m_p) = { "clk_200m_pmu_src", "clk_100m_pmu_src",354 "clk_50m_pmu_src", "xin24m" };355PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", "clk_50m_pmu_src", "xin24m" };356PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", "xin_osc0_div" };357PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" };358PNAME(clk_usbphy_ref_src_p) = { "usbphy0_24m", "usbphy1_24m" };359PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" };360PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" };361 362static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = {363 [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p,364 0, RK3576_PLL_CON(0),365 RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates),366 [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,367 0, RK3576_LPLL_CON(16),368 RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates),369 [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,370 0, RK3576_PLL_CON(88),371 RK3576_MODE_CON0, 4, 15, 0, rk3576_pll_rates),372 [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,373 0, RK3576_PLL_CON(96),374 RK3576_MODE_CON0, 6, 15, 0, rk3576_pll_rates),375 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,376 CLK_IGNORE_UNUSED, RK3576_PLL_CON(104),377 RK3576_MODE_CON0, 8, 15, 0, rk3576_pll_rates),378 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,379 CLK_IGNORE_UNUSED, RK3576_PLL_CON(112),380 RK3576_MODE_CON0, 2, 15, 0, rk3576_pll_rates),381 [ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p,382 CLK_IGNORE_UNUSED, RK3576_PMU_PLL_CON(128),383 RK3576_MODE_CON0, 10, 15, 0, rk3576_ppll_rates),384};385 386static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {387 /*388 * CRU Clock-Architecture389 */390 /* fixed */391 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),392 393 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL,394 RK3576_PMU_CLKSEL_CON(21), 0,395 RK3576_PMU_CLKGATE_CON(7), 11, GFLAGS),396 397 FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12),398 FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6),399 FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4),400 FACTOR(0, "lpll_div2", "lpll", 0, 1, 2),401 FACTOR(0, "bpll_div4", "bpll", 0, 1, 4),402 403 /* top */404 COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, CLK_IS_CRITICAL,405 RK3576_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,406 RK3576_CLKGATE_CON(0), 0, GFLAGS),407 COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, CLK_IS_CRITICAL,408 RK3576_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,409 RK3576_CLKGATE_CON(0), 1, GFLAGS),410 COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, CLK_IS_CRITICAL,411 RK3576_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,412 RK3576_CLKGATE_CON(0), 2, GFLAGS),413 COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, CLK_IS_CRITICAL,414 RK3576_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,415 RK3576_CLKGATE_CON(0), 3, GFLAGS),416 COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, CLK_IS_CRITICAL,417 RK3576_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,418 RK3576_CLKGATE_CON(0), 4, GFLAGS),419 COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, CLK_IS_CRITICAL,420 RK3576_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,421 RK3576_CLKGATE_CON(0), 5, GFLAGS),422 COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL,423 RK3576_CLKSEL_CON(3), 5, 2, MFLAGS, 0, 5, DFLAGS,424 RK3576_CLKGATE_CON(0), 6, GFLAGS),425 COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, CLK_IS_CRITICAL,426 RK3576_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS,427 RK3576_CLKGATE_CON(0), 7, GFLAGS),428 COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, CLK_IS_CRITICAL,429 RK3576_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,430 RK3576_CLKGATE_CON(0), 9, GFLAGS),431 COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, CLK_IS_CRITICAL,432 RK3576_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,433 RK3576_CLKGATE_CON(0), 10, GFLAGS),434 COMPOSITE(CLK_SPLL_DIV1, "clk_spll_div1", gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL,435 RK3576_CLKSEL_CON(6), 5, 3, MFLAGS, 0, 5, DFLAGS,436 RK3576_CLKGATE_CON(0), 12, GFLAGS),437 COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,438 RK3576_CLKSEL_CON(8), 7, 2, MFLAGS,439 RK3576_CLKGATE_CON(1), 1, GFLAGS),440 COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_aupll_p, CLK_IS_CRITICAL,441 RK3576_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS,442 RK3576_CLKGATE_CON(1), 3, GFLAGS),443 COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL,444 RK3576_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS,445 RK3576_CLKGATE_CON(1), 6, GFLAGS),446 COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL,447 RK3576_CLKSEL_CON(10), 11, 3, MFLAGS, 6, 5, DFLAGS,448 RK3576_CLKGATE_CON(1), 7, GFLAGS),449 COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,450 RK3576_CLKSEL_CON(19), 2, 2, MFLAGS,451 RK3576_CLKGATE_CON(1), 14, GFLAGS),452 COMPOSITE_NODIV(HCLK_VO0VOP_CHANNEL, "hclk_vo0vop_channel", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,453 RK3576_CLKSEL_CON(19), 6, 2, MFLAGS,454 RK3576_CLKGATE_CON(2), 0, GFLAGS),455 COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL,456 RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS,457 RK3576_CLKGATE_CON(2), 1, GFLAGS),458 MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,459 RK3576_CLKSEL_CON(13), 0, 2, MFLAGS),460 COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0,461 RK3576_CLKSEL_CON(12), 0,462 RK3576_CLKGATE_CON(1), 10, GFLAGS),463 MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,464 RK3576_CLKSEL_CON(15), 0, 2, MFLAGS),465 COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0,466 RK3576_CLKSEL_CON(14), 0,467 RK3576_CLKGATE_CON(1), 11, GFLAGS),468 MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,469 RK3576_CLKSEL_CON(17), 0, 2, MFLAGS),470 COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0,471 RK3576_CLKSEL_CON(16), 0,472 RK3576_CLKGATE_CON(1), 12, GFLAGS),473 MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,474 RK3576_CLKSEL_CON(19), 0, 2, MFLAGS),475 COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0,476 RK3576_CLKSEL_CON(18), 0,477 RK3576_CLKGATE_CON(1), 13, GFLAGS),478 MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0,479 RK3576_CLKSEL_CON(22), 0, 2, MFLAGS),480 COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", "clk_uart_frac_0_src", 0,481 RK3576_CLKSEL_CON(21), 0,482 RK3576_CLKGATE_CON(2), 5, GFLAGS),483 MUX(0, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0,484 RK3576_CLKSEL_CON(24), 0, 2, MFLAGS),485 COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", "clk_uart_frac_1_src", 0,486 RK3576_CLKSEL_CON(23), 0,487 RK3576_CLKGATE_CON(2), 6, GFLAGS),488 MUX(0, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0,489 RK3576_CLKSEL_CON(26), 0, 2, MFLAGS),490 COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", "clk_uart_frac_2_src", 0,491 RK3576_CLKSEL_CON(25), 0,492 RK3576_CLKGATE_CON(2), 7, GFLAGS),493 COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_p, 0,494 RK3576_CLKSEL_CON(27), 13, 3, MFLAGS, 5, 8, DFLAGS,495 RK3576_CLKGATE_CON(2), 13, GFLAGS),496 COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "gpll", 0,497 RK3576_CLKSEL_CON(28), 0, 5, DFLAGS,498 RK3576_CLKGATE_CON(2), 14, GFLAGS),499 COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "cpll", 0,500 RK3576_CLKSEL_CON(28), 5, 5, DFLAGS,501 RK3576_CLKGATE_CON(2), 15, GFLAGS),502 COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0,503 RK3576_CLKSEL_CON(28), 10, 5, DFLAGS,504 RK3576_CLKGATE_CON(3), 0, GFLAGS),505 COMPOSITE(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", audio_frac_int_p, 0,506 RK3576_CLKSEL_CON(29), 9, 3, MFLAGS, 0, 9, DFLAGS,507 RK3576_CLKGATE_CON(3), 2, GFLAGS),508 COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0,509 RK3576_CLKSEL_CON(30), 10, 5, DFLAGS,510 RK3576_CLKGATE_CON(3), 6, GFLAGS),511 COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0,512 RK3576_CLKSEL_CON(31), 0, 5, DFLAGS,513 RK3576_CLKGATE_CON(3), 7, GFLAGS),514 COMPOSITE(LCLK_ASRC_SRC_0, "lclk_asrc_src_0", audio_frac_p, 0,515 RK3576_CLKSEL_CON(31), 10, 2, MFLAGS, 5, 5, DFLAGS,516 RK3576_CLKGATE_CON(3), 10, GFLAGS),517 COMPOSITE(LCLK_ASRC_SRC_1, "lclk_asrc_src_1", audio_frac_p, 0,518 RK3576_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,519 RK3576_CLKGATE_CON(3), 11, GFLAGS),520 COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0,521 RK3576_CLKSEL_CON(33), 8, 3, MFLAGS, 0, 8, DFLAGS,522 RK3576_CLKGATE_CON(4), 1, GFLAGS),523 COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0,524 RK3576_CLKSEL_CON(34), 8, 3, MFLAGS, 0, 8, DFLAGS,525 RK3576_CLKGATE_CON(4), 2, GFLAGS),526 COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0,527 RK3576_CLKSEL_CON(35), 8, 3, MFLAGS, 0, 8, DFLAGS,528 RK3576_CLKGATE_CON(4), 3, GFLAGS),529 COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, 0,530 RK3576_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,531 RK3576_CLKGATE_CON(5), 10, GFLAGS),532 COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, 0,533 RK3576_CLKSEL_CON(36), 15, 1, MFLAGS, 8, 7, DFLAGS,534 RK3576_CLKGATE_CON(5), 11, GFLAGS),535 COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,536 RK3576_CLKSEL_CON(37), 8, 2, MFLAGS, 0, 8, DFLAGS,537 RK3576_CLKGATE_CON(5), 12, GFLAGS),538 GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0,539 RK3576_CLKGATE_CON(5), 13, GFLAGS),540 GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0,541 RK3576_CLKGATE_CON(5), 14, GFLAGS),542 GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,543 RK3576_CLKGATE_CON(5), 15, GFLAGS),544 COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,545 RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,546 RK3576_CLKGATE_CON(6), 3, GFLAGS),547 COMPOSITE(CLK_MIPI_CAMERAOUT_M1, "clk_mipi_cameraout_m1", mux_24m_spll_gpll_cpll_p, 0,548 RK3576_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,549 RK3576_CLKGATE_CON(6), 4, GFLAGS),550 COMPOSITE(CLK_MIPI_CAMERAOUT_M2, "clk_mipi_cameraout_m2", mux_24m_spll_gpll_cpll_p, 0,551 RK3576_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,552 RK3576_CLKGATE_CON(6), 5, GFLAGS),553 COMPOSITE(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", audio_frac_int_p, 0,554 RK3576_CLKSEL_CON(41), 7, 3, MFLAGS, 2, 5, DFLAGS,555 RK3576_CLKGATE_CON(6), 8, GFLAGS),556 557 /* bus */558 COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,559 RK3576_CLKSEL_CON(55), 0, 2, MFLAGS,560 RK3576_CLKGATE_CON(11), 0, GFLAGS),561 COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,562 RK3576_CLKSEL_CON(55), 2, 2, MFLAGS,563 RK3576_CLKGATE_CON(11), 1, GFLAGS),564 COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,565 RK3576_CLKSEL_CON(55), 9, 1, MFLAGS, 4, 5, DFLAGS,566 RK3576_CLKGATE_CON(11), 2, GFLAGS),567 GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0,568 RK3576_CLKGATE_CON(11), 6, GFLAGS),569 COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0,570 RK3576_CLKSEL_CON(56), 5, 2, MFLAGS, 0, 5, DFLAGS,571 RK3576_CLKGATE_CON(11), 7, GFLAGS),572 GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0,573 RK3576_CLKGATE_CON(11), 8, GFLAGS),574 COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0,575 RK3576_CLKSEL_CON(56), 12, 2, MFLAGS, 7, 5, DFLAGS,576 RK3576_CLKGATE_CON(11), 9, GFLAGS),577 GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL,578 RK3576_CLKGATE_CON(11), 15, GFLAGS),579 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,580 RK3576_CLKGATE_CON(12), 0, GFLAGS),581 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0,582 RK3576_CLKGATE_CON(12), 1, GFLAGS),583 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,584 RK3576_CLKGATE_CON(12), 2, GFLAGS),585 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0,586 RK3576_CLKGATE_CON(12), 3, GFLAGS),587 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0,588 RK3576_CLKGATE_CON(12), 4, GFLAGS),589 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0,590 RK3576_CLKGATE_CON(12), 5, GFLAGS),591 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0,592 RK3576_CLKGATE_CON(12), 6, GFLAGS),593 GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0,594 RK3576_CLKGATE_CON(12), 7, GFLAGS),595 GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0,596 RK3576_CLKGATE_CON(12), 8, GFLAGS),597 GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0,598 RK3576_CLKGATE_CON(12), 9, GFLAGS),599 GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0,600 RK3576_CLKGATE_CON(12), 10, GFLAGS),601 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,602 RK3576_CLKGATE_CON(12), 11, GFLAGS),603 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,604 RK3576_CLKSEL_CON(57), 0, 2, MFLAGS,605 RK3576_CLKGATE_CON(12), 12, GFLAGS),606 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,607 RK3576_CLKSEL_CON(57), 2, 2, MFLAGS,608 RK3576_CLKGATE_CON(12), 13, GFLAGS),609 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,610 RK3576_CLKSEL_CON(57), 4, 2, MFLAGS,611 RK3576_CLKGATE_CON(12), 14, GFLAGS),612 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,613 RK3576_CLKSEL_CON(57), 6, 2, MFLAGS,614 RK3576_CLKGATE_CON(12), 15, GFLAGS),615 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,616 RK3576_CLKSEL_CON(57), 8, 2, MFLAGS,617 RK3576_CLKGATE_CON(13), 0, GFLAGS),618 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,619 RK3576_CLKSEL_CON(57), 10, 2, MFLAGS,620 RK3576_CLKGATE_CON(13), 1, GFLAGS),621 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,622 RK3576_CLKSEL_CON(57), 12, 2, MFLAGS,623 RK3576_CLKGATE_CON(13), 2, GFLAGS),624 COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0,625 RK3576_CLKSEL_CON(57), 14, 2, MFLAGS,626 RK3576_CLKGATE_CON(13), 3, GFLAGS),627 COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0,628 RK3576_CLKSEL_CON(58), 0, 2, MFLAGS,629 RK3576_CLKGATE_CON(13), 4, GFLAGS),630 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0,631 RK3576_CLKGATE_CON(13), 6, GFLAGS),632 COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,633 RK3576_CLKSEL_CON(58), 12, 1, MFLAGS, 4, 8, DFLAGS,634 RK3576_CLKGATE_CON(13), 7, GFLAGS),635 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0,636 RK3576_CLKGATE_CON(13), 8, GFLAGS),637 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,638 RK3576_CLKSEL_CON(59), 0, 8, DFLAGS,639 RK3576_CLKGATE_CON(13), 9, GFLAGS),640 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,641 RK3576_CLKGATE_CON(13), 10, GFLAGS),642 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,643 RK3576_CLKGATE_CON(13), 11, GFLAGS),644 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0,645 RK3576_CLKGATE_CON(13), 12, GFLAGS),646 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0,647 RK3576_CLKGATE_CON(13), 13, GFLAGS),648 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,649 RK3576_CLKGATE_CON(13), 14, GFLAGS),650 GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0,651 RK3576_CLKGATE_CON(13), 15, GFLAGS),652 GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,653 RK3576_CLKGATE_CON(14), 0, GFLAGS),654 GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0,655 RK3576_CLKGATE_CON(14), 1, GFLAGS),656 GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0,657 RK3576_CLKGATE_CON(14), 2, GFLAGS),658 GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0,659 RK3576_CLKGATE_CON(14), 3, GFLAGS),660 GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0,661 RK3576_CLKGATE_CON(14), 4, GFLAGS),662 COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0,663 RK3576_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS,664 RK3576_CLKGATE_CON(14), 5, GFLAGS),665 COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0,666 RK3576_CLKSEL_CON(61), 8, 3, MFLAGS, 0, 8, DFLAGS,667 RK3576_CLKGATE_CON(14), 6, GFLAGS),668 COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0,669 RK3576_CLKSEL_CON(62), 8, 3, MFLAGS, 0, 8, DFLAGS,670 RK3576_CLKGATE_CON(14), 9, GFLAGS),671 COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0,672 RK3576_CLKSEL_CON(63), 8, 3, MFLAGS, 0, 8, DFLAGS,673 RK3576_CLKGATE_CON(14), 12, GFLAGS),674 COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0,675 RK3576_CLKSEL_CON(64), 8, 3, MFLAGS, 0, 8, DFLAGS,676 RK3576_CLKGATE_CON(14), 15, GFLAGS),677 COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0,678 RK3576_CLKSEL_CON(65), 8, 3, MFLAGS, 0, 8, DFLAGS,679 RK3576_CLKGATE_CON(15), 2, GFLAGS),680 COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0,681 RK3576_CLKSEL_CON(66), 8, 3, MFLAGS, 0, 8, DFLAGS,682 RK3576_CLKGATE_CON(15), 5, GFLAGS),683 COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0,684 RK3576_CLKSEL_CON(67), 8, 3, MFLAGS, 0, 8, DFLAGS,685 RK3576_CLKGATE_CON(15), 8, GFLAGS),686 COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_p, 0,687 RK3576_CLKSEL_CON(68), 8, 3, MFLAGS, 0, 8, DFLAGS,688 RK3576_CLKGATE_CON(15), 9, GFLAGS),689 COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_p, 0,690 RK3576_CLKSEL_CON(69), 8, 3, MFLAGS, 0, 8, DFLAGS,691 RK3576_CLKGATE_CON(15), 10, GFLAGS),692 COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_p, 0,693 RK3576_CLKSEL_CON(70), 8, 3, MFLAGS, 0, 8, DFLAGS,694 RK3576_CLKGATE_CON(15), 11, GFLAGS),695 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0,696 RK3576_CLKGATE_CON(15), 13, GFLAGS),697 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,698 RK3576_CLKGATE_CON(15), 14, GFLAGS),699 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0,700 RK3576_CLKGATE_CON(15), 15, GFLAGS),701 GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0,702 RK3576_CLKGATE_CON(16), 0, GFLAGS),703 GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0,704 RK3576_CLKGATE_CON(16), 1, GFLAGS),705 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,706 RK3576_CLKSEL_CON(70), 13, 2, MFLAGS,707 RK3576_CLKGATE_CON(16), 2, GFLAGS),708 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,709 RK3576_CLKSEL_CON(71), 0, 2, MFLAGS,710 RK3576_CLKGATE_CON(16), 3, GFLAGS),711 COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0,712 RK3576_CLKSEL_CON(71), 2, 2, MFLAGS,713 RK3576_CLKGATE_CON(16), 4, GFLAGS),714 COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0,715 RK3576_CLKSEL_CON(71), 4, 2, MFLAGS,716 RK3576_CLKGATE_CON(16), 5, GFLAGS),717 COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0,718 RK3576_CLKSEL_CON(71), 6, 2, MFLAGS,719 RK3576_CLKGATE_CON(16), 6, GFLAGS),720 GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,721 RK3576_CLKGATE_CON(16), 7, GFLAGS),722 GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,723 RK3576_CLKGATE_CON(16), 8, GFLAGS),724 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,725 RK3576_CLKGATE_CON(16), 10, GFLAGS),726 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,727 RK3576_CLKSEL_CON(71), 8, 2, MFLAGS,728 RK3576_CLKGATE_CON(16), 11, GFLAGS),729 GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,730 RK3576_CLKGATE_CON(16), 13, GFLAGS),731 GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0,732 RK3576_CLKGATE_CON(16), 15, GFLAGS),733 GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0,734 RK3576_CLKGATE_CON(17), 3, GFLAGS),735 GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0,736 RK3576_CLKGATE_CON(17), 4, GFLAGS),737 COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, 0,738 RK3576_CLKSEL_CON(71), 14, 1, MFLAGS,739 RK3576_CLKGATE_CON(17), 5, GFLAGS),740 GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0,741 RK3576_CLKGATE_CON(17), 6, GFLAGS),742 GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0,743 RK3576_CLKGATE_CON(17), 7, GFLAGS),744 GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0,745 RK3576_CLKGATE_CON(17), 8, GFLAGS),746 GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0,747 RK3576_CLKGATE_CON(17), 9, GFLAGS),748 GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0,749 RK3576_CLKGATE_CON(17), 10, GFLAGS),750 GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0,751 RK3576_CLKGATE_CON(17), 11, GFLAGS),752 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0,753 RK3576_CLKGATE_CON(17), 13, GFLAGS),754 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0,755 RK3576_CLKGATE_CON(17), 15, GFLAGS),756 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,757 RK3576_CLKGATE_CON(18), 0, GFLAGS),758 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0,759 RK3576_CLKGATE_CON(18), 1, GFLAGS),760 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,761 RK3576_CLKGATE_CON(18), 2, GFLAGS),762 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0,763 RK3576_CLKGATE_CON(18), 3, GFLAGS),764 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,765 RK3576_CLKGATE_CON(18), 4, GFLAGS),766 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0,767 RK3576_CLKGATE_CON(18), 5, GFLAGS),768 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,769 RK3576_CLKGATE_CON(18), 6, GFLAGS),770 GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,771 RK3576_CLKGATE_CON(18), 7, GFLAGS),772 GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0,773 RK3576_CLKGATE_CON(18), 8, GFLAGS),774 COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,775 RK3576_CLKSEL_CON(72), 5, 1, MFLAGS, 0, 5, DFLAGS,776 RK3576_CLKGATE_CON(18), 9, GFLAGS),777 COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, 0,778 RK3576_CLKSEL_CON(72), 6, 1, MFLAGS,779 RK3576_CLKGATE_CON(18), 10, GFLAGS),780 GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0,781 RK3576_CLKGATE_CON(18), 11, GFLAGS),782 COMPOSITE(CLK_TIMER7, "clk_timer7", mux_100m_24m_lclk0_p, 0,783 RK3576_CLKSEL_CON(72), 12, 2, MFLAGS, 7, 5, DFLAGS,784 RK3576_CLKGATE_CON(18), 12, GFLAGS),785 COMPOSITE(CLK_TIMER8, "clk_timer8", mux_100m_24m_lclk1_p, 0,786 RK3576_CLKSEL_CON(73), 5, 2, MFLAGS, 0, 5, DFLAGS,787 RK3576_CLKGATE_CON(18), 13, GFLAGS),788 GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0,789 RK3576_CLKGATE_CON(18), 14, GFLAGS),790 GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0,791 RK3576_CLKGATE_CON(18), 15, GFLAGS),792 GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0,793 RK3576_CLKGATE_CON(19), 0, GFLAGS),794 GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,795 RK3576_CLKGATE_CON(19), 1, GFLAGS),796 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,797 RK3576_CLKGATE_CON(19), 2, GFLAGS),798 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,799 RK3576_CLKGATE_CON(19), 3, GFLAGS),800 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,801 RK3576_CLKGATE_CON(19), 4, GFLAGS),802 GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0,803 RK3576_CLKGATE_CON(19), 7, GFLAGS),804 GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0,805 RK3576_CLKGATE_CON(19), 9, GFLAGS),806 COMPOSITE_NODIV(HCLK_BUS_CM0_ROOT, "hclk_bus_cm0_root", mux_400m_200m_100m_24m_p, 0,807 RK3576_CLKSEL_CON(73), 13, 2, MFLAGS,808 RK3576_CLKGATE_CON(19), 10, GFLAGS),809 GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0,810 RK3576_CLKGATE_CON(19), 12, GFLAGS),811 COMPOSITE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", mux_24m_32k_p, 0,812 RK3576_CLKSEL_CON(74), 5, 1, MFLAGS, 0, 5, DFLAGS,813 RK3576_CLKGATE_CON(19), 14, GFLAGS),814 GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL,815 RK3576_CLKGATE_CON(19), 15, GFLAGS),816 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0,817 RK3576_CLKGATE_CON(20), 4, GFLAGS),818 COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,819 RK3576_CLKSEL_CON(74), 6, 2, MFLAGS,820 RK3576_CLKGATE_CON(20), 5, GFLAGS),821 GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,822 RK3576_CLKGATE_CON(20), 7, GFLAGS),823 GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0,824 RK3576_CLKGATE_CON(20), 6, GFLAGS),825 COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0,826 RK3576_CLKSEL_CON(74), 8, 3, MFLAGS,827 RK3576_CLKGATE_CON(20), 8, GFLAGS),828 COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_counter_pwm1_p, 0,829 RK3576_CLKSEL_CON(74), 11, 3, MFLAGS,830 RK3576_CLKGATE_CON(20), 9, GFLAGS),831 COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", sai_sclkin_freq_p, 0,832 RK3576_CLKSEL_CON(75), 0, 3, MFLAGS,833 RK3576_CLKGATE_CON(20), 10, GFLAGS),834 COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", sai_sclkin_freq_p, 0,835 RK3576_CLKSEL_CON(75), 3, 3, MFLAGS,836 RK3576_CLKGATE_CON(20), 11, GFLAGS),837 COMPOSITE(CLK_I3C0, "clk_i3c0", gpll_cpll_aupll_spll_p, 0,838 RK3576_CLKSEL_CON(78), 5, 2, MFLAGS, 0, 5, DFLAGS,839 RK3576_CLKGATE_CON(20), 12, GFLAGS),840 COMPOSITE(CLK_I3C1, "clk_i3c1", gpll_cpll_aupll_spll_p, 0,841 RK3576_CLKSEL_CON(78), 12, 2, MFLAGS, 7, 5, DFLAGS,842 RK3576_CLKGATE_CON(20), 13, GFLAGS),843 GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0,844 RK3576_CLKGATE_CON(40), 2, GFLAGS),845 846 /* cci */847 COMPOSITE(PCLK_CCI_ROOT, "pclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL,848 RK3576_CCI_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,849 RK3576_CCI_CLKGATE_CON(1), 10, GFLAGS),850 COMPOSITE(ACLK_CCI_ROOT, "aclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL,851 RK3576_CCI_CLKSEL_CON(4), 12, 2, MFLAGS, 7, 5, DFLAGS,852 RK3576_CCI_CLKGATE_CON(1), 11, GFLAGS),853 854 /* center */855 COMPOSITE_DIV_OFFSET(ACLK_CENTER_ROOT, "aclk_center_root", gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL,856 RK3576_CLKSEL_CON(168), 5, 3, MFLAGS,857 RK3576_CLKSEL_CON(167), 9, 5, DFLAGS,858 RK3576_CLKGATE_CON(72), 0, GFLAGS),859 COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL,860 RK3576_CLKSEL_CON(168), 8, 2, MFLAGS,861 RK3576_CLKGATE_CON(72), 1, GFLAGS),862 COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,863 RK3576_CLKSEL_CON(168), 10, 2, MFLAGS,864 RK3576_CLKGATE_CON(72), 2, GFLAGS),865 COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,866 RK3576_CLKSEL_CON(168), 12, 2, MFLAGS,867 RK3576_CLKGATE_CON(72), 3, GFLAGS),868 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IGNORE_UNUSED,869 RK3576_CLKGATE_CON(72), 5, GFLAGS),870 GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IGNORE_UNUSED,871 RK3576_CLKGATE_CON(72), 6, GFLAGS),872 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IGNORE_UNUSED,873 RK3576_CLKGATE_CON(72), 10, GFLAGS),874 GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IGNORE_UNUSED,875 RK3576_CLKGATE_CON(72), 11, GFLAGS),876 877 /* ddr */878 COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL,879 RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS,880 RK3576_CLKGATE_CON(21), 0, GFLAGS),881 GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED,882 RK3576_CLKGATE_CON(21), 1, GFLAGS),883 COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED,884 RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS,885 RK3576_CLKGATE_CON(22), 11, GFLAGS),886 GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL,887 RK3576_CLKGATE_CON(22), 15, GFLAGS),888 COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_100m_24m_p, 0,889 RK3576_CLKSEL_CON(77), 6, 1, MFLAGS,890 RK3576_CLKGATE_CON(23), 3, GFLAGS),891 GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,892 RK3576_CLKGATE_CON(23), 4, GFLAGS),893 GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,894 RK3576_CLKGATE_CON(23), 5, GFLAGS),895 GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,896 RK3576_CLKGATE_CON(23), 6, GFLAGS),897 GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0,898 RK3576_CLKGATE_CON(23), 7, GFLAGS),899 GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0,900 RK3576_CLKGATE_CON(23), 8, GFLAGS),901 COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, 0,902 RK3576_CLKSEL_CON(77), 12, 1, MFLAGS, 7, 5, DFLAGS,903 RK3576_CLKGATE_CON(23), 10, GFLAGS),904 905 /* gpu */906 COMPOSITE(CLK_GPU_SRC_PRE, "clk_gpu_src_pre", gpll_cpll_aupll_spll_lpll_p, 0,907 RK3576_CLKSEL_CON(165), 5, 3, MFLAGS, 0, 5, DFLAGS,908 RK3576_CLKGATE_CON(69), 1, GFLAGS),909 GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0,910 RK3576_CLKGATE_CON(69), 3, GFLAGS),911 COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0,912 RK3576_CLKSEL_CON(166), 10, 2, MFLAGS,913 RK3576_CLKGATE_CON(69), 8, GFLAGS),914 915 /* npu */916 COMPOSITE_NODIV(HCLK_RKNN_ROOT, "hclk_rknn_root", mux_200m_100m_50m_24m_p, 0,917 RK3576_CLKSEL_CON(86), 0, 2, MFLAGS,918 RK3576_CLKGATE_CON(31), 4, GFLAGS),919 COMPOSITE(CLK_RKNN_DSU0, "clk_rknn_dsu0", gpll_cpll_aupll_spll_p, 0,920 RK3576_CLKSEL_CON(86), 7, 2, MFLAGS, 2, 5, DFLAGS,921 RK3576_CLKGATE_CON(31), 5, GFLAGS),922 GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0,923 RK3576_CLKGATE_CON(28), 9, GFLAGS),924 GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0,925 RK3576_CLKGATE_CON(29), 0, GFLAGS),926 COMPOSITE_NODIV(PCLK_NPUTOP_ROOT, "pclk_nputop_root", mux_100m_50m_24m_p, 0,927 RK3576_CLKSEL_CON(87), 0, 2, MFLAGS,928 RK3576_CLKGATE_CON(31), 8, GFLAGS),929 GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0,930 RK3576_CLKGATE_CON(31), 10, GFLAGS),931 COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_100m_24m_p, 0,932 RK3576_CLKSEL_CON(87), 2, 1, MFLAGS,933 RK3576_CLKGATE_CON(31), 11, GFLAGS),934 GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,935 RK3576_CLKGATE_CON(31), 12, GFLAGS),936 GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,937 RK3576_CLKGATE_CON(31), 13, GFLAGS),938 GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0,939 RK3576_CLKGATE_CON(31), 14, GFLAGS),940 GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,941 RK3576_CLKGATE_CON(31), 15, GFLAGS),942 GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0,943 RK3576_CLKGATE_CON(32), 0, GFLAGS),944 COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0,945 RK3576_CLKSEL_CON(87), 3, 2, MFLAGS,946 RK3576_CLKGATE_CON(32), 5, GFLAGS),947 GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,948 RK3576_CLKGATE_CON(32), 7, GFLAGS),949 COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,950 RK3576_CLKSEL_CON(87), 10, 1, MFLAGS, 5, 5, DFLAGS,951 RK3576_CLKGATE_CON(32), 9, GFLAGS),952 GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0,953 RK3576_CLKGATE_CON(32), 12, GFLAGS),954 955 /* nvm */956 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,957 RK3576_CLKSEL_CON(88), 0, 2, MFLAGS,958 RK3576_CLKGATE_CON(33), 0, GFLAGS),959 COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, CLK_IS_CRITICAL,960 RK3576_CLKSEL_CON(88), 7, 1, MFLAGS, 2, 5, DFLAGS,961 RK3576_CLKGATE_CON(33), 1, GFLAGS),962 COMPOSITE(SCLK_FSPI_X2, "sclk_fspi_x2", gpll_cpll_24m_p, 0,963 RK3576_CLKSEL_CON(89), 6, 2, MFLAGS, 0, 6, DFLAGS,964 RK3576_CLKGATE_CON(33), 6, GFLAGS),965 GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0,966 RK3576_CLKGATE_CON(33), 7, GFLAGS),967 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0,968 RK3576_CLKSEL_CON(89), 14, 2, MFLAGS, 8, 6, DFLAGS,969 RK3576_CLKGATE_CON(33), 8, GFLAGS),970 GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0,971 RK3576_CLKGATE_CON(33), 9, GFLAGS),972 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,973 RK3576_CLKGATE_CON(33), 10, GFLAGS),974 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,975 RK3576_CLKSEL_CON(90), 0, 2, MFLAGS,976 RK3576_CLKGATE_CON(33), 11, GFLAGS),977 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,978 RK3576_CLKGATE_CON(33), 12, GFLAGS),979 980 /* usb */981 COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0,982 RK3576_CLKSEL_CON(115), 5, 1, MFLAGS, 0, 5, DFLAGS,983 RK3576_CLKGATE_CON(47), 0, GFLAGS),984 COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, CLK_IS_CRITICAL,985 RK3576_CLKSEL_CON(115), 11, 1, MFLAGS, 6, 5, DFLAGS,986 RK3576_CLKGATE_CON(47), 1, GFLAGS),987 COMPOSITE_NODIV(PCLK_USB_ROOT, "pclk_usb_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,988 RK3576_CLKSEL_CON(115), 12, 2, MFLAGS,989 RK3576_CLKGATE_CON(47), 2, GFLAGS),990 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0,991 RK3576_CLKGATE_CON(47), 5, GFLAGS),992 GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0,993 RK3576_CLKGATE_CON(47), 6, GFLAGS),994 GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0,995 RK3576_CLKGATE_CON(47), 7, GFLAGS),996 GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0,997 RK3576_CLKGATE_CON(47), 12, GFLAGS),998 GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0,999 RK3576_CLKGATE_CON(47), 13, GFLAGS),1000 GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0,1001 RK3576_CLKGATE_CON(47), 15, GFLAGS),1002 1003 /* vdec */1004 COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, 0,1005 RK3576_CLKSEL_CON(110), 0, 2, MFLAGS,1006 RK3576_CLKGATE_CON(45), 0, GFLAGS),1007 COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", gpll_cpll_aupll_spll_p, 0,1008 RK3576_CLKSEL_CON(110), 7, 2, MFLAGS, 2, 5, DFLAGS,1009 RK3576_CLKGATE_CON(45), 1, GFLAGS),1010 COMPOSITE(ACLK_RKVDEC_ROOT_BAK, "aclk_rkvdec_root_bak", cpll_vpll_lpll_bpll_p, 0,1011 RK3576_CLKSEL_CON(110), 14, 2, MFLAGS, 9, 5, DFLAGS,1012 RK3576_CLKGATE_CON(45), 2, GFLAGS),1013 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,1014 RK3576_CLKGATE_CON(45), 3, GFLAGS),1015 COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_lpll_bpll_p, 0,1016 RK3576_CLKSEL_CON(111), 5, 2, MFLAGS, 0, 5, DFLAGS,1017 RK3576_CLKGATE_CON(45), 8, GFLAGS),1018 GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0,1019 RK3576_CLKGATE_CON(45), 9, GFLAGS),1020 1021 /* venc */1022 COMPOSITE_NODIV(HCLK_VEPU0_ROOT, "hclk_vepu0_root", mux_200m_100m_50m_24m_p, 0,1023 RK3576_CLKSEL_CON(124), 0, 2, MFLAGS,1024 RK3576_CLKGATE_CON(51), 0, GFLAGS),1025 COMPOSITE(ACLK_VEPU0_ROOT, "aclk_vepu0_root", gpll_cpll_p, 0,1026 RK3576_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,1027 RK3576_CLKGATE_CON(51), 1, GFLAGS),1028 COMPOSITE(CLK_VEPU0_CORE, "clk_vepu0_core", gpll_cpll_spll_lpll_bpll_p, 0,1029 RK3576_CLKSEL_CON(124), 13, 3, MFLAGS, 8, 5, DFLAGS,1030 RK3576_CLKGATE_CON(51), 6, GFLAGS),1031 GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0,1032 RK3576_CLKGATE_CON(51), 4, GFLAGS),1033 GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0,1034 RK3576_CLKGATE_CON(51), 5, GFLAGS),1035 1036 /* vi */1037 COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL,1038 RK3576_CLKSEL_CON(128), 5, 3, MFLAGS, 0, 5, DFLAGS,1039 RK3576_CLKGATE_CON(53), 0, GFLAGS),1040 COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", "aclk_vi_root", 0,1041 RK3576_CLKSEL_CON(130), 10, 3, DFLAGS,1042 RK3576_CLKGATE_CON(54), 13, GFLAGS),1043 COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, CLK_IS_CRITICAL,1044 RK3576_CLKSEL_CON(128), 8, 2, MFLAGS,1045 RK3576_CLKGATE_CON(53), 1, GFLAGS),1046 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,1047 RK3576_CLKSEL_CON(128), 10, 2, MFLAGS,1048 RK3576_CLKGATE_CON(53), 2, GFLAGS),1049 COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,1050 RK3576_CLKSEL_CON(129), 5, 1, MFLAGS, 0, 5, DFLAGS,1051 RK3576_CLKGATE_CON(53), 6, GFLAGS),1052 GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,1053 RK3576_CLKGATE_CON(53), 7, GFLAGS),1054 GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,1055 RK3576_CLKGATE_CON(53), 8, GFLAGS),1056 COMPOSITE(CLK_ISP_CORE, "clk_isp_core", gpll_spll_isppvtpll_bpll_lpll_p, 0,1057 RK3576_CLKSEL_CON(129), 11, 3, MFLAGS, 6, 5, DFLAGS,1058 RK3576_CLKGATE_CON(53), 9, GFLAGS),1059 GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0,1060 RK3576_CLKGATE_CON(53), 10, GFLAGS),1061 GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0,1062 RK3576_CLKGATE_CON(53), 11, GFLAGS),1063 GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,1064 RK3576_CLKGATE_CON(53), 12, GFLAGS),1065 GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,1066 RK3576_CLKGATE_CON(53), 13, GFLAGS),1067 GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0,1068 RK3576_CLKGATE_CON(53), 15, GFLAGS),1069 GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0,1070 RK3576_CLKGATE_CON(54), 0, GFLAGS),1071 GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0,1072 RK3576_CLKGATE_CON(54), 1, GFLAGS),1073 GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,1074 RK3576_CLKGATE_CON(54), 4, GFLAGS),1075 GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,1076 RK3576_CLKGATE_CON(54), 5, GFLAGS),1077 GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,1078 RK3576_CLKGATE_CON(54), 6, GFLAGS),1079 GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,1080 RK3576_CLKGATE_CON(54), 7, GFLAGS),1081 GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,1082 RK3576_CLKGATE_CON(54), 8, GFLAGS),1083 COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0,1084 RK3576_CLKSEL_CON(130), 7, 2, MFLAGS,1085 RK3576_CLKGATE_CON(54), 10, GFLAGS),1086 GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,1087 RK3576_CLKGATE_CON(54), 11, GFLAGS),1088 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL,1089 RK3576_CLKSEL_CON(144), 5, 3, MFLAGS, 0, 5, DFLAGS,1090 RK3576_CLKGATE_CON(61), 0, GFLAGS),1091 COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,1092 RK3576_CLKSEL_CON(144), 10, 2, MFLAGS,1093 RK3576_CLKGATE_CON(61), 2, GFLAGS),1094 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,1095 RK3576_CLKSEL_CON(144), 12, 2, MFLAGS,1096 RK3576_CLKGATE_CON(61), 3, GFLAGS),1097 GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,1098 RK3576_CLKGATE_CON(61), 8, GFLAGS),1099 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,1100 RK3576_CLKGATE_CON(61), 9, GFLAGS),1101 COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,1102 RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS,1103 RK3576_CLKGATE_CON(61), 10, GFLAGS),1104 COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,1105 RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS,1106 RK3576_CLKGATE_CON(61), 11, GFLAGS),1107 COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,1108 RK3576_CLKSEL_CON(147), 8, 3, MFLAGS, 0, 8, DFLAGS,1109 RK3576_CLKGATE_CON(61), 12, GFLAGS),1110 COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,1111 RK3576_CLKSEL_CON(147), 11, 1, MFLAGS,1112 RK3576_CLKGATE_CON(61), 13, GFLAGS),1113 COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,1114 RK3576_CLKSEL_CON(147), 12, 1, MFLAGS,1115 RK3576_CLKGATE_CON(62), 0, GFLAGS),1116 COMPOSITE_NODIV(DCLK_VP2, "dclk_vp2", dclk_vp2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,1117 RK3576_CLKSEL_CON(147), 13, 1, MFLAGS,1118 RK3576_CLKGATE_CON(62), 1, GFLAGS),1119 1120 /* vo0 */1121 COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_lpll_bpll_p, 0,1122 RK3576_CLKSEL_CON(149), 5, 2, MFLAGS, 0, 5, DFLAGS,1123 RK3576_CLKGATE_CON(63), 0, GFLAGS),1124 COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,1125 RK3576_CLKSEL_CON(149), 7, 2, MFLAGS,1126 RK3576_CLKGATE_CON(63), 1, GFLAGS),1127 COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_150m_100m_50m_24m_p, 0,1128 RK3576_CLKSEL_CON(149), 11, 2, MFLAGS,1129 RK3576_CLKGATE_CON(63), 3, GFLAGS),1130 GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0,1131 RK3576_CLKGATE_CON(63), 12, GFLAGS),1132 GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0,1133 RK3576_CLKGATE_CON(63), 13, GFLAGS),1134 GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,1135 RK3576_CLKGATE_CON(63), 14, GFLAGS),1136 GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0,1137 RK3576_CLKGATE_CON(64), 4, GFLAGS),1138 GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0,1139 RK3576_CLKGATE_CON(64), 5, GFLAGS),1140 COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_spll_vpll_bpll_lpll_p, 0,1141 RK3576_CLKSEL_CON(151), 7, 3, MFLAGS, 0, 7, DFLAGS,1142 RK3576_CLKGATE_CON(64), 6, GFLAGS),1143 GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0,1144 RK3576_CLKGATE_CON(64), 7, GFLAGS),1145 COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,1146 RK3576_CLKSEL_CON(151), 15, 1, MFLAGS, 10, 5, DFLAGS,1147 RK3576_CLKGATE_CON(64), 8, GFLAGS),1148 GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0,1149 RK3576_CLKGATE_CON(64), 9, GFLAGS),1150 GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0,1151 RK3576_CLKGATE_CON(64), 13, GFLAGS),1152 GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,1153 RK3576_CLKGATE_CON(64), 14, GFLAGS),1154 COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,1155 RK3576_CLKSEL_CON(152), 1, 2, MFLAGS,1156 RK3576_CLKGATE_CON(64), 15, GFLAGS),1157 COMPOSITE(MCLK_SAI5_8CH_SRC, "mclk_sai5_8ch_src", audio_frac_int_p, 0,1158 RK3576_CLKSEL_CON(154), 10, 3, MFLAGS, 2, 8, DFLAGS,1159 RK3576_CLKGATE_CON(65), 3, GFLAGS),1160 COMPOSITE_NODIV(MCLK_SAI5_8CH, "mclk_sai5_8ch", mclk_sai5_8ch_p, CLK_SET_RATE_PARENT,1161 RK3576_CLKSEL_CON(154), 13, 1, MFLAGS,1162 RK3576_CLKGATE_CON(65), 4, GFLAGS),1163 GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0,1164 RK3576_CLKGATE_CON(65), 5, GFLAGS),1165 COMPOSITE(MCLK_SAI6_8CH_SRC, "mclk_sai6_8ch_src", audio_frac_int_p, 0,1166 RK3576_CLKSEL_CON(155), 8, 3, MFLAGS, 0, 8, DFLAGS,1167 RK3576_CLKGATE_CON(65), 7, GFLAGS),1168 COMPOSITE_NODIV(MCLK_SAI6_8CH, "mclk_sai6_8ch", mclk_sai6_8ch_p, CLK_SET_RATE_PARENT,1169 RK3576_CLKSEL_CON(155), 11, 1, MFLAGS,1170 RK3576_CLKGATE_CON(65), 8, GFLAGS),1171 GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0,1172 RK3576_CLKGATE_CON(65), 9, GFLAGS),1173 GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0,1174 RK3576_CLKGATE_CON(65), 10, GFLAGS),1175 COMPOSITE(MCLK_SPDIF_TX2, "mclk_spdif_tx2", audio_frac_int_p, 0,1176 RK3576_CLKSEL_CON(156), 5, 3, MFLAGS, 0, 5, DFLAGS,1177 RK3576_CLKGATE_CON(65), 13, GFLAGS),1178 GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0,1179 RK3576_CLKGATE_CON(65), 14, GFLAGS),1180 COMPOSITE(MCLK_SPDIF_RX2, "mclk_spdif_rx2", gpll_cpll_aupll_p, 0,1181 RK3576_CLKSEL_CON(156), 13, 2, MFLAGS, 8, 5, DFLAGS,1182 RK3576_CLKGATE_CON(65), 15, GFLAGS),1183 1184 /* vo1 */1185 COMPOSITE(ACLK_VO1_ROOT, "aclk_vo1_root", gpll_cpll_lpll_bpll_p, 0,1186 RK3576_CLKSEL_CON(158), 5, 2, MFLAGS, 0, 5, DFLAGS,1187 RK3576_CLKGATE_CON(67), 1, GFLAGS),1188 COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,1189 RK3576_CLKSEL_CON(158), 7, 2, MFLAGS,1190 RK3576_CLKGATE_CON(67), 2, GFLAGS),1191 COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_100m_50m_24m_p, 0,1192 RK3576_CLKSEL_CON(158), 9, 2, MFLAGS,1193 RK3576_CLKGATE_CON(67), 3, GFLAGS),1194 COMPOSITE(MCLK_SAI8_8CH_SRC, "mclk_sai8_8ch_src", audio_frac_int_p, 0,1195 RK3576_CLKSEL_CON(157), 8, 3, MFLAGS, 0, 8, DFLAGS,1196 RK3576_CLKGATE_CON(66), 1, GFLAGS),1197 COMPOSITE_NODIV(MCLK_SAI8_8CH, "mclk_sai8_8ch", mclk_sai8_8ch_p, CLK_SET_RATE_PARENT,1198 RK3576_CLKSEL_CON(157), 11, 1, MFLAGS,1199 RK3576_CLKGATE_CON(66), 2, GFLAGS),1200 GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0,1201 RK3576_CLKGATE_CON(66), 0, GFLAGS),1202 COMPOSITE(MCLK_SAI7_8CH_SRC, "mclk_sai7_8ch_src", audio_frac_int_p, 0,1203 RK3576_CLKSEL_CON(159), 8, 3, MFLAGS, 0, 8, DFLAGS,1204 RK3576_CLKGATE_CON(67), 8, GFLAGS),1205 COMPOSITE_NODIV(MCLK_SAI7_8CH, "mclk_sai7_8ch", mclk_sai7_8ch_p, CLK_SET_RATE_PARENT,1206 RK3576_CLKSEL_CON(159), 11, 1, MFLAGS,1207 RK3576_CLKGATE_CON(67), 9, GFLAGS),1208 GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0,1209 RK3576_CLKGATE_CON(67), 10, GFLAGS),1210 GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0,1211 RK3576_CLKGATE_CON(67), 11, GFLAGS),1212 GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0,1213 RK3576_CLKGATE_CON(67), 12, GFLAGS),1214 GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0,1215 RK3576_CLKGATE_CON(67), 13, GFLAGS),1216 COMPOSITE(MCLK_SPDIF_TX3, "mclk_spdif_tx3", audio_frac_int_p, 0,1217 RK3576_CLKSEL_CON(160), 8, 3, MFLAGS, 0, 8, DFLAGS,1218 RK3576_CLKGATE_CON(67), 14, GFLAGS),1219 COMPOSITE_NOMUX(CLK_AUX16MHZ_0, "clk_aux16mhz_0", "gpll", 0,1220 RK3576_CLKSEL_CON(161), 0, 8, DFLAGS,1221 RK3576_CLKGATE_CON(67), 15, GFLAGS),1222 GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0,1223 RK3576_CLKGATE_CON(68), 0, GFLAGS),1224 GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0,1225 RK3576_CLKGATE_CON(68), 1, GFLAGS),1226 GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0,1227 RK3576_CLKGATE_CON(68), 4, GFLAGS),1228 GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0,1229 RK3576_CLKGATE_CON(68), 5, GFLAGS),1230 GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,1231 RK3576_CLKGATE_CON(68), 6, GFLAGS),1232 GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0,1233 RK3576_CLKGATE_CON(68), 7, GFLAGS),1234 GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0,1235 RK3576_CLKGATE_CON(68), 9, GFLAGS),1236 COMPOSITE(MCLK_SAI9_8CH_SRC, "mclk_sai9_8ch_src", audio_frac_int_p, 0,1237 RK3576_CLKSEL_CON(162), 8, 3, MFLAGS, 0, 8, DFLAGS,1238 RK3576_CLKGATE_CON(68), 10, GFLAGS),1239 COMPOSITE_NODIV(MCLK_SAI9_8CH, "mclk_sai9_8ch", mclk_sai9_8ch_p, CLK_SET_RATE_PARENT,1240 RK3576_CLKSEL_CON(162), 11, 1, MFLAGS,1241 RK3576_CLKGATE_CON(68), 11, GFLAGS),1242 COMPOSITE(MCLK_SPDIF_TX4, "mclk_spdif_tx4", audio_frac_int_p, 0,1243 RK3576_CLKSEL_CON(163), 8, 3, MFLAGS, 0, 8, DFLAGS,1244 RK3576_CLKGATE_CON(68), 12, GFLAGS),1245 COMPOSITE(MCLK_SPDIF_TX5, "mclk_spdif_tx5", audio_frac_int_p, 0,1246 RK3576_CLKSEL_CON(164), 8, 3, MFLAGS, 0, 8, DFLAGS,1247 RK3576_CLKGATE_CON(68), 13, GFLAGS),1248 1249 /* vpu */1250 COMPOSITE(ACLK_VPU_ROOT, "aclk_vpu_root", gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL,1251 RK3576_CLKSEL_CON(118), 5, 3, MFLAGS, 0, 5, DFLAGS,1252 RK3576_CLKGATE_CON(49), 0, GFLAGS),1253 COMPOSITE_NODIV(ACLK_VPU_MID_ROOT, "aclk_vpu_mid_root", mux_600m_400m_300m_24m_p, 0,1254 RK3576_CLKSEL_CON(118), 8, 2, MFLAGS,1255 RK3576_CLKGATE_CON(49), 1, GFLAGS),1256 COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, 0,1257 RK3576_CLKSEL_CON(118), 10, 2, MFLAGS,1258 RK3576_CLKGATE_CON(49), 2, GFLAGS),1259 COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, 0,1260 RK3576_CLKSEL_CON(119), 5, 2, MFLAGS, 0, 5, DFLAGS,1261 RK3576_CLKGATE_CON(49), 3, GFLAGS),1262 COMPOSITE_NODIV(ACLK_VPU_LOW_ROOT, "aclk_vpu_low_root", mux_400m_200m_100m_24m_p, 0,1263 RK3576_CLKSEL_CON(119), 7, 2, MFLAGS,1264 RK3576_CLKGATE_CON(49), 4, GFLAGS),1265 GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0,1266 RK3576_CLKGATE_CON(49), 13, GFLAGS),1267 GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0,1268 RK3576_CLKGATE_CON(49), 14, GFLAGS),1269 COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", gpll_spll_cpll_bpll_lpll_p, 0,1270 RK3576_CLKSEL_CON(120), 5, 3, MFLAGS, 0, 5, DFLAGS,1271 RK3576_CLKGATE_CON(49), 15, GFLAGS),1272 GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0,1273 RK3576_CLKGATE_CON(50), 0, GFLAGS),1274 GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0,1275 RK3576_CLKGATE_CON(50), 1, GFLAGS),1276 GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0,1277 RK3576_CLKGATE_CON(50), 2, GFLAGS),1278 GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0,1279 RK3576_CLKGATE_CON(50), 3, GFLAGS),1280 COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0,1281 RK3576_CLKSEL_CON(120), 13, 1, MFLAGS, 8, 5, DFLAGS,1282 RK3576_CLKGATE_CON(50), 4, GFLAGS),1283 GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0,1284 RK3576_CLKGATE_CON(50), 5, GFLAGS),1285 GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0,1286 RK3576_CLKGATE_CON(50), 6, GFLAGS),1287 COMPOSITE(CLK_CORE_RGA2E_1, "clk_core_rga2e_1", gpll_spll_cpll_bpll_lpll_p, 0,1288 RK3576_CLKSEL_CON(121), 5, 3, MFLAGS, 0, 5, DFLAGS,1289 RK3576_CLKGATE_CON(50), 7, GFLAGS),1290 MUX(0, "dclk_ebc_frac_src_p", gpll_cpll_vpll_aupll_24m_p, 0,1291 RK3576_CLKSEL_CON(123), 0, 3, MFLAGS),1292 COMPOSITE_FRAC(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", "dclk_ebc_frac_src_p", 0,1293 RK3576_CLKSEL_CON(122), 0,1294 RK3576_CLKGATE_CON(50), 9, GFLAGS),1295 GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0,1296 RK3576_CLKGATE_CON(50), 11, GFLAGS),1297 GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0,1298 RK3576_CLKGATE_CON(50), 10, GFLAGS),1299 COMPOSITE(DCLK_EBC, "dclk_ebc", dclk_ebc_p, CLK_SET_RATE_NO_REPARENT,1300 RK3576_CLKSEL_CON(123), 12, 3, MFLAGS, 3, 9, DFLAGS,1301 RK3576_CLKGATE_CON(50), 12, GFLAGS),1302 1303 /* vepu */1304 COMPOSITE_NODIV(HCLK_VEPU1_ROOT, "hclk_vepu1_root", mux_200m_100m_50m_24m_p, 0,1305 RK3576_CLKSEL_CON(178), 0, 2, MFLAGS,1306 RK3576_CLKGATE_CON(78), 0, GFLAGS),1307 COMPOSITE(ACLK_VEPU1_ROOT, "aclk_vepu1_root", gpll_cpll_p, 0,1308 RK3576_CLKSEL_CON(180), 5, 1, MFLAGS, 0, 5, DFLAGS,1309 RK3576_CLKGATE_CON(79), 0, GFLAGS),1310 GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0,1311 RK3576_CLKGATE_CON(79), 3, GFLAGS),1312 GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0,1313 RK3576_CLKGATE_CON(79), 4, GFLAGS),1314 COMPOSITE(CLK_VEPU1_CORE, "clk_vepu1_core", gpll_cpll_spll_lpll_bpll_p, 0,1315 RK3576_CLKSEL_CON(180), 11, 3, MFLAGS, 6, 5, DFLAGS,1316 RK3576_CLKGATE_CON(79), 5, GFLAGS),1317 1318 /* php */1319 COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_100m_50m_24m_p, 0,1320 RK3576_CLKSEL_CON(92), 0, 2, MFLAGS,1321 RK3576_CLKGATE_CON(34), 0, GFLAGS),1322 COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0,1323 RK3576_CLKSEL_CON(92), 9, 1, MFLAGS, 4, 5, DFLAGS,1324 RK3576_CLKGATE_CON(34), 7, GFLAGS),1325 GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0,1326 RK3576_CLKGATE_CON(34), 13, GFLAGS),1327 GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0,1328 RK3576_CLKGATE_CON(34), 14, GFLAGS),1329 GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0,1330 RK3576_CLKGATE_CON(34), 15, GFLAGS),1331 GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0,1332 RK3576_CLKGATE_CON(35), 0, GFLAGS),1333 GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0,1334 RK3576_CLKGATE_CON(35), 1, GFLAGS),1335 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0,1336 RK3576_CLKGATE_CON(35), 3, GFLAGS),1337 GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0,1338 RK3576_CLKGATE_CON(35), 4, GFLAGS),1339 GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0,1340 RK3576_CLKGATE_CON(35), 5, GFLAGS),1341 GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0,1342 RK3576_CLKGATE_CON(35), 11, GFLAGS),1343 GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0,1344 RK3576_CLKGATE_CON(35), 13, GFLAGS),1345 GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0,1346 RK3576_CLKGATE_CON(35), 14, GFLAGS),1347 GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0,1348 RK3576_CLKGATE_CON(36), 0, GFLAGS),1349 GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0,1350 RK3576_CLKGATE_CON(36), 7, GFLAGS),1351 GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0,1352 RK3576_CLKGATE_CON(36), 8, GFLAGS),1353 GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0,1354 RK3576_CLKGATE_CON(36), 9, GFLAGS),1355 GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0,1356 RK3576_CLKGATE_CON(36), 10, GFLAGS),1357 GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0,1358 RK3576_CLKGATE_CON(36), 11, GFLAGS),1359 COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,1360 RK3576_CLKSEL_CON(93), 7, 1, MFLAGS, 0, 7, DFLAGS,1361 RK3576_CLKGATE_CON(37), 0, GFLAGS),1362 COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,1363 RK3576_CLKSEL_CON(93), 15, 1, MFLAGS, 8, 7, DFLAGS,1364 RK3576_CLKGATE_CON(37), 1, GFLAGS),1365 GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL,1366 RK3576_CLKGATE_CON(37), 2, GFLAGS),1367 GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL,1368 RK3576_CLKGATE_CON(37), 3, GFLAGS),1369 GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0,1370 RK3576_CLKGATE_CON(37), 4, GFLAGS),1371 GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0,1372 RK3576_CLKGATE_CON(37), 5, GFLAGS),1373 1374 /* audio */1375 COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0,1376 RK3576_CLKSEL_CON(42), 0, 2, MFLAGS,1377 RK3576_CLKGATE_CON(7), 1, GFLAGS),1378 GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0,1379 RK3576_CLKGATE_CON(7), 3, GFLAGS),1380 GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0,1381 RK3576_CLKGATE_CON(7), 4, GFLAGS),1382 GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0,1383 RK3576_CLKGATE_CON(7), 5, GFLAGS),1384 GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0,1385 RK3576_CLKGATE_CON(7), 6, GFLAGS),1386 COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0,1387 RK3576_CLKSEL_CON(42), 7, 2, MFLAGS, 2, 5, DFLAGS,1388 RK3576_CLKGATE_CON(7), 7, GFLAGS),1389 COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0,1390 RK3576_CLKSEL_CON(42), 14, 2, MFLAGS, 9, 5, DFLAGS,1391 RK3576_CLKGATE_CON(7), 8, GFLAGS),1392 COMPOSITE(CLK_ASRC_4CH_0, "clk_asrc_4ch_0", gpll_cpll_aupll_p, 0,1393 RK3576_CLKSEL_CON(43), 5, 2, MFLAGS, 0, 5, DFLAGS,1394 RK3576_CLKGATE_CON(7), 9, GFLAGS),1395 COMPOSITE(CLK_ASRC_4CH_1, "clk_asrc_4ch_1", gpll_cpll_aupll_p, 0,1396 RK3576_CLKSEL_CON(43), 12, 2, MFLAGS, 7, 5, DFLAGS,1397 RK3576_CLKGATE_CON(7), 10, GFLAGS),1398 COMPOSITE(MCLK_SAI0_8CH_SRC, "mclk_sai0_8ch_src", audio_frac_int_p, 0,1399 RK3576_CLKSEL_CON(44), 8, 3, MFLAGS, 0, 8, DFLAGS,1400 RK3576_CLKGATE_CON(7), 11, GFLAGS),1401 COMPOSITE_NODIV(MCLK_SAI0_8CH, "mclk_sai0_8ch", mclk_sai0_8ch_p, CLK_SET_RATE_PARENT,1402 RK3576_CLKSEL_CON(44), 11, 2, MFLAGS,1403 RK3576_CLKGATE_CON(7), 12, GFLAGS),1404 GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0,1405 RK3576_CLKGATE_CON(7), 13, GFLAGS),1406 GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0,1407 RK3576_CLKGATE_CON(7), 14, GFLAGS),1408 COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0,1409 RK3576_CLKSEL_CON(45), 5, 2, MFLAGS, 0, 5, DFLAGS,1410 RK3576_CLKGATE_CON(7), 15, GFLAGS),1411 GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0,1412 RK3576_CLKGATE_CON(8), 0, GFLAGS),1413 COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0,1414 RK3576_CLKSEL_CON(45), 12, 2, MFLAGS, 7, 5, DFLAGS,1415 RK3576_CLKGATE_CON(8), 1, GFLAGS),1416 COMPOSITE(MCLK_SAI1_8CH_SRC, "mclk_sai1_8ch_src", audio_frac_int_p, 0,1417 RK3576_CLKSEL_CON(46), 8, 3, MFLAGS, 0, 8, DFLAGS,1418 RK3576_CLKGATE_CON(8), 4, GFLAGS),1419 COMPOSITE_NODIV(MCLK_SAI1_8CH, "mclk_sai1_8ch", mclk_sai1_8ch_p, CLK_SET_RATE_PARENT,1420 RK3576_CLKSEL_CON(46), 11, 1, MFLAGS,1421 RK3576_CLKGATE_CON(8), 5, GFLAGS),1422 GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0,1423 RK3576_CLKGATE_CON(8), 6, GFLAGS),1424 COMPOSITE(MCLK_SAI2_2CH_SRC, "mclk_sai2_2ch_src", audio_frac_int_p, 0,1425 RK3576_CLKSEL_CON(47), 8, 3, MFLAGS, 0, 8, DFLAGS,1426 RK3576_CLKGATE_CON(8), 7, GFLAGS),1427 COMPOSITE_NODIV(MCLK_SAI2_2CH, "mclk_sai2_2ch", mclk_sai2_2ch_p, CLK_SET_RATE_PARENT,1428 RK3576_CLKSEL_CON(47), 11, 2, MFLAGS,1429 RK3576_CLKGATE_CON(8), 8, GFLAGS),1430 GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0,1431 RK3576_CLKGATE_CON(8), 10, GFLAGS),1432 COMPOSITE(MCLK_SAI3_2CH_SRC, "mclk_sai3_2ch_src", audio_frac_int_p, 0,1433 RK3576_CLKSEL_CON(48), 8, 3, MFLAGS, 0, 8, DFLAGS,1434 RK3576_CLKGATE_CON(8), 11, GFLAGS),1435 COMPOSITE_NODIV(MCLK_SAI3_2CH, "mclk_sai3_2ch", mclk_sai3_2ch_p, CLK_SET_RATE_PARENT,1436 RK3576_CLKSEL_CON(48), 11, 2, MFLAGS,1437 RK3576_CLKGATE_CON(8), 12, GFLAGS),1438 GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0,1439 RK3576_CLKGATE_CON(8), 14, GFLAGS),1440 COMPOSITE(MCLK_SAI4_2CH_SRC, "mclk_sai4_2ch_src", audio_frac_int_p, 0,1441 RK3576_CLKSEL_CON(49), 8, 3, MFLAGS, 0, 8, DFLAGS,1442 RK3576_CLKGATE_CON(8), 15, GFLAGS),1443 COMPOSITE_NODIV(MCLK_SAI4_2CH, "mclk_sai4_2ch", mclk_sai4_2ch_p, CLK_SET_RATE_PARENT,1444 RK3576_CLKSEL_CON(49), 11, 2, MFLAGS,1445 RK3576_CLKGATE_CON(9), 0, GFLAGS),1446 GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0,1447 RK3576_CLKGATE_CON(9), 2, GFLAGS),1448 GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0,1449 RK3576_CLKGATE_CON(9), 3, GFLAGS),1450 GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0,1451 RK3576_CLKGATE_CON(9), 4, GFLAGS),1452 COMPOSITE(CLK_PDM1, "clk_pdm1", audio_frac_int_p, 0,1453 RK3576_CLKSEL_CON(50), 9, 3, MFLAGS, 0, 9, DFLAGS,1454 RK3576_CLKGATE_CON(9), 5, GFLAGS),1455 GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,1456 RK3576_CLKGATE_CON(9), 7, GFLAGS),1457 GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0,1458 RK3576_CLKGATE_CON(3), 5, GFLAGS),1459 COMPOSITE(MCLK_PDM1, "mclk_pdm1", audio_frac_int_p, 0,1460 RK3576_CLKSEL_CON(51), 5, 3, MFLAGS, 0, 5, DFLAGS,1461 RK3576_CLKGATE_CON(9), 8, GFLAGS),1462 GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0,1463 RK3576_CLKGATE_CON(9), 9, GFLAGS),1464 COMPOSITE(MCLK_SPDIF_TX0, "mclk_spdif_tx0", audio_frac_int_p, 0,1465 RK3576_CLKSEL_CON(52), 8, 3, MFLAGS, 0, 8, DFLAGS,1466 RK3576_CLKGATE_CON(9), 10, GFLAGS),1467 GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0,1468 RK3576_CLKGATE_CON(9), 11, GFLAGS),1469 COMPOSITE(MCLK_SPDIF_TX1, "mclk_spdif_tx1", audio_frac_int_p, 0,1470 RK3576_CLKSEL_CON(53), 8, 3, MFLAGS, 0, 8, DFLAGS,1471 RK3576_CLKGATE_CON(9), 12, GFLAGS),1472 GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0,1473 RK3576_CLKGATE_CON(9), 13, GFLAGS),1474 GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0,1475 RK3576_CLKGATE_CON(9), 14, GFLAGS),1476 GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0,1477 RK3576_CLKGATE_CON(9), 15, GFLAGS),1478 GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0,1479 RK3576_CLKGATE_CON(10), 0, GFLAGS),1480 GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0,1481 RK3576_CLKGATE_CON(10), 1, GFLAGS),1482 1483 /* sdgmac */1484 COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0,1485 RK3576_CLKSEL_CON(103), 0, 2, MFLAGS,1486 RK3576_CLKGATE_CON(42), 0, GFLAGS),1487 COMPOSITE(ACLK_SDGMAC_ROOT, "aclk_sdgmac_root", gpll_cpll_p, CLK_IS_CRITICAL,1488 RK3576_CLKSEL_CON(103), 7, 1, MFLAGS, 2, 5, DFLAGS,1489 RK3576_CLKGATE_CON(42), 1, GFLAGS),1490 COMPOSITE_NODIV(PCLK_SDGMAC_ROOT, "pclk_sdgmac_root", mux_100m_50m_24m_p, 0,1491 RK3576_CLKSEL_CON(103), 8, 2, MFLAGS,1492 RK3576_CLKGATE_CON(42), 2, GFLAGS),1493 GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0,1494 RK3576_CLKGATE_CON(42), 7, GFLAGS),1495 GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0,1496 RK3576_CLKGATE_CON(42), 8, GFLAGS),1497 GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0,1498 RK3576_CLKGATE_CON(42), 9, GFLAGS),1499 GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0,1500 RK3576_CLKGATE_CON(42), 10, GFLAGS),1501 COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,1502 RK3576_CLKSEL_CON(104), 6, 2, MFLAGS, 0, 6, DFLAGS,1503 RK3576_CLKGATE_CON(42), 11, GFLAGS),1504 GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0,1505 RK3576_CLKGATE_CON(42), 12, GFLAGS),1506 COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", clk_gmac1_ptp_ref_src_p, 0,1507 RK3576_CLKSEL_CON(104), 13, 2, MFLAGS, 8, 5, DFLAGS,1508 RK3576_CLKGATE_CON(42), 15, GFLAGS),1509 COMPOSITE(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", clk_gmac0_ptp_ref_src_p, 0,1510 RK3576_CLKSEL_CON(105), 5, 2, MFLAGS, 0, 5, DFLAGS,1511 RK3576_CLKGATE_CON(43), 0, GFLAGS),1512 GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", 0,1513 RK3576_CLKGATE_CON(42), 13, GFLAGS),1514 GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", 0,1515 RK3576_CLKGATE_CON(42), 14, GFLAGS),1516 COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0,1517 RK3576_CLKSEL_CON(105), 13, 2, MFLAGS, 7, 6, DFLAGS,1518 RK3576_CLKGATE_CON(43), 1, GFLAGS),1519 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0,1520 RK3576_CLKGATE_CON(43), 2, GFLAGS),1521 COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_24m_p, 0,1522 RK3576_CLKSEL_CON(106), 6, 2, MFLAGS, 0, 6, DFLAGS,1523 RK3576_CLKGATE_CON(43), 3, GFLAGS),1524 GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0,1525 RK3576_CLKGATE_CON(43), 4, GFLAGS),1526 COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, CLK_IS_CRITICAL,1527 RK3576_CLKSEL_CON(106), 13, 1, MFLAGS, 8, 5, DFLAGS,1528 RK3576_CLKGATE_CON(43), 5, GFLAGS),1529 GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0,1530 RK3576_CLKGATE_CON(43), 7, GFLAGS),1531 GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0,1532 RK3576_CLKGATE_CON(43), 8, GFLAGS),1533 COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_p, 0,1534 RK3576_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS,1535 RK3576_CLKGATE_CON(43), 9, GFLAGS),1536 GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0,1537 RK3576_CLKGATE_CON(43), 10, GFLAGS),1538 COMPOSITE(CLK_HSGPIO_TX, "clk_hsgpio_tx", gpll_cpll_24m_p, 0,1539 RK3576_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS,1540 RK3576_CLKGATE_CON(43), 11, GFLAGS),1541 COMPOSITE(CLK_HSGPIO_RX, "clk_hsgpio_rx", gpll_cpll_24m_p, 0,1542 RK3576_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS,1543 RK3576_CLKGATE_CON(43), 12, GFLAGS),1544 GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0,1545 RK3576_CLKGATE_CON(43), 13, GFLAGS),1546 1547 /* phpphy */1548 GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", CLK_IS_CRITICAL,1549 RK3576_PHP_CLKGATE_CON(0), 2, GFLAGS),1550 GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpphy_root", 0,1551 RK3576_PHP_CLKGATE_CON(0), 5, GFLAGS),1552 GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpphy_root", 0,1553 RK3576_PHP_CLKGATE_CON(0), 7, GFLAGS),1554 COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0,1555 RK3576_PHP_CLKSEL_CON(0), 2, 5, DFLAGS,1556 RK3576_PHP_CLKGATE_CON(1), 1, GFLAGS),1557 COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", "ppll", 0,1558 RK3576_PHP_CLKSEL_CON(0), 7, 5, DFLAGS,1559 RK3576_PHP_CLKGATE_CON(1), 2, GFLAGS),1560 COMPOSITE_NODIV(CLK_REF_PCIE0_PHY, "clk_ref_pcie0_phy", clk_ref_pcie0_phy_p, 0,1561 RK3576_PHP_CLKSEL_CON(0), 12, 2, MFLAGS,1562 RK3576_PHP_CLKGATE_CON(1), 5, GFLAGS),1563 COMPOSITE_NODIV(CLK_REF_PCIE1_PHY, "clk_ref_pcie1_phy", clk_ref_pcie0_phy_p, 0,1564 RK3576_PHP_CLKSEL_CON(0), 14, 2, MFLAGS,1565 RK3576_PHP_CLKGATE_CON(1), 8, GFLAGS),1566 COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", CLK_IS_CRITICAL,1567 RK3576_PHP_CLKSEL_CON(1), 0, 8, DFLAGS,1568 RK3576_PHP_CLKGATE_CON(1), 9, GFLAGS),1569 1570 /* pmu */1571 GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0,1572 RK3576_PMU_CLKGATE_CON(3), 2, GFLAGS),1573 COMPOSITE_NOMUX(CLK_100M_PMU_SRC, "clk_100m_pmu_src", "cpll", 0,1574 RK3576_PMU_CLKSEL_CON(4), 4, 5, DFLAGS,1575 RK3576_PMU_CLKGATE_CON(3), 3, GFLAGS),1576 FACTOR_GATE(CLK_50M_PMU_SRC, "clk_50m_pmu_src", "clk_100m_pmu_src", 0, 1, 2,1577 RK3576_PMU_CLKGATE_CON(3), 4, GFLAGS),1578 COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL,1579 RK3576_PMU_CLKSEL_CON(4), 0, 2, MFLAGS,1580 RK3576_PMU_CLKGATE_CON(3), 0, GFLAGS),1581 COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", mux_pmu200m_pmu100m_pmu50m_24m_p, 0,1582 RK3576_PMU_CLKSEL_CON(4), 2, 2, MFLAGS,1583 RK3576_PMU_CLKGATE_CON(3), 1, GFLAGS),1584 COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", mux_pmu100m_pmu50m_24m_p, 0,1585 RK3576_PMU_CLKSEL_CON(20), 0, 2, MFLAGS,1586 RK3576_PMU_CLKGATE_CON(7), 0, GFLAGS),1587 GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,1588 RK3576_PMU_CLKGATE_CON(7), 3, GFLAGS),1589 GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", CLK_IS_CRITICAL,1590 RK3576_PMU_CLKGATE_CON(7), 9, GFLAGS),1591 GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL,1592 RK3576_PMU_CLKGATE_CON(3), 15, GFLAGS),1593 GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL,1594 RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS),1595 GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL,1596 RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS),1597 GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0,1598 RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS),1599 GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0,1600 RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS),1601 GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0,1602 RK3576_PMU_CLKGATE_CON(0), 8, GFLAGS),1603 GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0,1604 RK3576_PMU_CLKGATE_CON(0), 12, GFLAGS),1605 COMPOSITE_NOMUX(CLK_PMUPHY_REF_SRC, "clk_pmuphy_ref_src", "cpll", 0,1606 RK3576_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,1607 RK3576_PMU_CLKGATE_CON(0), 13, GFLAGS),1608 GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0,1609 RK3576_PMU_CLKGATE_CON(0), 15, GFLAGS),1610 GATE(CLK_HDMITXHDP, "clk_hdmitxhdp", "xin24m", 0,1611 RK3576_PMU_CLKGATE_CON(1), 13, GFLAGS),1612 GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0,1613 RK3576_PMU_CLKGATE_CON(2), 0, GFLAGS),1614 MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0,1615 RK3576_PMU_CLKSEL_CON(3), 0, 2, MFLAGS),1616 GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0,1617 RK3576_PMU_CLKGATE_CON(2), 5, GFLAGS),1618 GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0,1619 RK3576_PMU_CLKGATE_CON(3), 12, GFLAGS),1620 COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, 0,1621 RK3576_PMU_CLKSEL_CON(4), 14, 1, MFLAGS, 9, 5, DFLAGS,1622 RK3576_PMU_CLKGATE_CON(3), 14, GFLAGS),1623 GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0,1624 RK3576_PMU_CLKGATE_CON(4), 5, GFLAGS),1625 COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,1626 RK3576_PMU_CLKSEL_CON(4), 15, 1, MFLAGS,1627 RK3576_PMU_CLKGATE_CON(4), 6, GFLAGS),1628 GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0,1629 RK3576_PMU_CLKGATE_CON(4), 7, GFLAGS),1630 COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", mux_pmu100m_24m_32k_p, 0,1631 RK3576_PMU_CLKSEL_CON(5), 0, 2, MFLAGS,1632 RK3576_PMU_CLKGATE_CON(4), 8, GFLAGS),1633 GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0,1634 RK3576_PMU_CLKGATE_CON(4), 9, GFLAGS),1635 GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0,1636 RK3576_PMU_CLKGATE_CON(4), 10, GFLAGS),1637 GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0,1638 RK3576_PMU_CLKGATE_CON(4), 11, GFLAGS),1639 COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", mux_pmu100m_pmu50m_24m_p, 0,1640 RK3576_PMU_CLKSEL_CON(5), 2, 2, MFLAGS,1641 RK3576_PMU_CLKGATE_CON(4), 12, GFLAGS),1642 GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0,1643 RK3576_PMU_CLKGATE_CON(4), 13, GFLAGS),1644 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0,1645 RK3576_PMU_CLKGATE_CON(5), 1, GFLAGS),1646 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0,1647 RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS,1648 RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS),1649 COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0,1650 RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS,1651 RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS),1652 GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0,1653 RK3576_PMU_CLKGATE_CON(5), 6, GFLAGS),1654 GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0,1655 RK3576_PMU_CLKGATE_CON(5), 13, GFLAGS),1656 GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,1657 RK3576_PMU_CLKGATE_CON(5), 15, GFLAGS),1658 GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0,1659 RK3576_PMU_CLKGATE_CON(6), 0, GFLAGS),1660 GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,1661 RK3576_PMU_CLKGATE_CON(6), 1, GFLAGS),1662 GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0,1663 RK3576_PMU_CLKGATE_CON(6), 8, GFLAGS),1664 COMPOSITE(CLK_HPTIMER_SRC, "clk_hptimer_src", cpll_24m_p, CLK_IS_CRITICAL,1665 RK3576_PMU_CLKSEL_CON(11), 6, 1, MFLAGS, 1, 5, DFLAGS,1666 RK3576_PMU_CLKGATE_CON(6), 10, GFLAGS),1667 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,1668 RK3576_PMU_CLKGATE_CON(7), 6, GFLAGS),1669 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,1670 RK3576_PMU_CLKSEL_CON(20), 2, 1, MFLAGS,1671 RK3576_PMU_CLKGATE_CON(7), 7, GFLAGS),1672 GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL,1673 RK3576_PMU_CLKGATE_CON(7), 8, GFLAGS),1674 GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0,1675 RK3576_PMU_CLKGATE_CON(5), 7, GFLAGS),1676 1677 /* phy ref */1678 MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0,1679 RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS),1680 MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0,1681 RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS),1682 MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0,1683 RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS),1684 MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0,1685 RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS),1686 1687 /* secure ns */1688 COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL,1689 RK3576_SECURE_NS_CLKSEL_CON(0), 0, 2, MFLAGS,1690 RK3576_SECURE_NS_CLKGATE_CON(0), 0, GFLAGS),1691 COMPOSITE_NODIV(HCLK_SECURE_NS, "hclk_secure_ns", mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL,1692 RK3576_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS,1693 RK3576_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS),1694 COMPOSITE_NODIV(PCLK_SECURE_NS, "pclk_secure_ns", mux_116m_58m_24m_p, CLK_IS_CRITICAL,1695 RK3576_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS,1696 RK3576_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS),1697 GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0,1698 RK3576_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS),1699 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0,1700 RK3576_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS),1701 GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,1702 RK3576_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS),1703 GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0,1704 RK3576_NON_SECURE_GATING_CON00, 14, GFLAGS),1705 GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0,1706 RK3576_NON_SECURE_GATING_CON00, 13, GFLAGS),1707 GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0,1708 RK3576_NON_SECURE_GATING_CON00, 1, GFLAGS),1709 1710 /* io */1711 GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0,1712 RK3576_CLKGATE_CON(59), 1, GFLAGS),1713 GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0,1714 RK3576_CLKGATE_CON(59), 2, GFLAGS),1715 GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0,1716 RK3576_CLKGATE_CON(59), 3, GFLAGS),1717 GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0,1718 RK3576_CLKGATE_CON(59), 4, GFLAGS),1719 GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0,1720 RK3576_CLKGATE_CON(59), 5, GFLAGS),1721};1722 1723static void __init rk3576_clk_init(struct device_node *np)1724{1725 struct rockchip_clk_provider *ctx;1726 unsigned long clk_nr_clks;1727 void __iomem *reg_base;1728 struct regmap *grf;1729 1730 clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,1731 ARRAY_SIZE(rk3576_clk_branches)) + 1;1732 1733 grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");1734 if (IS_ERR(grf)) {1735 pr_err("%s: could not get PMU0 GRF syscon\n", __func__);1736 return;1737 }1738 1739 reg_base = of_iomap(np, 0);1740 if (!reg_base) {1741 pr_err("%s: could not map cru region\n", __func__);1742 return;1743 }1744 1745 ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);1746 if (IS_ERR(ctx)) {1747 pr_err("%s: rockchip clk init failed\n", __func__);1748 iounmap(reg_base);1749 return;1750 }1751 1752 ctx->grf = grf;1753 1754 rockchip_clk_register_plls(ctx, rk3576_pll_clks,1755 ARRAY_SIZE(rk3576_pll_clks),1756 RK3576_GRF_SOC_STATUS0);1757 1758 rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",1759 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),1760 &rk3576_cpulclk_data, rk3576_cpulclk_rates,1761 ARRAY_SIZE(rk3576_cpulclk_rates));1762 rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b",1763 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),1764 &rk3576_cpubclk_data, rk3576_cpubclk_rates,1765 ARRAY_SIZE(rk3576_cpubclk_rates));1766 1767 rockchip_clk_register_branches(ctx, rk3576_clk_branches,1768 ARRAY_SIZE(rk3576_clk_branches));1769 1770 rk3576_rst_init(np, reg_base);1771 1772 rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL);1773 1774 rockchip_clk_of_add_provider(np, ctx);1775}1776 1777CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init);1778 1779struct clk_rk3576_inits {1780 void (*inits)(struct device_node *np);1781};1782 1783static const struct clk_rk3576_inits clk_rk3576_cru_init = {1784 .inits = rk3576_clk_init,1785};1786 1787static const struct of_device_id clk_rk3576_match_table[] = {1788 {1789 .compatible = "rockchip,rk3576-cru",1790 .data = &clk_rk3576_cru_init,1791 },1792 { }1793};1794 1795static int clk_rk3576_probe(struct platform_device *pdev)1796{1797 const struct clk_rk3576_inits *init_data;1798 struct device *dev = &pdev->dev;1799 1800 init_data = device_get_match_data(dev);1801 if (!init_data)1802 return -EINVAL;1803 1804 if (init_data->inits)1805 init_data->inits(dev->of_node);1806 1807 return 0;1808}1809 1810static struct platform_driver clk_rk3576_driver = {1811 .probe = clk_rk3576_probe,1812 .driver = {1813 .name = "clk-rk3576",1814 .of_match_table = clk_rk3576_match_table,1815 .suppress_bind_attrs = true,1816 },1817};1818builtin_platform_driver_probe(clk_rk3576_driver, clk_rk3576_probe);1819