1106 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 *5 * Common Clock Framework support for Exynos3250 SoC.6 */7 8#include <linux/clk-provider.h>9#include <linux/io.h>10#include <linux/of.h>11#include <linux/of_address.h>12#include <linux/platform_device.h>13 14#include <dt-bindings/clock/exynos3250.h>15 16#include "clk.h"17#include "clk-cpu.h"18#include "clk-pll.h"19 20#define SRC_LEFTBUS 0x420021#define DIV_LEFTBUS 0x450022#define GATE_IP_LEFTBUS 0x480023#define SRC_RIGHTBUS 0x820024#define DIV_RIGHTBUS 0x850025#define GATE_IP_RIGHTBUS 0x880026#define GATE_IP_PERIR 0x896027#define MPLL_LOCK 0xc01028#define MPLL_CON0 0xc11029#define VPLL_LOCK 0xc02030#define VPLL_CON0 0xc12031#define UPLL_LOCK 0xc03032#define UPLL_CON0 0xc13033#define SRC_TOP0 0xc21034#define SRC_TOP1 0xc21435#define SRC_CAM 0xc22036#define SRC_MFC 0xc22837#define SRC_G3D 0xc22c38#define SRC_LCD 0xc23439#define SRC_ISP 0xc23840#define SRC_FSYS 0xc24041#define SRC_PERIL0 0xc25042#define SRC_PERIL1 0xc25443#define SRC_MASK_TOP 0xc31044#define SRC_MASK_CAM 0xc32045#define SRC_MASK_LCD 0xc33446#define SRC_MASK_ISP 0xc33847#define SRC_MASK_FSYS 0xc34048#define SRC_MASK_PERIL0 0xc35049#define SRC_MASK_PERIL1 0xc35450#define DIV_TOP 0xc51051#define DIV_CAM 0xc52052#define DIV_MFC 0xc52853#define DIV_G3D 0xc52c54#define DIV_LCD 0xc53455#define DIV_ISP 0xc53856#define DIV_FSYS0 0xc54057#define DIV_FSYS1 0xc54458#define DIV_FSYS2 0xc54859#define DIV_PERIL0 0xc55060#define DIV_PERIL1 0xc55461#define DIV_PERIL3 0xc55c62#define DIV_PERIL4 0xc56063#define DIV_PERIL5 0xc56464#define DIV_CAM1 0xc56865#define CLKDIV2_RATIO 0xc58066#define GATE_SCLK_CAM 0xc82067#define GATE_SCLK_MFC 0xc82868#define GATE_SCLK_G3D 0xc82c69#define GATE_SCLK_LCD 0xc83470#define GATE_SCLK_ISP_TOP 0xc83871#define GATE_SCLK_FSYS 0xc84072#define GATE_SCLK_PERIL 0xc85073#define GATE_IP_CAM 0xc92074#define GATE_IP_MFC 0xc92875#define GATE_IP_G3D 0xc92c76#define GATE_IP_LCD 0xc93477#define GATE_IP_ISP 0xc93878#define GATE_IP_FSYS 0xc94079#define GATE_IP_PERIL 0xc95080#define GATE_BLOCK 0xc97081#define APLL_LOCK 0x1400082#define APLL_CON0 0x1410083#define SRC_CPU 0x1420084#define DIV_CPU0 0x1450085#define DIV_CPU1 0x1450486#define PWR_CTRL1 0x1502087#define PWR_CTRL2 0x1502488 89/* Below definitions are used for PWR_CTRL settings */90#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)91#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)92#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)93#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)94#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)95#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)96#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)97#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)98#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)99#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)100#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)101#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)102 103/* NOTE: Must be equal to the last clock ID increased by one */104#define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1)105#define CLKS_NR_DMC (CLK_DIV_DMCD + 1)106#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1)107 108static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {109 SRC_LEFTBUS,110 DIV_LEFTBUS,111 GATE_IP_LEFTBUS,112 SRC_RIGHTBUS,113 DIV_RIGHTBUS,114 GATE_IP_RIGHTBUS,115 GATE_IP_PERIR,116 MPLL_LOCK,117 MPLL_CON0,118 VPLL_LOCK,119 VPLL_CON0,120 UPLL_LOCK,121 UPLL_CON0,122 SRC_TOP0,123 SRC_TOP1,124 SRC_CAM,125 SRC_MFC,126 SRC_G3D,127 SRC_LCD,128 SRC_ISP,129 SRC_FSYS,130 SRC_PERIL0,131 SRC_PERIL1,132 SRC_MASK_TOP,133 SRC_MASK_CAM,134 SRC_MASK_LCD,135 SRC_MASK_ISP,136 SRC_MASK_FSYS,137 SRC_MASK_PERIL0,138 SRC_MASK_PERIL1,139 DIV_TOP,140 DIV_CAM,141 DIV_MFC,142 DIV_G3D,143 DIV_LCD,144 DIV_ISP,145 DIV_FSYS0,146 DIV_FSYS1,147 DIV_FSYS2,148 DIV_PERIL0,149 DIV_PERIL1,150 DIV_PERIL3,151 DIV_PERIL4,152 DIV_PERIL5,153 DIV_CAM1,154 CLKDIV2_RATIO,155 GATE_SCLK_CAM,156 GATE_SCLK_MFC,157 GATE_SCLK_G3D,158 GATE_SCLK_LCD,159 GATE_SCLK_ISP_TOP,160 GATE_SCLK_FSYS,161 GATE_SCLK_PERIL,162 GATE_IP_CAM,163 GATE_IP_MFC,164 GATE_IP_G3D,165 GATE_IP_LCD,166 GATE_IP_ISP,167 GATE_IP_FSYS,168 GATE_IP_PERIL,169 GATE_BLOCK,170 APLL_LOCK,171 SRC_CPU,172 DIV_CPU0,173 DIV_CPU1,174 PWR_CTRL1,175 PWR_CTRL2,176};177 178/* list of all parent clock list */179PNAME(mout_vpllsrc_p) = { "fin_pll", };180 181PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };182PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };183PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };184PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };185 186PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };187PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };188PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };189PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };190 191PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };192PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };193 194PNAME(mout_gdl_p) = { "mout_mpll_user_l", };195PNAME(mout_gdr_p) = { "mout_mpll_user_r", };196 197PNAME(mout_aclk_400_mcuisp_sub_p)198 = { "fin_pll", "div_aclk_400_mcuisp", };199PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };200PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };201PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };202PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };203 204PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };205PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };206PNAME(group_sclk_p) = { "xxti", "xusbxti",207 "none", "none",208 "none", "none", "div_mpll_pre",209 "mout_epll_user", "mout_vpll", };210PNAME(group_sclk_audio_p) = { "audiocdclk", "none",211 "none", "none",212 "xxti", "xusbxti",213 "div_mpll_pre", "mout_epll_user",214 "mout_vpll", };215PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",216 "none", "none", "none",217 "none", "div_mpll_pre",218 "mout_epll_user", "mout_vpll",219 "none", "none", "none",220 "div_cam_blk_320", };221PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",222 "m_bitclkhsdiv4_2l", "none",223 "none", "none", "div_mpll_pre",224 "mout_epll_user", "mout_vpll",225 "none", "none", "none",226 "div_lcd_blk_145", };227 228PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };229PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };230 231static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {232 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),233 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),234 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),235 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),236 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),237 238 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */239 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),240};241 242static const struct samsung_mux_clock mux_clks[] __initconst = {243 /*244 * NOTE: Following table is sorted by register address in ascending245 * order and then bitfield shift in descending order, as it is done246 * in the User's Manual. When adding new entries, please make sure247 * that the order is preserved, to avoid merge conflicts and make248 * further work with defined data easier.249 */250 251 /* SRC_LEFTBUS */252 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,253 SRC_LEFTBUS, 4, 1),254 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),255 256 /* SRC_RIGHTBUS */257 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,258 SRC_RIGHTBUS, 4, 1),259 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),260 261 /* SRC_TOP0 */262 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),263 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),264 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),265 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),266 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),267 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),268 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),269 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),270 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),271 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),272 273 /* SRC_TOP1 */274 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),275 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,276 SRC_TOP1, 24, 1),277 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),278 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),279 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),280 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),281 282 /* SRC_CAM */283 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),284 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),285 286 /* SRC_MFC */287 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),288 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),289 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),290 291 /* SRC_G3D */292 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),293 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),294 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),295 296 /* SRC_LCD */297 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),298 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),299 300 /* SRC_ISP */301 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),302 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),303 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),304 305 /* SRC_FSYS */306 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),307 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),308 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),309 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),310 311 /* SRC_PERIL0 */312 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),313 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),314 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),315 316 /* SRC_PERIL1 */317 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),318 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),319 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),320 321 /* SRC_CPU */322 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,323 SRC_CPU, 24, 1),324 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),325 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,326 CLK_SET_RATE_PARENT, 0),327 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,328 CLK_SET_RATE_PARENT, 0),329};330 331static const struct samsung_div_clock div_clks[] __initconst = {332 /*333 * NOTE: Following table is sorted by register address in ascending334 * order and then bitfield shift in descending order, as it is done335 * in the User's Manual. When adding new entries, please make sure336 * that the order is preserved, to avoid merge conflicts and make337 * further work with defined data easier.338 */339 340 /* DIV_LEFTBUS */341 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),342 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),343 344 /* DIV_RIGHTBUS */345 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),346 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),347 348 /* DIV_TOP */349 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),350 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",351 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),352 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),353 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),354 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),355 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),356 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),357 358 /* DIV_CAM */359 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),360 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),361 362 /* DIV_MFC */363 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),364 365 /* DIV_G3D */366 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),367 368 /* DIV_LCD */369 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,370 CLK_SET_RATE_PARENT, 0),371 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),372 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),373 374 /* DIV_ISP */375 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),376 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",377 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),378 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),379 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",380 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),381 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),382 383 /* DIV_FSYS0 */384 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,385 CLK_SET_RATE_PARENT, 0),386 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),387 388 /* DIV_FSYS1 */389 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,390 CLK_SET_RATE_PARENT, 0),391 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),392 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,393 CLK_SET_RATE_PARENT, 0),394 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),395 396 /* DIV_FSYS2 */397 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,398 CLK_SET_RATE_PARENT, 0),399 DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),400 401 /* DIV_PERIL0 */402 DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),403 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),404 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),405 406 /* DIV_PERIL1 */407 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,408 CLK_SET_RATE_PARENT, 0),409 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),410 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,411 CLK_SET_RATE_PARENT, 0),412 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),413 414 /* DIV_PERIL4 */415 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),416 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),417 418 /* DIV_PERIL5 */419 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),420 421 /* DIV_CPU0 */422 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),423 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),424 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),425 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),426 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),427 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),428 429 /* DIV_CPU1 */430 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),431 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),432};433 434static const struct samsung_gate_clock gate_clks[] __initconst = {435 /*436 * NOTE: Following table is sorted by register address in ascending437 * order and then bitfield shift in descending order, as it is done438 * in the User's Manual. When adding new entries, please make sure439 * that the order is preserved, to avoid merge conflicts and make440 * further work with defined data easier.441 */442 443 /* GATE_IP_LEFTBUS */444 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,445 CLK_IGNORE_UNUSED, 0),446 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,447 CLK_IGNORE_UNUSED, 0),448 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,449 CLK_IGNORE_UNUSED, 0),450 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,451 CLK_IGNORE_UNUSED, 0),452 453 /* GATE_IP_RIGHTBUS */454 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",455 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),456 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",457 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),458 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",459 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),460 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,461 CLK_IGNORE_UNUSED, 0),462 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,463 CLK_IGNORE_UNUSED, 0),464 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,465 CLK_IGNORE_UNUSED, 0),466 467 /* GATE_IP_PERIR */468 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,469 CLK_IGNORE_UNUSED, 0),470 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,471 CLK_IGNORE_UNUSED, 0),472 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",473 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),474 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",475 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),476 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,477 CLK_IGNORE_UNUSED, 0),478 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",479 GATE_IP_PERIR, 17, 0, 0),480 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),481 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),482 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),483 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),484 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,485 CLK_IGNORE_UNUSED, 0),486 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,487 CLK_IGNORE_UNUSED, 0),488 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,489 CLK_IGNORE_UNUSED, 0),490 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,491 CLK_IGNORE_UNUSED, 0),492 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,493 CLK_IGNORE_UNUSED, 0),494 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,495 CLK_IGNORE_UNUSED, 0),496 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,497 CLK_IGNORE_UNUSED, 0),498 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,499 CLK_IGNORE_UNUSED, 0),500 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,501 CLK_IGNORE_UNUSED, 0),502 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,503 CLK_IGNORE_UNUSED, 0),504 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,505 CLK_IGNORE_UNUSED, 0),506 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,507 CLK_IGNORE_UNUSED, 0),508 509 /* GATE_SCLK_CAM */510 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",511 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),512 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",513 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),514 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",515 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),516 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",517 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),518 519 /* GATE_SCLK_MFC */520 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",521 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),522 523 /* GATE_SCLK_G3D */524 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",525 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),526 527 /* GATE_SCLK_LCD */528 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",529 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),530 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",531 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),532 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",533 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),534 535 /* GATE_SCLK_ISP_TOP */536 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",537 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),538 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",539 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),540 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",541 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),542 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",543 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),544 545 /* GATE_SCLK_FSYS */546 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),547 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",548 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),549 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",550 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),551 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",552 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),553 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",554 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),555 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",556 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),557 558 /* GATE_SCLK_PERIL */559 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",560 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),561 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",562 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),563 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",564 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),565 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",566 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),567 568 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",569 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),570 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",571 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),572 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",573 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),574 575 /* GATE_IP_CAM */576 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,577 CLK_IGNORE_UNUSED, 0),578 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",579 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),580 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",581 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),582 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",583 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),584 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",585 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),586 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",587 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),588 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",589 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),590 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",591 GATE_IP_CAM, 11, 0, 0),592 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",593 GATE_IP_CAM, 9, 0, 0),594 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",595 GATE_IP_CAM, 8, 0, 0),596 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",597 GATE_IP_CAM, 7, 0, 0),598 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),599 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",600 GATE_IP_CAM, 2, 0, 0),601 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),602 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),603 604 /* GATE_IP_MFC */605 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,606 CLK_IGNORE_UNUSED, 0),607 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,608 CLK_IGNORE_UNUSED, 0),609 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),610 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),611 612 /* GATE_IP_G3D */613 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),614 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,615 CLK_IGNORE_UNUSED, 0),616 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,617 CLK_IGNORE_UNUSED, 0),618 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),619 620 /* GATE_IP_LCD */621 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,622 CLK_IGNORE_UNUSED, 0),623 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,624 CLK_IGNORE_UNUSED, 0),625 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,626 CLK_IGNORE_UNUSED, 0),627 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),628 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),629 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),630 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),631 632 /* GATE_IP_ISP */633 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),634 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",635 GATE_IP_ISP, 3, 0, 0),636 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",637 GATE_IP_ISP, 2, 0, 0),638 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",639 GATE_IP_ISP, 1, 0, 0),640 641 /* GATE_IP_FSYS */642 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),643 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,644 CLK_IGNORE_UNUSED, 0),645 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),646 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),647 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),648 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),649 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),650 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),651 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),652 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),653 654 /* GATE_IP_PERIL */655 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),656 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),657 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),658 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),659 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),660 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),661 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),662 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),663 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),664 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),665 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),666 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),667 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),668 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),669 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),670 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),671};672 673/* APLL & MPLL & BPLL & UPLL */674static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {675 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),676 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),677 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),678 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),679 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),680 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),681 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),682 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),683 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),684 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),685 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2),686 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2),687 PLL_35XX_RATE(24 * MHZ, 520000000, 260, 3, 2),688 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),689 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),690 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),691 PLL_35XX_RATE(24 * MHZ, 100000000, 200, 3, 4),692 { /* sentinel */ }693};694 695/* EPLL */696static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {697 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0),698 PLL_36XX_RATE(24 * MHZ, 288000000, 96, 2, 2, 0),699 PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3, 0),700 PLL_36XX_RATE(24 * MHZ, 144000000, 96, 2, 3, 0),701 PLL_36XX_RATE(24 * MHZ, 96000000, 128, 2, 4, 0),702 PLL_36XX_RATE(24 * MHZ, 84000000, 112, 2, 4, 0),703 PLL_36XX_RATE(24 * MHZ, 80000003, 106, 2, 4, 43691),704 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),705 PLL_36XX_RATE(24 * MHZ, 67737598, 270, 3, 5, 62285),706 PLL_36XX_RATE(24 * MHZ, 65535999, 174, 2, 5, 49982),707 PLL_36XX_RATE(24 * MHZ, 50000000, 200, 3, 5, 0),708 PLL_36XX_RATE(24 * MHZ, 49152002, 131, 2, 5, 4719),709 PLL_36XX_RATE(24 * MHZ, 48000000, 128, 2, 5, 0),710 PLL_36XX_RATE(24 * MHZ, 45158401, 180, 3, 5, 41524),711 { /* sentinel */ }712};713 714/* VPLL */715static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {716 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0),717 PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),718 PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2, 5046),719 PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2, 0),720 PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),721 PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),722 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0),723 PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),724 PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),725 PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2, 0),726 PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),727 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0),728 PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2, 0),729 PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),730 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0),731 PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3, 0),732 PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),733 PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),734 PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3, 0),735 PLL_36XX_RATE(24 * MHZ, 148500000, 99, 2, 3, 0),736 PLL_36XX_RATE(24 * MHZ, 148352005, 98, 2, 3, 59070),737 PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4, 0),738 PLL_36XX_RATE(24 * MHZ, 74250000, 99, 2, 4, 0),739 PLL_36XX_RATE(24 * MHZ, 74176002, 98, 2, 4, 59070),740 PLL_36XX_RATE(24 * MHZ, 54054000, 216, 3, 5, 14156),741 PLL_36XX_RATE(24 * MHZ, 54000000, 144, 2, 5, 0),742 { /* sentinel */ }743};744 745static const struct samsung_pll_clock exynos3250_plls[] __initconst = {746 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",747 APLL_LOCK, APLL_CON0, exynos3250_pll_rates),748 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",749 MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),750 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",751 VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),752 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",753 UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),754};755 756#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \757 (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \758 ((corem) << 4))759#define E3250_CPU_DIV1(hpm, copy) \760 (((hpm) << 4) | ((copy) << 0))761 762static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {763 { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },764 { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },765 { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },766 { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },767 { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },768 { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },769 { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },770 { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },771 { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },772 { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },773 { 0 },774};775 776static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {777 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,778 CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d),779};780 781static void __init exynos3_core_down_clock(void __iomem *reg_base)782{783 unsigned int tmp;784 785 /*786 * Enable arm clock down (in idle) and set arm divider787 * ratios in WFI/WFE state.788 */789 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |790 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |791 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |792 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);793 __raw_writel(tmp, reg_base + PWR_CTRL1);794 795 /*796 * Disable the clock up feature on Exynos4x12, in case it was797 * enabled by bootloader.798 */799 __raw_writel(0x0, reg_base + PWR_CTRL2);800}801 802static const struct samsung_cmu_info cmu_info __initconst = {803 .pll_clks = exynos3250_plls,804 .nr_pll_clks = ARRAY_SIZE(exynos3250_plls),805 .mux_clks = mux_clks,806 .nr_mux_clks = ARRAY_SIZE(mux_clks),807 .div_clks = div_clks,808 .nr_div_clks = ARRAY_SIZE(div_clks),809 .gate_clks = gate_clks,810 .nr_gate_clks = ARRAY_SIZE(gate_clks),811 .fixed_factor_clks = fixed_factor_clks,812 .nr_fixed_factor_clks = ARRAY_SIZE(fixed_factor_clks),813 .cpu_clks = exynos3250_cpu_clks,814 .nr_cpu_clks = ARRAY_SIZE(exynos3250_cpu_clks),815 .nr_clk_ids = CLKS_NR_MAIN,816 .clk_regs = exynos3250_cmu_clk_regs,817 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),818};819 820static void __init exynos3250_cmu_init(struct device_node *np)821{822 struct samsung_clk_provider *ctx;823 824 ctx = samsung_cmu_register_one(np, &cmu_info);825 if (!ctx)826 return;827 828 exynos3_core_down_clock(ctx->reg_base);829}830CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);831 832/*833 * CMU DMC834 */835 836#define BPLL_LOCK 0x0118837#define BPLL_CON0 0x0218838#define BPLL_CON1 0x021c839#define BPLL_CON2 0x0220840#define SRC_DMC 0x0300841#define DIV_DMC1 0x0504842#define GATE_BUS_DMC0 0x0700843#define GATE_BUS_DMC1 0x0704844#define GATE_BUS_DMC2 0x0708845#define GATE_BUS_DMC3 0x070c846#define GATE_SCLK_DMC 0x0800847#define GATE_IP_DMC0 0x0900848#define GATE_IP_DMC1 0x0904849#define EPLL_LOCK 0x1110850#define EPLL_CON0 0x1114851#define EPLL_CON1 0x1118852#define EPLL_CON2 0x111c853#define SRC_EPLL 0x1120854 855static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {856 BPLL_LOCK,857 BPLL_CON0,858 BPLL_CON1,859 BPLL_CON2,860 SRC_DMC,861 DIV_DMC1,862 GATE_BUS_DMC0,863 GATE_BUS_DMC1,864 GATE_BUS_DMC2,865 GATE_BUS_DMC3,866 GATE_SCLK_DMC,867 GATE_IP_DMC0,868 GATE_IP_DMC1,869 EPLL_LOCK,870 EPLL_CON0,871 EPLL_CON1,872 EPLL_CON2,873 SRC_EPLL,874};875 876PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };877PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };878PNAME(mout_mpll_mif_p) = { "fin_pll", "sclk_mpll_mif", };879PNAME(mout_dphy_p) = { "mout_mpll_mif", "mout_bpll", };880 881static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {882 /*883 * NOTE: Following table is sorted by register address in ascending884 * order and then bitfield shift in descending order, as it is done885 * in the User's Manual. When adding new entries, please make sure886 * that the order is preserved, to avoid merge conflicts and make887 * further work with defined data easier.888 */889 890 /* SRC_DMC */891 MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),892 MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),893 MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),894 MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC, 4, 1),895 896 /* SRC_EPLL */897 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),898};899 900static const struct samsung_div_clock dmc_div_clks[] __initconst = {901 /*902 * NOTE: Following table is sorted by register address in ascending903 * order and then bitfield shift in descending order, as it is done904 * in the User's Manual. When adding new entries, please make sure905 * that the order is preserved, to avoid merge conflicts and make906 * further work with defined data easier.907 */908 909 /* DIV_DMC1 */910 DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),911 DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),912 DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),913 DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),914 DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),915};916 917static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {918 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",919 BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),920 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",921 EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),922};923 924static const struct samsung_cmu_info dmc_cmu_info __initconst = {925 .pll_clks = exynos3250_dmc_plls,926 .nr_pll_clks = ARRAY_SIZE(exynos3250_dmc_plls),927 .mux_clks = dmc_mux_clks,928 .nr_mux_clks = ARRAY_SIZE(dmc_mux_clks),929 .div_clks = dmc_div_clks,930 .nr_div_clks = ARRAY_SIZE(dmc_div_clks),931 .nr_clk_ids = CLKS_NR_DMC,932 .clk_regs = exynos3250_cmu_dmc_clk_regs,933 .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),934};935 936static void __init exynos3250_cmu_dmc_init(struct device_node *np)937{938 samsung_cmu_register_one(np, &dmc_cmu_info);939}940CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",941 exynos3250_cmu_dmc_init);942 943 944/*945 * CMU ISP946 */947 948#define DIV_ISP0 0x300949#define DIV_ISP1 0x304950#define GATE_IP_ISP0 0x800951#define GATE_IP_ISP1 0x804952#define GATE_SCLK_ISP 0x900953 954static const struct samsung_div_clock isp_div_clks[] __initconst = {955 /*956 * NOTE: Following table is sorted by register address in ascending957 * order and then bitfield shift in descending order, as it is done958 * in the User's Manual. When adding new entries, please make sure959 * that the order is preserved, to avoid merge conflicts and make960 * further work with defined data easier.961 */962 /* DIV_ISP0 */963 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),964 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),965 966 /* DIV_ISP1 */967 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",968 DIV_ISP1, 8, 3),969 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",970 DIV_ISP1, 4, 3),971 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),972};973 974static const struct samsung_gate_clock isp_gate_clks[] __initconst = {975 /*976 * NOTE: Following table is sorted by register address in ascending977 * order and then bitfield shift in descending order, as it is done978 * in the User's Manual. When adding new entries, please make sure979 * that the order is preserved, to avoid merge conflicts and make980 * further work with defined data easier.981 */982 983 /* GATE_IP_ISP0 */984 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",985 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),986 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",987 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),988 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",989 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),990 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",991 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),992 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",993 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),994 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",995 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),996 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",997 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),998 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",999 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),1000 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",1001 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),1002 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",1003 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),1004 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",1005 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),1006 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",1007 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),1008 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",1009 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),1010 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",1011 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),1012 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",1013 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),1014 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",1015 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),1016 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",1017 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),1018 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",1019 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),1020 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",1021 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),1022 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",1023 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),1024 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",1025 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),1026 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",1027 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),1028 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",1029 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),1030 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",1031 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),1032 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",1033 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),1034 GATE(CLK_FD, "fd", "mout_aclk_266_sub",1035 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),1036 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",1037 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),1038 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",1039 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),1040 1041 /* GATE_IP_ISP1 */1042 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",1043 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),1044 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",1045 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),1046 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",1047 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),1048 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",1049 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),1050 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",1051 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),1052 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",1053 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),1054 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",1055 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),1056 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",1057 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),1058 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",1059 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),1060 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",1061 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),1062 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",1063 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),1064 1065 /* GATE_SCLK_ISP */1066 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",1067 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),1068};1069 1070static const struct samsung_cmu_info isp_cmu_info __initconst = {1071 .div_clks = isp_div_clks,1072 .nr_div_clks = ARRAY_SIZE(isp_div_clks),1073 .gate_clks = isp_gate_clks,1074 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),1075 .nr_clk_ids = CLKS_NR_ISP,1076};1077 1078static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)1079{1080 struct device_node *np = pdev->dev.of_node;1081 1082 samsung_cmu_register_one(np, &isp_cmu_info);1083 return 0;1084}1085 1086static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {1087 { .compatible = "samsung,exynos3250-cmu-isp", },1088 { /* sentinel */ }1089};1090 1091static struct platform_driver exynos3250_cmu_isp_driver __initdata = {1092 .driver = {1093 .name = "exynos3250-cmu-isp",1094 .suppress_bind_attrs = true,1095 .of_match_table = exynos3250_cmu_isp_of_match,1096 },1097};1098 1099static int __init exynos3250_cmu_platform_init(void)1100{1101 return platform_driver_probe(&exynos3250_cmu_isp_driver,1102 exynos3250_cmu_isp_probe);1103}1104subsys_initcall(exynos3250_cmu_platform_init);1105 1106