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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.4 * Author: Rahul Sharma <rahul.sharma@samsung.com>5 *6 * Common Clock Framework support for Exynos5260 SoC.7 */8 9#ifndef __CLK_EXYNOS5260_H10#define __CLK_EXYNOS5260_H11 12/*13*Registers for CMU_AUD14*/15#define MUX_SEL_AUD 0x020016#define MUX_ENABLE_AUD 0x030017#define MUX_STAT_AUD 0x040018#define MUX_IGNORE_AUD 0x050019#define DIV_AUD0 0x060020#define DIV_AUD1 0x060421#define DIV_STAT_AUD0 0x070022#define DIV_STAT_AUD1 0x070423#define EN_ACLK_AUD 0x080024#define EN_PCLK_AUD 0x090025#define EN_SCLK_AUD 0x0a0026#define EN_IP_AUD 0x0b0027 28/*29*Registers for CMU_DISP30*/31#define MUX_SEL_DISP0 0x020032#define MUX_SEL_DISP1 0x020433#define MUX_SEL_DISP2 0x020834#define MUX_SEL_DISP3 0x020C35#define MUX_SEL_DISP4 0x021036#define MUX_ENABLE_DISP0 0x030037#define MUX_ENABLE_DISP1 0x030438#define MUX_ENABLE_DISP2 0x030839#define MUX_ENABLE_DISP3 0x030c40#define MUX_ENABLE_DISP4 0x031041#define MUX_STAT_DISP0 0x040042#define MUX_STAT_DISP1 0x040443#define MUX_STAT_DISP2 0x040844#define MUX_STAT_DISP3 0x040c45#define MUX_STAT_DISP4 0x041046#define MUX_IGNORE_DISP0 0x050047#define MUX_IGNORE_DISP1 0x050448#define MUX_IGNORE_DISP2 0x050849#define MUX_IGNORE_DISP3 0x050c50#define MUX_IGNORE_DISP4 0x051051#define DIV_DISP 0x060052#define DIV_STAT_DISP 0x070053#define EN_ACLK_DISP 0x080054#define EN_PCLK_DISP 0x090055#define EN_SCLK_DISP0 0x0a0056#define EN_SCLK_DISP1 0x0a0457#define EN_IP_DISP 0x0b0058#define EN_IP_DISP_BUS 0x0b0459 60 61/*62*Registers for CMU_EGL63*/64#define EGL_PLL_LOCK 0x000065#define EGL_DPLL_LOCK 0x000466#define EGL_PLL_CON0 0x010067#define EGL_PLL_CON1 0x010468#define EGL_PLL_FREQ_DET 0x010c69#define EGL_DPLL_CON0 0x011070#define EGL_DPLL_CON1 0x011471#define EGL_DPLL_FREQ_DET 0x011c72#define MUX_SEL_EGL 0x020073#define MUX_ENABLE_EGL 0x030074#define MUX_STAT_EGL 0x040075#define DIV_EGL 0x060076#define DIV_EGL_PLL_FDET 0x060477#define DIV_STAT_EGL 0x070078#define DIV_STAT_EGL_PLL_FDET 0x070479#define EN_ACLK_EGL 0x080080#define EN_PCLK_EGL 0x090081#define EN_SCLK_EGL 0x0a0082#define EN_IP_EGL 0x0b0083#define CLKOUT_CMU_EGL 0x0c0084#define CLKOUT_CMU_EGL_DIV_STAT 0x0c0485#define ARMCLK_STOPCTRL 0x100086#define EAGLE_EMA_CTRL 0x100887#define EAGLE_EMA_STATUS 0x100c88#define PWR_CTRL 0x102089#define PWR_CTRL2 0x102490#define CLKSTOP_CTRL 0x102891#define INTR_SPREAD_EN 0x108092#define INTR_SPREAD_USE_STANDBYWFI 0x108493#define INTR_SPREAD_BLOCKING_DURATION 0x108894#define CMU_EGL_SPARE0 0x200095#define CMU_EGL_SPARE1 0x200496#define CMU_EGL_SPARE2 0x200897#define CMU_EGL_SPARE3 0x200c98#define CMU_EGL_SPARE4 0x201099 100/*101*Registers for CMU_FSYS102*/103 104#define MUX_SEL_FSYS0 0x0200105#define MUX_SEL_FSYS1 0x0204106#define MUX_ENABLE_FSYS0 0x0300107#define MUX_ENABLE_FSYS1 0x0304108#define MUX_STAT_FSYS0 0x0400109#define MUX_STAT_FSYS1 0x0404110#define MUX_IGNORE_FSYS0 0x0500111#define MUX_IGNORE_FSYS1 0x0504112#define EN_ACLK_FSYS 0x0800113#define EN_ACLK_FSYS_SECURE_RTIC 0x0804114#define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808115#define EN_PCLK_FSYS 0x0900116#define EN_SCLK_FSYS 0x0a00117#define EN_IP_FSYS 0x0b00118#define EN_IP_FSYS_SECURE_RTIC 0x0b04119#define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08120 121/*122*Registers for CMU_G2D123*/124 125#define MUX_SEL_G2D 0x0200126#define MUX_ENABLE_G2D 0x0300127#define MUX_STAT_G2D 0x0400128#define DIV_G2D 0x0600129#define DIV_STAT_G2D 0x0700130#define EN_ACLK_G2D 0x0800131#define EN_ACLK_G2D_SECURE_SSS 0x0804132#define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808133#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c134#define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810135#define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814136#define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818137#define EN_PCLK_G2D 0x0900138#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904139#define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908140#define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c141#define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910142#define EN_IP_G2D 0x0b00143#define EN_IP_G2D_SECURE_SSS 0x0b04144#define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08145#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c146#define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10147#define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14148#define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18149 150/*151*Registers for CMU_G3D152*/153 154#define G3D_PLL_LOCK 0x0000155#define G3D_PLL_CON0 0x0100156#define G3D_PLL_CON1 0x0104157#define G3D_PLL_FDET 0x010c158#define MUX_SEL_G3D 0x0200159#define MUX_EN_G3D 0x0300160#define MUX_STAT_G3D 0x0400161#define MUX_IGNORE_G3D 0x0500162#define DIV_G3D 0x0600163#define DIV_G3D_PLL_FDET 0x0604164#define DIV_STAT_G3D 0x0700165#define DIV_STAT_G3D_PLL_FDET 0x0704166#define EN_ACLK_G3D 0x0800167#define EN_PCLK_G3D 0x0900168#define EN_SCLK_G3D 0x0a00169#define EN_IP_G3D 0x0b00170#define CLKOUT_CMU_G3D 0x0c00171#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04172#define G3DCLK_STOPCTRL 0x1000173#define G3D_EMA_CTRL 0x1008174#define G3D_EMA_STATUS 0x100c175 176/*177*Registers for CMU_GSCL178*/179 180#define MUX_SEL_GSCL 0x0200181#define MUX_EN_GSCL 0x0300182#define MUX_STAT_GSCL 0x0400183#define MUX_IGNORE_GSCL 0x0500184#define DIV_GSCL 0x0600185#define DIV_STAT_GSCL 0x0700186#define EN_ACLK_GSCL 0x0800187#define EN_ACLK_GSCL_FIMC 0x0804188#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808189#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c190#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810191#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814192#define EN_PCLK_GSCL 0x0900193#define EN_PCLK_GSCL_FIMC 0x0904194#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908195#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c196#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910197#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914198#define EN_SCLK_GSCL 0x0a00199#define EN_SCLK_GSCL_FIMC 0x0a04200#define EN_IP_GSCL 0x0b00201#define EN_IP_GSCL_FIMC 0x0b04202#define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08203#define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c204#define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10205#define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14206 207/*208*Registers for CMU_ISP209*/210#define MUX_SEL_ISP0 0x0200211#define MUX_SEL_ISP1 0x0204212#define MUX_ENABLE_ISP0 0x0300213#define MUX_ENABLE_ISP1 0x0304214#define MUX_STAT_ISP0 0x0400215#define MUX_STAT_ISP1 0x0404216#define MUX_IGNORE_ISP0 0x0500217#define MUX_IGNORE_ISP1 0x0504218#define DIV_ISP 0x0600219#define DIV_STAT_ISP 0x0700220#define EN_ACLK_ISP0 0x0800221#define EN_ACLK_ISP1 0x0804222#define EN_PCLK_ISP0 0x0900223#define EN_PCLK_ISP1 0x0904224#define EN_SCLK_ISP 0x0a00225#define EN_IP_ISP0 0x0b00226#define EN_IP_ISP1 0x0b04227 228/*229*Registers for CMU_KFC230*/231#define KFC_PLL_LOCK 0x0000232#define KFC_PLL_CON0 0x0100233#define KFC_PLL_CON1 0x0104234#define KFC_PLL_FDET 0x010c235#define MUX_SEL_KFC0 0x0200236#define MUX_SEL_KFC2 0x0208237#define MUX_ENABLE_KFC0 0x0300238#define MUX_ENABLE_KFC2 0x0308239#define MUX_STAT_KFC0 0x0400240#define MUX_STAT_KFC2 0x0408241#define DIV_KFC 0x0600242#define DIV_KFC_PLL_FDET 0x0604243#define DIV_STAT_KFC 0x0700244#define DIV_STAT_KFC_PLL_FDET 0x0704245#define EN_ACLK_KFC 0x0800246#define EN_PCLK_KFC 0x0900247#define EN_SCLK_KFC 0x0a00248#define EN_IP_KFC 0x0b00249#define CLKOUT_CMU_KFC 0x0c00250#define CLKOUT_CMU_KFC_DIV_STAT 0x0c04251#define ARMCLK_STOPCTRL_KFC 0x1000252#define ARM_EMA_CTRL 0x1008253#define ARM_EMA_STATUS 0x100c254#define PWR_CTRL_KFC 0x1020255#define PWR_CTRL2_KFC 0x1024256#define CLKSTOP_CTRL_KFC 0x1028257#define INTR_SPREAD_ENABLE_KFC 0x1080258#define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084259#define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088260#define CMU_KFC_SPARE0 0x2000261#define CMU_KFC_SPARE1 0x2004262#define CMU_KFC_SPARE2 0x2008263#define CMU_KFC_SPARE3 0x200c264#define CMU_KFC_SPARE4 0x2010265 266/*267*Registers for CMU_MFC268*/269#define MUX_SEL_MFC 0x0200270#define MUX_ENABLE_MFC 0x0300271#define MUX_STAT_MFC 0x0400272#define DIV_MFC 0x0600273#define DIV_STAT_MFC 0x0700274#define EN_ACLK_MFC 0x0800275#define EN_ACLK_SECURE_SMMU2_MFC 0x0804276#define EN_PCLK_MFC 0x0900277#define EN_PCLK_SECURE_SMMU2_MFC 0x0904278#define EN_IP_MFC 0x0b00279#define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04280 281/*282*Registers for CMU_MIF283*/284#define MEM_PLL_LOCK 0x0000285#define BUS_PLL_LOCK 0x0004286#define MEDIA_PLL_LOCK 0x0008287#define MEM_PLL_CON0 0x0100288#define MEM_PLL_CON1 0x0104289#define MEM_PLL_FDET 0x010c290#define BUS_PLL_CON0 0x0110291#define BUS_PLL_CON1 0x0114292#define BUS_PLL_FDET 0x011c293#define MEDIA_PLL_CON0 0x0120294#define MEDIA_PLL_CON1 0x0124295#define MEDIA_PLL_FDET 0x012c296#define MUX_SEL_MIF 0x0200297#define MUX_ENABLE_MIF 0x0300298#define MUX_STAT_MIF 0x0400299#define MUX_IGNORE_MIF 0x0500300#define DIV_MIF 0x0600301#define DIV_MIF_PLL_FDET 0x0604302#define DIV_STAT_MIF 0x0700303#define DIV_STAT_MIF_PLL_FDET 0x0704304#define EN_ACLK_MIF 0x0800305#define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804306#define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808307#define EN_ACLK_MIF_SECURE_INTMEM 0x080c308#define EN_PCLK_MIF 0x0900309#define EN_PCLK_MIF_SECURE_MONOCNT 0x0904310#define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908311#define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c312#define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910313#define EN_SCLK_MIF 0x0a00314#define EN_IP_MIF 0x0b00315#define EN_IP_MIF_SECURE_MONOCNT 0x0b04316#define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08317#define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c318#define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10319#define EN_IP_MIF_SECURE_INTEMEM 0x0b14320#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04321#define DREX_FREQ_CTRL 0x1000322#define PAUSE 0x1004323#define DDRPHY_LOCK_CTRL 0x1008324#define CLKOUT_CMU_MIF 0xcb00325 326/*327*Registers for CMU_PERI328*/329#define MUX_SEL_PERI 0x0200330#define MUX_SEL_PERI1 0x0204331#define MUX_ENABLE_PERI 0x0300332#define MUX_ENABLE_PERI1 0x0304333#define MUX_STAT_PERI 0x0400334#define MUX_STAT_PERI1 0x0404335#define MUX_IGNORE_PERI 0x0500336#define MUX_IGNORE_PERI1 0x0504337#define DIV_PERI 0x0600338#define DIV_STAT_PERI 0x0700339#define EN_PCLK_PERI0 0x0800340#define EN_PCLK_PERI1 0x0804341#define EN_PCLK_PERI2 0x0808342#define EN_PCLK_PERI3 0x080c343#define EN_PCLK_PERI_SECURE_CHIPID 0x0810344#define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814345#define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818346#define EN_PCLK_PERI_SECURE_SECKEY 0x081c347#define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820348#define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824349#define EN_PCLK_PERI_SECURE_TZPC 0x0828350#define EN_SCLK_PERI 0x0a00351#define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04352#define EN_IP_PERI0 0x0b00353#define EN_IP_PERI1 0x0b04354#define EN_IP_PERI2 0x0b08355#define EN_IP_PERI_SECURE_CHIPID 0x0b0c356#define EN_IP_PERI_SECURE_PROVKEY0 0x0b10357#define EN_IP_PERI_SECURE_PROVKEY1 0x0b14358#define EN_IP_PERI_SECURE_SECKEY 0x0b18359#define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c360#define EN_IP_PERI_SECURE_TOP_RTC 0x0b20361#define EN_IP_PERI_SECURE_TZPC 0x0b24362 363/*364*Registers for CMU_TOP365*/366#define DISP_PLL_LOCK 0x0000367#define AUD_PLL_LOCK 0x0004368#define DISP_PLL_CON0 0x0100369#define DISP_PLL_CON1 0x0104370#define DISP_PLL_FDET 0x0108371#define AUD_PLL_CON0 0x0110372#define AUD_PLL_CON1 0x0114373#define AUD_PLL_CON2 0x0118374#define AUD_PLL_FDET 0x011c375#define MUX_SEL_TOP_PLL0 0x0200376#define MUX_SEL_TOP_MFC 0x0204377#define MUX_SEL_TOP_G2D 0x0208378#define MUX_SEL_TOP_GSCL 0x020c379#define MUX_SEL_TOP_ISP10 0x0214380#define MUX_SEL_TOP_ISP11 0x0218381#define MUX_SEL_TOP_DISP0 0x021c382#define MUX_SEL_TOP_DISP1 0x0220383#define MUX_SEL_TOP_BUS 0x0224384#define MUX_SEL_TOP_PERI0 0x0228385#define MUX_SEL_TOP_PERI1 0x022c386#define MUX_SEL_TOP_FSYS 0x0230387#define MUX_ENABLE_TOP_PLL0 0x0300388#define MUX_ENABLE_TOP_MFC 0x0304389#define MUX_ENABLE_TOP_G2D 0x0308390#define MUX_ENABLE_TOP_GSCL 0x030c391#define MUX_ENABLE_TOP_ISP10 0x0314392#define MUX_ENABLE_TOP_ISP11 0x0318393#define MUX_ENABLE_TOP_DISP0 0x031c394#define MUX_ENABLE_TOP_DISP1 0x0320395#define MUX_ENABLE_TOP_BUS 0x0324396#define MUX_ENABLE_TOP_PERI0 0x0328397#define MUX_ENABLE_TOP_PERI1 0x032c398#define MUX_ENABLE_TOP_FSYS 0x0330399#define MUX_STAT_TOP_PLL0 0x0400400#define MUX_STAT_TOP_MFC 0x0404401#define MUX_STAT_TOP_G2D 0x0408402#define MUX_STAT_TOP_GSCL 0x040c403#define MUX_STAT_TOP_ISP10 0x0414404#define MUX_STAT_TOP_ISP11 0x0418405#define MUX_STAT_TOP_DISP0 0x041c406#define MUX_STAT_TOP_DISP1 0x0420407#define MUX_STAT_TOP_BUS 0x0424408#define MUX_STAT_TOP_PERI0 0x0428409#define MUX_STAT_TOP_PERI1 0x042c410#define MUX_STAT_TOP_FSYS 0x0430411#define MUX_IGNORE_TOP_PLL0 0x0500412#define MUX_IGNORE_TOP_MFC 0x0504413#define MUX_IGNORE_TOP_G2D 0x0508414#define MUX_IGNORE_TOP_GSCL 0x050c415#define MUX_IGNORE_TOP_ISP10 0x0514416#define MUX_IGNORE_TOP_ISP11 0x0518417#define MUX_IGNORE_TOP_DISP0 0x051c418#define MUX_IGNORE_TOP_DISP1 0x0520419#define MUX_IGNORE_TOP_BUS 0x0524420#define MUX_IGNORE_TOP_PERI0 0x0528421#define MUX_IGNORE_TOP_PERI1 0x052c422#define MUX_IGNORE_TOP_FSYS 0x0530423#define DIV_TOP_G2D_MFC 0x0600424#define DIV_TOP_GSCL_ISP0 0x0604425#define DIV_TOP_ISP10 0x0608426#define DIV_TOP_ISP11 0x060c427#define DIV_TOP_DISP 0x0610428#define DIV_TOP_BUS 0x0614429#define DIV_TOP_PERI0 0x0618430#define DIV_TOP_PERI1 0x061c431#define DIV_TOP_PERI2 0x0620432#define DIV_TOP_FSYS0 0x0624433#define DIV_TOP_FSYS1 0x0628434#define DIV_TOP_HPM 0x062c435#define DIV_TOP_PLL_FDET 0x0630436#define DIV_STAT_TOP_G2D_MFC 0x0700437#define DIV_STAT_TOP_GSCL_ISP0 0x0704438#define DIV_STAT_TOP_ISP10 0x0708439#define DIV_STAT_TOP_ISP11 0x070c440#define DIV_STAT_TOP_DISP 0x0710441#define DIV_STAT_TOP_BUS 0x0714442#define DIV_STAT_TOP_PERI0 0x0718443#define DIV_STAT_TOP_PERI1 0x071c444#define DIV_STAT_TOP_PERI2 0x0720445#define DIV_STAT_TOP_FSYS0 0x0724446#define DIV_STAT_TOP_FSYS1 0x0728447#define DIV_STAT_TOP_HPM 0x072c448#define DIV_STAT_TOP_PLL_FDET 0x0730449#define EN_ACLK_TOP 0x0800450#define EN_SCLK_TOP 0x0a00451#define EN_IP_TOP 0x0b00452#define CLKOUT_CMU_TOP 0x0c00453#define CLKOUT_CMU_TOP_DIV_STAT 0x0c04454 455#endif /*__CLK_EXYNOS5260_H */456 457