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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.4 * Copyright (c) 2013 Linaro Ltd.5 *6 * Common Clock Framework support for all PLL's in Samsung platforms7*/8 9#ifndef __SAMSUNG_CLK_PLL_H10#define __SAMSUNG_CLK_PLL_H11 12enum samsung_pll_type {13	pll_2126,14	pll_3000,15	pll_35xx,16	pll_36xx,17	pll_2550,18	pll_2650,19	pll_4500,20	pll_4502,21	pll_4508,22	pll_4600,23	pll_4650,24	pll_4650c,25	pll_6552,26	pll_6552_s3c2416,27	pll_6553,28	pll_2550x,29	pll_2550xx,30	pll_2650x,31	pll_2650xx,32	pll_1417x,33	pll_1418x,34	pll_1450x,35	pll_1451x,36	pll_1452x,37	pll_1460x,38	pll_0818x,39	pll_0822x,40	pll_0831x,41	pll_142xx,42	pll_0516x,43	pll_0517x,44	pll_0518x,45	pll_531x,46};47 48#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \49	((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))50#define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \51	BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))52 53#define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)			\54	{							\55		.rate	=	PLL_VALID_RATE(_fin, _rate,	\56				_m, _p, _s, 0, 16),		\57		.mdiv	=	(_m),				\58		.pdiv	=	(_p),				\59		.sdiv	=	(_s),				\60	}61 62#define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)		\63	{							\64		.rate	=	PLL_VALID_RATE(_fin, _rate,	\65				_m, _p, _s, _k, 16),		\66		.mdiv	=	(_m),				\67		.pdiv	=	(_p),				\68		.sdiv	=	(_s),				\69		.kdiv	=	(_k),				\70	}71 72#define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)		\73	{							\74		.rate	=	PLL_VALID_RATE(_fin, _rate,	\75				_m, _p, _s - 1, 0, 16),		\76		.mdiv	=	(_m),				\77		.pdiv	=	(_p),				\78		.sdiv	=	(_s),				\79		.afc	=	(_afc),				\80	}81 82#define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)	\83	{							\84		.rate	=	PLL_VALID_RATE(_fin, _rate,	\85				_m, _p, _s, _k, 16),		\86		.mdiv	=	(_m),				\87		.pdiv	=	(_p),				\88		.sdiv	=	(_s),				\89		.kdiv	=	(_k),				\90		.vsel	=	(_vsel),			\91	}92 93#define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \94	{							\95		.rate	=	PLL_VALID_RATE(_fin, _rate,	\96				_m, _p, _s, _k, 10),		\97		.mdiv	=	(_m),				\98		.pdiv	=	(_p),				\99		.sdiv	=	(_s),				\100		.kdiv	=	(_k),				\101		.mfr	=	(_mfr),				\102		.mrr	=	(_mrr),				\103		.vsel	=	(_vsel),			\104	}105 106/* NOTE: Rate table should be kept sorted in descending order. */107 108struct samsung_pll_rate_table {109	unsigned int rate;110	unsigned int pdiv;111	unsigned int mdiv;112	unsigned int sdiv;113	unsigned int kdiv;114	unsigned int afc;115	unsigned int mfr;116	unsigned int mrr;117	unsigned int vsel;118};119 120#endif /* __SAMSUNG_CLK_PLL_H */121