124 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright 2011-2012 Calxeda, Inc.4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>5 *6 * Based from clk-highbank.c7 */8#include <linux/slab.h>9#include <linux/clk-provider.h>10#include <linux/io.h>11#include <linux/of.h>12 13#include "clk.h"14 15#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)16 17static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,18 unsigned long parent_rate)19{20 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);21 u32 div, val;22 23 if (socfpgaclk->fixed_div) {24 div = socfpgaclk->fixed_div;25 } else {26 if (socfpgaclk->div_reg) {27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;28 val &= GENMASK(socfpgaclk->width - 1, 0);29 parent_rate /= (val + 1);30 }31 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);32 }33 34 return parent_rate / div;35}36 37static u8 clk_periclk_get_parent(struct clk_hw *hwclk)38{39 u32 clk_src;40 41 clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);42 return clk_src & 0x1;43}44 45static const struct clk_ops periclk_ops = {46 .recalc_rate = clk_periclk_recalc_rate,47 .get_parent = clk_periclk_get_parent,48};49 50static void __init __socfpga_periph_init(struct device_node *node,51 const struct clk_ops *ops)52{53 u32 reg;54 struct clk_hw *hw_clk;55 struct socfpga_periph_clk *periph_clk;56 const char *clk_name = node->name;57 const char *parent_name[SOCFPGA_MAX_PARENTS];58 struct clk_init_data init;59 int rc;60 u32 fixed_div;61 u32 div_reg[3];62 63 of_property_read_u32(node, "reg", ®);64 65 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);66 if (WARN_ON(!periph_clk))67 return;68 69 periph_clk->hw.reg = clk_mgr_base_addr + reg;70 71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);72 if (!rc) {73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];74 periph_clk->shift = div_reg[1];75 periph_clk->width = div_reg[2];76 } else {77 periph_clk->div_reg = NULL;78 }79 80 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);81 if (rc)82 periph_clk->fixed_div = 0;83 else84 periph_clk->fixed_div = fixed_div;85 86 of_property_read_string(node, "clock-output-names", &clk_name);87 88 init.name = clk_name;89 init.ops = ops;90 init.flags = 0;91 92 init.num_parents = of_clk_parent_fill(node, parent_name,93 SOCFPGA_MAX_PARENTS);94 init.parent_names = parent_name;95 96 periph_clk->hw.hw.init = &init;97 hw_clk = &periph_clk->hw.hw;98 99 rc = clk_hw_register(NULL, hw_clk);100 if (rc) {101 pr_err("Could not register clock:%s\n", clk_name);102 goto err_clk_hw_register;103 }104 105 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk);106 if (rc) {107 pr_err("Could not register clock provider for node:%s\n",108 clk_name);109 goto err_of_clk_add_hw_provider;110 }111 112 return;113 114err_of_clk_add_hw_provider:115 clk_hw_unregister(hw_clk);116err_clk_hw_register:117 kfree(periph_clk);118}119 120void __init socfpga_periph_init(struct device_node *node)121{122 __socfpga_periph_init(node, &periclk_ops);123}124