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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>4 *5 * based on drivers/clk/tegra/clk.h6 */7 8#ifndef __SOCFPGA_CLK_H9#define __SOCFPGA_CLK_H10 11#include <linux/clk-provider.h>12 13/* Clock Manager offsets */14#define CLKMGR_CTRL 0x015#define CLKMGR_BYPASS 0x416#define CLKMGR_DBCTRL 0x1017#define CLKMGR_L4SRC 0x7018#define CLKMGR_PERPLL_SRC 0xAC19 20#define SOCFPGA_MAX_PARENTS 521 22#define streq(a, b) (strcmp((a), (b)) == 0)23#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))25 26#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))28 29extern void __iomem *clk_mgr_base_addr;30extern void __iomem *clk_mgr_a10_base_addr;31 32void __init socfpga_pll_init(struct device_node *node);33void __init socfpga_periph_init(struct device_node *node);34void __init socfpga_gate_init(struct device_node *node);35void socfpga_a10_pll_init(struct device_node *node);36void socfpga_a10_periph_init(struct device_node *node);37void socfpga_a10_gate_init(struct device_node *node);38 39struct socfpga_pll {40 struct clk_gate hw;41};42 43struct socfpga_gate_clk {44 struct clk_gate hw;45 char *parent_name;46 u32 fixed_div;47 void __iomem *div_reg;48 void __iomem *bypass_reg;49 struct regmap *sys_mgr_base_addr;50 u32 width; /* only valid if div_reg != 0 */51 u32 shift; /* only valid if div_reg != 0 */52 u32 bypass_shift; /* only valid if bypass_reg != 0 */53};54 55struct socfpga_periph_clk {56 struct clk_gate hw;57 char *parent_name;58 u32 fixed_div;59 void __iomem *div_reg;60 void __iomem *bypass_reg;61 u32 width; /* only valid if div_reg != 0 */62 u32 shift; /* only valid if div_reg != 0 */63 u32 bypass_shift; /* only valid if bypass_reg != 0 */64};65 66#endif /* SOCFPGA_CLK_H */67