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1# SPDX-License-Identifier: GPL-2.02# common clock support for SOPHGO SoC family.3 4config CLK_SOPHGO_CV18005 tristate "Support for the Sophgo CV1800 series SoCs clock controller"6 depends on ARCH_SOPHGO || COMPILE_TEST7 help8 This driver supports clock controller of Sophgo CV18XX series SoC.9 The driver require a 25MHz Oscillator to function generate clock.10 It includes PLLs, common clock function and some vendor clock for11 IPs of CV18XX series SoC12 13config CLK_SOPHGO_SG2042_PLL14 tristate "Sophgo SG2042 PLL clock support"15 depends on ARCH_SOPHGO || COMPILE_TEST16 help17 This driver supports the PLL clock controller on the18 Sophgo SG2042 SoC. This clock IP uses three oscillators with19 frequency of 25 MHz as input, which are used for Main/Fixed20 PLL, DDR PLL 0 and DDR PLL 1 respectively.21 22config CLK_SOPHGO_SG2042_CLKGEN23 tristate "Sophgo SG2042 Clock Generator support"24 depends on CLK_SOPHGO_SG2042_PLL25 help26 This driver supports the Clock Generator on the27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock28 because it uses PLL clocks as input.29 This driver provides clock function such as DIV/Mux/Gate.30 31config CLK_SOPHGO_SG2042_RPGATE32 tristate "Sophgo SG2042 RP subsystem clock controller support"33 depends on CLK_SOPHGO_SG2042_CLKGEN34 help35 This driver supports the RP((Riscv Processors)) subsystem clock36 controller on the Sophgo SG2042 SoC.37 This clock IP depends on SG2042 Clock Generator because it uses38 clock from Clock Generator IP as input.39 This driver provides Gate function for RP.40