124 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>4 */5 6#ifndef _CLK_SOPHGO_CV1800_H_7#define _CLK_SOPHGO_CV1800_H_8 9#include <dt-bindings/clock/sophgo,cv1800.h>10 11#define CV1800_CLK_MAX (CLK_XTAL_AP + 1)12#define CV1810_CLK_MAX (CLK_DISP_SRC_VIP + 1)13 14#define REG_PLL_G2_CTRL 0x80015#define REG_PLL_G2_STATUS 0x80416#define REG_MIPIMPLL_CSR 0x80817#define REG_A0PLL_CSR 0x80C18#define REG_DISPPLL_CSR 0x81019#define REG_CAM0PLL_CSR 0x81420#define REG_CAM1PLL_CSR 0x81821#define REG_PLL_G2_SSC_SYN_CTRL 0x84022#define REG_A0PLL_SSC_SYN_CTRL 0x85023#define REG_A0PLL_SSC_SYN_SET 0x85424#define REG_A0PLL_SSC_SYN_SPAN 0x85825#define REG_A0PLL_SSC_SYN_STEP 0x85C26#define REG_DISPPLL_SSC_SYN_CTRL 0x86027#define REG_DISPPLL_SSC_SYN_SET 0x86428#define REG_DISPPLL_SSC_SYN_SPAN 0x86829#define REG_DISPPLL_SSC_SYN_STEP 0x86C30#define REG_CAM0PLL_SSC_SYN_CTRL 0x87031#define REG_CAM0PLL_SSC_SYN_SET 0x87432#define REG_CAM0PLL_SSC_SYN_SPAN 0x87833#define REG_CAM0PLL_SSC_SYN_STEP 0x87C34#define REG_CAM1PLL_SSC_SYN_CTRL 0x88035#define REG_CAM1PLL_SSC_SYN_SET 0x88436#define REG_CAM1PLL_SSC_SYN_SPAN 0x88837#define REG_CAM1PLL_SSC_SYN_STEP 0x88C38#define REG_APLL_FRAC_DIV_CTRL 0x89039#define REG_APLL_FRAC_DIV_M 0x89440#define REG_APLL_FRAC_DIV_N 0x89841#define REG_MIPIMPLL_CLK_CSR 0x8A042#define REG_A0PLL_CLK_CSR 0x8A443#define REG_DISPPLL_CLK_CSR 0x8A844#define REG_CAM0PLL_CLK_CSR 0x8AC45#define REG_CAM1PLL_CLK_CSR 0x8B046#define REG_CLK_CAM0_SRC_DIV 0x8C047#define REG_CLK_CAM1_SRC_DIV 0x8C448 49/* top_pll_g6 */50#define REG_PLL_G6_CTRL 0x90051#define REG_PLL_G6_STATUS 0x90452#define REG_MPLL_CSR 0x90853#define REG_TPLL_CSR 0x90C54#define REG_FPLL_CSR 0x91055#define REG_PLL_G6_SSC_SYN_CTRL 0x94056#define REG_DPLL_SSC_SYN_CTRL 0x95057#define REG_DPLL_SSC_SYN_SET 0x95458#define REG_DPLL_SSC_SYN_SPAN 0x95859#define REG_DPLL_SSC_SYN_STEP 0x95C60#define REG_MPLL_SSC_SYN_CTRL 0x96061#define REG_MPLL_SSC_SYN_SET 0x96462#define REG_MPLL_SSC_SYN_SPAN 0x96863#define REG_MPLL_SSC_SYN_STEP 0x96C64#define REG_TPLL_SSC_SYN_CTRL 0x97065#define REG_TPLL_SSC_SYN_SET 0x97466#define REG_TPLL_SSC_SYN_SPAN 0x97867#define REG_TPLL_SSC_SYN_STEP 0x97C68 69/* clkgen */70#define REG_CLK_EN_0 0x00071#define REG_CLK_EN_1 0x00472#define REG_CLK_EN_2 0x00873#define REG_CLK_EN_3 0x00C74#define REG_CLK_EN_4 0x01075#define REG_CLK_SEL_0 0x02076#define REG_CLK_BYP_0 0x03077#define REG_CLK_BYP_1 0x03478 79#define REG_DIV_CLK_A53_0 0x04080#define REG_DIV_CLK_A53_1 0x04481#define REG_DIV_CLK_CPU_AXI0 0x04882#define REG_DIV_CLK_CPU_GIC 0x05083#define REG_DIV_CLK_TPU 0x05484#define REG_DIV_CLK_EMMC 0x06485#define REG_DIV_CLK_EMMC_100K 0x06C86#define REG_DIV_CLK_SD0 0x07087#define REG_DIV_CLK_SD0_100K 0x07888#define REG_DIV_CLK_SD1 0x07C89#define REG_DIV_CLK_SD1_100K 0x08490#define REG_DIV_CLK_SPI_NAND 0x08891#define REG_DIV_CLK_ETH0_500M 0x08C92#define REG_DIV_CLK_ETH1_500M 0x09093#define REG_DIV_CLK_GPIO_DB 0x09494#define REG_DIV_CLK_SDMA_AUD0 0x09895#define REG_DIV_CLK_SDMA_AUD1 0x09C96#define REG_DIV_CLK_SDMA_AUD2 0x0A097#define REG_DIV_CLK_SDMA_AUD3 0x0A498#define REG_DIV_CLK_CAM0_200 0x0A899#define REG_DIV_CLK_AXI4 0x0B8100#define REG_DIV_CLK_AXI6 0x0BC101#define REG_DIV_CLK_DSI_ESC 0x0C4102#define REG_DIV_CLK_AXI_VIP 0x0C8103#define REG_DIV_CLK_SRC_VIP_SYS_0 0x0D0104#define REG_DIV_CLK_SRC_VIP_SYS_1 0x0D8105#define REG_DIV_CLK_DISP_SRC_VIP 0x0E0106#define REG_DIV_CLK_AXI_VIDEO_CODEC 0x0E4107#define REG_DIV_CLK_VC_SRC0 0x0EC108#define REG_DIV_CLK_1M 0x0FC109#define REG_DIV_CLK_SPI 0x100110#define REG_DIV_CLK_I2C 0x104111#define REG_DIV_CLK_SRC_VIP_SYS_2 0x110112#define REG_DIV_CLK_AUDSRC 0x118113#define REG_DIV_CLK_PWM_SRC_0 0x120114#define REG_DIV_CLK_AP_DEBUG 0x128115#define REG_DIV_CLK_RTCSYS_SRC_0 0x12C116#define REG_DIV_CLK_C906_0_0 0x130117#define REG_DIV_CLK_C906_0_1 0x134118#define REG_DIV_CLK_C906_1_0 0x138119#define REG_DIV_CLK_C906_1_1 0x13C120#define REG_DIV_CLK_SRC_VIP_SYS_3 0x140121#define REG_DIV_CLK_SRC_VIP_SYS_4 0x144122 123#endif /* _CLK_SOPHGO_CV1800_H_ */124