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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>4 */5 6#ifndef _CLK_SOPHGO_CV18XX_IP_H_7#define _CLK_SOPHGO_CV18XX_IP_H_8 9#include <linux/compiler.h>10#include <linux/clk-provider.h>11#include <linux/bitfield.h>12 13struct cv1800_clk_common {14	void __iomem	*base;15	spinlock_t	*lock;16	struct clk_hw	hw;17	unsigned long	features;18};19 20#define CV1800_CLK_COMMON(_name, _parents, _op, _flags)			\21	{								\22		.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents,	\23						    _op, _flags),	\24	}25 26static inline struct cv1800_clk_common *27hw_to_cv1800_clk_common(struct clk_hw *hw)28{29	return container_of(hw, struct cv1800_clk_common, hw);30}31 32struct cv1800_clk_regbit {33	u16		reg;34	s8		shift;35};36 37struct cv1800_clk_regfield {38	u16		reg;39	u8		shift;40	u8		width;41	s16		initval;42	unsigned long	flags;43};44 45#define CV1800_CLK_BIT(_reg, _shift)	\46	{				\47		.reg = _reg,		\48		.shift = _shift,	\49	}50 51#define CV1800_CLK_REG(_reg, _shift, _width, _initval, _flags)	\52	{							\53		.reg = _reg,					\54		.shift = _shift,				\55		.width = _width,				\56		.initval = _initval,				\57		.flags = _flags,				\58	}59 60#define cv1800_clk_regfield_genmask(_reg) \61	GENMASK((_reg)->shift + (_reg)->width - 1, (_reg)->shift)62#define cv1800_clk_regfield_get(_val, _reg) \63	(((_val) >> (_reg)->shift) & GENMASK((_reg)->width - 1, 0))64#define cv1800_clk_regfield_set(_val, _new, _reg)    \65	(((_val) & ~cv1800_clk_regfield_genmask((_reg))) | \66	 (((_new) & GENMASK((_reg)->width - 1, 0)) << (_reg)->shift))67 68#define _CV1800_SET_FIELD(_reg, _val, _field) \69	(((_reg) & ~(_field)) | FIELD_PREP((_field), (_val)))70 71int cv1800_clk_setbit(struct cv1800_clk_common *common,72		      struct cv1800_clk_regbit *field);73int cv1800_clk_clearbit(struct cv1800_clk_common *common,74			struct cv1800_clk_regbit *field);75int cv1800_clk_checkbit(struct cv1800_clk_common *common,76			struct cv1800_clk_regbit *field);77 78void cv1800_clk_wait_for_lock(struct cv1800_clk_common *common,79			      u32 reg, u32 lock);80 81#endif // _CLK_SOPHGO_CV18XX_IP_H_82