1806 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Unisoc SC9863A clock driver4 *5 * Copyright (C) 2019 Unisoc, Inc.6 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>7 */8 9#include <linux/clk-provider.h>10#include <linux/err.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/platform_device.h>14#include <linux/slab.h>15 16#include <dt-bindings/clock/sprd,sc9863a-clk.h>17 18#include "common.h"19#include "composite.h"20#include "div.h"21#include "gate.h"22#include "mux.h"23#include "pll.h"24 25/* mpll*_gate clocks control cpu cores, they were enabled by default */26static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,27 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);28static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,29 0x1000, BIT(0), 0, 0, 240);30static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,31 0x1000, BIT(0), 0, 0, 240);32static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,33 0x1000, BIT(0), 0, 0, 240);34static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,35 0x1000, BIT(0), 0, 0, 240);36static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,37 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);38static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,39 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);40static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",41 0x1e8, 0x1000, BIT(0), 0, 0, 240);42 43static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {44 /* address base is 0x402b0000 */45 &mpll0_gate.common,46 &dpll0_gate.common,47 &lpll_gate.common,48 &gpll_gate.common,49 &dpll1_gate.common,50 &mpll1_gate.common,51 &mpll2_gate.common,52 &isppll_gate.common,53};54 55static struct clk_hw_onecell_data sc9863a_pmu_gate_hws = {56 .hws = {57 [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,58 [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,59 [CLK_LPLL_GATE] = &lpll_gate.common.hw,60 [CLK_GPLL_GATE] = &gpll_gate.common.hw,61 [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,62 [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,63 [CLK_MPLL2_GATE] = &mpll2_gate.common.hw,64 [CLK_ISPPLL_GATE] = &isppll_gate.common.hw,65 },66 .num = CLK_PMU_APB_NUM,67};68 69static const struct sprd_clk_desc sc9863a_pmu_gate_desc = {70 .clk_clks = sc9863a_pmu_gate_clks,71 .num_clk_clks = ARRAY_SIZE(sc9863a_pmu_gate_clks),72 .hw_clks = &sc9863a_pmu_gate_hws,73};74 75static const u64 itable[5] = {4, 1000000000, 1200000000,76 1400000000, 1600000000};77 78static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = {79 { .shift = 95, .width = 1 }, /* lock_done */80 { .shift = 0, .width = 1 }, /* div_s */81 { .shift = 1, .width = 1 }, /* mod_en */82 { .shift = 2, .width = 1 }, /* sdm_en */83 { .shift = 0, .width = 0 }, /* refin */84 { .shift = 3, .width = 3 }, /* ibias */85 { .shift = 8, .width = 11 }, /* n */86 { .shift = 55, .width = 7 }, /* nint */87 { .shift = 32, .width = 23}, /* kint */88 { .shift = 0, .width = 0 }, /* prediv */89 { .shift = 0, .width = 0 }, /* postdiv */90};91static SPRD_PLL_FW_NAME(twpll, "twpll", "ext-26m", 0x4, 3, itable,92 f_twpll, 240, 1000, 1000, 0, 0);93static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw, 2, 1, 0);94static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw, 4, 1, 0);95static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw, 8, 1, 0);96static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw, 16, 1, 0);97static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw, 32, 1, 0);98static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw, 64, 1, 0);99static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw, 128, 1, 0);100static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw, 3, 1, 0);101static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw, 6, 1, 0);102static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw, 12, 1, 0);103static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw, 24, 1, 0);104static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw, 5, 1, 0);105static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw, 7, 1, 0);106static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw, 9, 1, 0);107static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw, 10, 1, 0);108static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw, 20, 1, 0);109static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw, 30, 1, 0);110static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw, 40, 1, 0);111static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw, 80, 1, 0);112 113static const struct clk_bit_field f_lpll[PLL_FACT_MAX] = {114 { .shift = 95, .width = 1 }, /* lock_done */115 { .shift = 0, .width = 1 }, /* div_s */116 { .shift = 1, .width = 1 }, /* mod_en */117 { .shift = 2, .width = 1 }, /* sdm_en */118 { .shift = 0, .width = 0 }, /* refin */119 { .shift = 6, .width = 2 }, /* ibias */120 { .shift = 8, .width = 11 }, /* n */121 { .shift = 55, .width = 7 }, /* nint */122 { .shift = 32, .width = 23}, /* kint */123 { .shift = 0, .width = 0 }, /* prediv */124 { .shift = 0, .width = 0 }, /* postdiv */125};126static SPRD_PLL_HW(lpll, "lpll", &lpll_gate.common.hw, 0x20, 3, itable,127 f_lpll, 240, 1000, 1000, 0, 0);128static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw, 3, 1, 0);129static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw, 5, 1, 0);130 131static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = {132 { .shift = 95, .width = 1 }, /* lock_done */133 { .shift = 0, .width = 1 }, /* div_s */134 { .shift = 1, .width = 1 }, /* mod_en */135 { .shift = 2, .width = 1 }, /* sdm_en */136 { .shift = 0, .width = 0 }, /* refin */137 { .shift = 6, .width = 2 }, /* ibias */138 { .shift = 8, .width = 11 }, /* n */139 { .shift = 55, .width = 7 }, /* nint */140 { .shift = 32, .width = 23}, /* kint */141 { .shift = 0, .width = 0 }, /* prediv */142 { .shift = 80, .width = 1 }, /* postdiv */143};144static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x38, 3, itable,145 f_gpll, 240, 1000, 1000, 1, 400000000);146 147static SPRD_PLL_HW(isppll, "isppll", &isppll_gate.common.hw, 0x50, 3, itable,148 f_gpll, 240, 1000, 1000, 0, 0);149static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw, 2, 1, 0);150 151static struct sprd_clk_common *sc9863a_pll_clks[] = {152 /* address base is 0x40353000 */153 &twpll.common,154 &lpll.common,155 &gpll.common,156 &isppll.common,157};158 159static struct clk_hw_onecell_data sc9863a_pll_hws = {160 .hws = {161 [CLK_TWPLL] = &twpll.common.hw,162 [CLK_TWPLL_768M] = &twpll_768m.hw,163 [CLK_TWPLL_384M] = &twpll_384m.hw,164 [CLK_TWPLL_192M] = &twpll_192m.hw,165 [CLK_TWPLL_96M] = &twpll_96m.hw,166 [CLK_TWPLL_48M] = &twpll_48m.hw,167 [CLK_TWPLL_24M] = &twpll_24m.hw,168 [CLK_TWPLL_12M] = &twpll_12m.hw,169 [CLK_TWPLL_512M] = &twpll_512m.hw,170 [CLK_TWPLL_256M] = &twpll_256m.hw,171 [CLK_TWPLL_128M] = &twpll_128m.hw,172 [CLK_TWPLL_64M] = &twpll_64m.hw,173 [CLK_TWPLL_307M2] = &twpll_307m2.hw,174 [CLK_TWPLL_219M4] = &twpll_219m4.hw,175 [CLK_TWPLL_170M6] = &twpll_170m6.hw,176 [CLK_TWPLL_153M6] = &twpll_153m6.hw,177 [CLK_TWPLL_76M8] = &twpll_76m8.hw,178 [CLK_TWPLL_51M2] = &twpll_51m2.hw,179 [CLK_TWPLL_38M4] = &twpll_38m4.hw,180 [CLK_TWPLL_19M2] = &twpll_19m2.hw,181 [CLK_LPLL] = &lpll.common.hw,182 [CLK_LPLL_409M6] = &lpll_409m6.hw,183 [CLK_LPLL_245M76] = &lpll_245m76.hw,184 [CLK_GPLL] = &gpll.common.hw,185 [CLK_ISPPLL] = &isppll.common.hw,186 [CLK_ISPPLL_468M] = &isppll_468m.hw,187 188 },189 .num = CLK_ANLG_PHY_G1_NUM,190};191 192static const struct sprd_clk_desc sc9863a_pll_desc = {193 .clk_clks = sc9863a_pll_clks,194 .num_clk_clks = ARRAY_SIZE(sc9863a_pll_clks),195 .hw_clks = &sc9863a_pll_hws,196};197 198static const u64 itable_mpll[6] = {5, 1000000000, 1200000000, 1400000000,199 1600000000, 1800000000};200static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x0, 3, itable_mpll,201 f_gpll, 240, 1000, 1000, 1, 1000000000);202static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x18, 3, itable_mpll,203 f_gpll, 240, 1000, 1000, 1, 1000000000);204static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x30, 3, itable_mpll,205 f_gpll, 240, 1000, 1000, 1, 1000000000);206static CLK_FIXED_FACTOR_HW(mpll2_675m, "mpll2-675m", &mpll2.common.hw, 2, 1, 0);207 208static struct sprd_clk_common *sc9863a_mpll_clks[] = {209 /* address base is 0x40359000 */210 &mpll0.common,211 &mpll1.common,212 &mpll2.common,213};214 215static struct clk_hw_onecell_data sc9863a_mpll_hws = {216 .hws = {217 [CLK_MPLL0] = &mpll0.common.hw,218 [CLK_MPLL1] = &mpll1.common.hw,219 [CLK_MPLL2] = &mpll2.common.hw,220 [CLK_MPLL2_675M] = &mpll2_675m.hw,221 222 },223 .num = CLK_ANLG_PHY_G4_NUM,224};225 226static const struct sprd_clk_desc sc9863a_mpll_desc = {227 .clk_clks = sc9863a_mpll_clks,228 .num_clk_clks = ARRAY_SIZE(sc9863a_mpll_clks),229 .hw_clks = &sc9863a_mpll_hws,230};231 232static SPRD_SC_GATE_CLK_FW_NAME(audio_gate, "audio-gate", "ext-26m",233 0x4, 0x1000, BIT(8), 0, 0);234 235static SPRD_PLL_FW_NAME(rpll, "rpll", "ext-26m", 0x10,236 3, itable, f_lpll, 240, 1000, 1000, 0, 0);237 238static CLK_FIXED_FACTOR_HW(rpll_390m, "rpll-390m", &rpll.common.hw, 2, 1, 0);239static CLK_FIXED_FACTOR_HW(rpll_260m, "rpll-260m", &rpll.common.hw, 3, 1, 0);240static CLK_FIXED_FACTOR_HW(rpll_195m, "rpll-195m", &rpll.common.hw, 4, 1, 0);241static CLK_FIXED_FACTOR_HW(rpll_26m, "rpll-26m", &rpll.common.hw, 30, 1, 0);242 243static struct sprd_clk_common *sc9863a_rpll_clks[] = {244 /* address base is 0x4035c000 */245 &audio_gate.common,246 &rpll.common,247};248 249static struct clk_hw_onecell_data sc9863a_rpll_hws = {250 .hws = {251 [CLK_AUDIO_GATE] = &audio_gate.common.hw,252 [CLK_RPLL] = &rpll.common.hw,253 [CLK_RPLL_390M] = &rpll_390m.hw,254 [CLK_RPLL_260M] = &rpll_260m.hw,255 [CLK_RPLL_195M] = &rpll_195m.hw,256 [CLK_RPLL_26M] = &rpll_26m.hw,257 },258 .num = CLK_ANLG_PHY_G5_NUM,259};260 261static const struct sprd_clk_desc sc9863a_rpll_desc = {262 .clk_clks = sc9863a_rpll_clks,263 .num_clk_clks = ARRAY_SIZE(sc9863a_rpll_clks),264 .hw_clks = &sc9863a_rpll_hws,265};266 267static const u64 itable_dpll[5] = {4, 1211000000, 1320000000, 1570000000,268 1866000000};269static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x0, 3, itable_dpll,270 f_lpll, 240, 1000, 1000, 0, 0);271static SPRD_PLL_HW(dpll1, "dpll1", &dpll1_gate.common.hw, 0x18, 3, itable_dpll,272 f_lpll, 240, 1000, 1000, 0, 0);273 274static CLK_FIXED_FACTOR_HW(dpll0_933m, "dpll0-933m", &dpll0.common.hw, 2, 1, 0);275static CLK_FIXED_FACTOR_HW(dpll0_622m3, "dpll0-622m3", &dpll0.common.hw, 3, 1, 0);276static CLK_FIXED_FACTOR_HW(dpll1_400m, "dpll1-400m", &dpll0.common.hw, 4, 1, 0);277static CLK_FIXED_FACTOR_HW(dpll1_266m7, "dpll1-266m7", &dpll0.common.hw, 6, 1, 0);278static CLK_FIXED_FACTOR_HW(dpll1_123m1, "dpll1-123m1", &dpll0.common.hw, 13, 1, 0);279static CLK_FIXED_FACTOR_HW(dpll1_50m, "dpll1-50m", &dpll0.common.hw, 32, 1, 0);280 281static struct sprd_clk_common *sc9863a_dpll_clks[] = {282 /* address base is 0x40363000 */283 &dpll0.common,284 &dpll1.common,285};286 287static struct clk_hw_onecell_data sc9863a_dpll_hws = {288 .hws = {289 [CLK_DPLL0] = &dpll0.common.hw,290 [CLK_DPLL1] = &dpll1.common.hw,291 [CLK_DPLL0_933M] = &dpll0_933m.hw,292 [CLK_DPLL0_622M3] = &dpll0_622m3.hw,293 [CLK_DPLL0_400M] = &dpll1_400m.hw,294 [CLK_DPLL0_266M7] = &dpll1_266m7.hw,295 [CLK_DPLL0_123M1] = &dpll1_123m1.hw,296 [CLK_DPLL0_50M] = &dpll1_50m.hw,297 298 },299 .num = CLK_ANLG_PHY_G7_NUM,300};301 302static const struct sprd_clk_desc sc9863a_dpll_desc = {303 .clk_clks = sc9863a_dpll_clks,304 .num_clk_clks = ARRAY_SIZE(sc9863a_dpll_clks),305 .hw_clks = &sc9863a_dpll_hws,306};307 308static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0);309static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0);310static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0);311static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0);312static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0);313static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0);314static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0);315 316#define SC9863A_MUX_FLAG \317 (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)318 319static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0);320static const struct clk_parent_data emc_clk_parents[] = {321 { .fw_name = "ext-26m" },322 { .hw = &twpll_384m.hw },323 { .hw = &twpll_512m.hw },324 { .hw = &twpll_768m.hw },325 { .hw = &twpll.common.hw },326};327static SPRD_MUX_CLK_DATA(emc_clk, "emc-clk", emc_clk_parents, 0x220,328 0, 3, SC9863A_MUX_FLAG);329 330static const struct clk_parent_data aon_apb_parents[] = {331 { .hw = &rco_4m.hw },332 { .hw = &rco_25m.hw },333 { .fw_name = "ext-26m" },334 { .hw = &twpll_96m.hw },335 { .fw_name = "rco-100m" },336 { .hw = &twpll_128m.hw },337};338static SPRD_COMP_CLK_DATA(aon_apb, "aon-apb", aon_apb_parents, 0x224,339 0, 3, 8, 2, 0);340 341static const struct clk_parent_data adi_parents[] = {342 { .hw = &rco_4m.hw },343 { .hw = &rco_25m.hw },344 { .fw_name = "ext-26m" },345 { .hw = &twpll_38m4.hw },346 { .hw = &twpll_51m2.hw },347};348static SPRD_MUX_CLK_DATA(adi_clk, "adi-clk", adi_parents, 0x228,349 0, 3, SC9863A_MUX_FLAG);350 351static const struct clk_parent_data aux_parents[] = {352 { .fw_name = "ext-32k" },353 { .hw = &rpll_26m.hw },354 { .fw_name = "ext-26m" },355};356static SPRD_COMP_CLK_DATA(aux0_clk, "aux0-clk", aux_parents, 0x22c,357 0, 5, 8, 4, 0);358static SPRD_COMP_CLK_DATA(aux1_clk, "aux1-clk", aux_parents, 0x230,359 0, 5, 8, 4, 0);360static SPRD_COMP_CLK_DATA(aux2_clk, "aux2-clk", aux_parents, 0x234,361 0, 5, 8, 4, 0);362static SPRD_COMP_CLK_DATA(probe_clk, "probe-clk", aux_parents, 0x238,363 0, 5, 8, 4, 0);364 365static const struct clk_parent_data pwm_parents[] = {366 { .fw_name = "ext-32k" },367 { .hw = &rpll_26m.hw },368 { .fw_name = "ext-26m" },369 { .hw = &twpll_48m.hw },370};371static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c,372 0, 2, SC9863A_MUX_FLAG);373static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x240,374 0, 2, SC9863A_MUX_FLAG);375static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x244,376 0, 2, SC9863A_MUX_FLAG);377 378static const struct clk_parent_data aon_thm_parents[] = {379 { .fw_name = "ext-32k" },380 { .hw = &clk_250k.hw },381};382static SPRD_MUX_CLK_DATA(aon_thm_clk, "aon-thm-clk", aon_thm_parents, 0x25c,383 0, 1, SC9863A_MUX_FLAG);384 385static const struct clk_parent_data audif_parents[] = {386 { .fw_name = "ext-26m" },387 { .hw = &twpll_38m4.hw },388 { .hw = &twpll_51m2.hw },389};390static SPRD_MUX_CLK_DATA(audif_clk, "audif-clk", audif_parents, 0x264,391 0, 2, SC9863A_MUX_FLAG);392 393static const struct clk_parent_data cpu_dap_parents[] = {394 { .hw = &rco_4m.hw },395 { .hw = &rco_25m.hw },396 { .fw_name = "ext-26m" },397 { .hw = &twpll_76m8.hw },398 { .fw_name = "rco-100m" },399 { .hw = &twpll_128m.hw },400 { .hw = &twpll_153m6.hw },401};402static SPRD_MUX_CLK_DATA(cpu_dap_clk, "cpu-dap-clk", cpu_dap_parents, 0x26c,403 0, 3, SC9863A_MUX_FLAG);404 405static const struct clk_parent_data cpu_ts_parents[] = {406 { .fw_name = "ext-32k" },407 { .fw_name = "ext-26m" },408 { .hw = &twpll_128m.hw },409 { .hw = &twpll_153m6.hw },410};411static SPRD_MUX_CLK_DATA(cpu_ts_clk, "cpu-ts-clk", cpu_ts_parents, 0x274,412 0, 2, SC9863A_MUX_FLAG);413 414static const struct clk_parent_data djtag_tck_parents[] = {415 { .hw = &rco_4m.hw },416 { .fw_name = "ext-26m" },417};418static SPRD_MUX_CLK_DATA(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents, 0x28c,419 0, 1, SC9863A_MUX_FLAG);420 421static const struct clk_parent_data emc_ref_parents[] = {422 { .hw = &clk_6m5.hw },423 { .hw = &clk_13m.hw },424 { .fw_name = "ext-26m" },425};426static SPRD_MUX_CLK_DATA(emc_ref_clk, "emc-ref-clk", emc_ref_parents, 0x29c,427 0, 2, SC9863A_MUX_FLAG);428 429static const struct clk_parent_data cssys_parents[] = {430 { .hw = &rco_4m.hw },431 { .fw_name = "ext-26m" },432 { .hw = &twpll_96m.hw },433 { .fw_name = "rco-100m" },434 { .hw = &twpll_128m.hw },435 { .hw = &twpll_153m6.hw },436 { .hw = &twpll_384m.hw },437 { .hw = &twpll_512m.hw },438 { .hw = &mpll2_675m.hw },439};440static SPRD_COMP_CLK_DATA(cssys_clk, "cssys-clk", cssys_parents, 0x2a0,441 0, 4, 8, 2, 0);442 443static const struct clk_parent_data aon_pmu_parents[] = {444 { .fw_name = "ext-32k" },445 { .hw = &rco_4m.hw },446 { .fw_name = "ext-4m" },447};448static SPRD_MUX_CLK_DATA(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents, 0x2a8,449 0, 2, SC9863A_MUX_FLAG);450 451static const struct clk_parent_data pmu_26m_parents[] = {452 { .hw = &rco_4m.hw },453 { .hw = &rco_25m.hw },454 { .fw_name = "ext-26m" },455};456static SPRD_MUX_CLK_DATA(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents, 0x2ac,457 0, 2, SC9863A_MUX_FLAG);458 459static const struct clk_parent_data aon_tmr_parents[] = {460 { .hw = &rco_4m.hw },461 { .fw_name = "ext-26m" },462};463static SPRD_MUX_CLK_DATA(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents, 0x2b0,464 0, 1, SC9863A_MUX_FLAG);465 466static const struct clk_parent_data power_cpu_parents[] = {467 { .fw_name = "ext-26m" },468 { .hw = &rco_25m.hw },469 { .fw_name = "rco-100m" },470 { .hw = &twpll_128m.hw },471};472static SPRD_MUX_CLK_DATA(power_cpu_clk, "power-cpu-clk", power_cpu_parents, 0x2c4,473 0, 2, SC9863A_MUX_FLAG);474 475static const struct clk_parent_data ap_axi_parents[] = {476 { .fw_name = "ext-26m" },477 { .hw = &twpll_76m8.hw },478 { .hw = &twpll_128m.hw },479 { .hw = &twpll_256m.hw },480};481static SPRD_MUX_CLK_DATA(ap_axi, "ap-axi", ap_axi_parents, 0x2c8,482 0, 2, SC9863A_MUX_FLAG);483 484static const struct clk_parent_data sdio_parents[] = {485 { .fw_name = "ext-26m" },486 { .hw = &twpll_307m2.hw },487 { .hw = &twpll_384m.hw },488 { .hw = &rpll_390m.hw },489 { .hw = &dpll1_400m.hw },490 { .hw = &lpll_409m6.hw },491};492static SPRD_MUX_CLK_DATA(sdio0_2x, "sdio0-2x", sdio_parents, 0x2cc,493 0, 3, SC9863A_MUX_FLAG);494static SPRD_MUX_CLK_DATA(sdio1_2x, "sdio1-2x", sdio_parents, 0x2d4,495 0, 3, SC9863A_MUX_FLAG);496static SPRD_MUX_CLK_DATA(sdio2_2x, "sdio2-2x", sdio_parents, 0x2dc,497 0, 3, SC9863A_MUX_FLAG);498static SPRD_MUX_CLK_DATA(emmc_2x, "emmc-2x", sdio_parents, 0x2e4,499 0, 3, SC9863A_MUX_FLAG);500 501static const struct clk_parent_data dpu_parents[] = {502 { .hw = &twpll_153m6.hw },503 { .hw = &twpll_192m.hw },504 { .hw = &twpll_256m.hw },505 { .hw = &twpll_384m.hw },506};507static SPRD_MUX_CLK_DATA(dpu_clk, "dpu", dpu_parents, 0x2f4,508 0, 2, SC9863A_MUX_FLAG);509 510static const struct clk_parent_data dpu_dpi_parents[] = {511 { .hw = &twpll_128m.hw },512 { .hw = &twpll_153m6.hw },513 { .hw = &twpll_192m.hw },514};515static SPRD_COMP_CLK_DATA(dpu_dpi, "dpu-dpi", dpu_dpi_parents, 0x2f8,516 0, 2, 8, 4, 0);517 518static const struct clk_parent_data otg_ref_parents[] = {519 { .hw = &twpll_12m.hw },520 { .fw_name = "ext-26m" },521};522static SPRD_MUX_CLK_DATA(otg_ref_clk, "otg-ref-clk", otg_ref_parents, 0x308,523 0, 1, SC9863A_MUX_FLAG);524 525static const struct clk_parent_data sdphy_apb_parents[] = {526 { .fw_name = "ext-26m" },527 { .hw = &twpll_48m.hw },528};529static SPRD_MUX_CLK_DATA(sdphy_apb_clk, "sdphy-apb-clk", sdphy_apb_parents, 0x330,530 0, 1, SC9863A_MUX_FLAG);531 532static const struct clk_parent_data alg_io_apb_parents[] = {533 { .hw = &rco_4m.hw },534 { .fw_name = "ext-26m" },535 { .hw = &twpll_48m.hw },536 { .hw = &twpll_96m.hw },537};538static SPRD_MUX_CLK_DATA(alg_io_apb_clk, "alg-io-apb-clk", alg_io_apb_parents, 0x33c,539 0, 1, SC9863A_MUX_FLAG);540 541static const struct clk_parent_data gpu_parents[] = {542 { .hw = &twpll_153m6.hw },543 { .hw = &twpll_192m.hw },544 { .hw = &twpll_256m.hw },545 { .hw = &twpll_307m2.hw },546 { .hw = &twpll_384m.hw },547 { .hw = &twpll_512m.hw },548 { .hw = &gpll.common.hw },549};550static SPRD_COMP_CLK_DATA(gpu_core, "gpu-core", gpu_parents, 0x344,551 0, 3, 8, 2, 0);552static SPRD_COMP_CLK_DATA(gpu_soc, "gpu-soc", gpu_parents, 0x348,553 0, 3, 8, 2, 0);554 555static const struct clk_parent_data mm_emc_parents[] = {556 { .fw_name = "ext-26m" },557 { .hw = &twpll_384m.hw },558 { .hw = &isppll_468m.hw },559 { .hw = &twpll_512m.hw },560};561static SPRD_MUX_CLK_DATA(mm_emc, "mm-emc", mm_emc_parents, 0x350,562 0, 2, SC9863A_MUX_FLAG);563 564static const struct clk_parent_data mm_ahb_parents[] = {565 { .fw_name = "ext-26m" },566 { .hw = &twpll_96m.hw },567 { .hw = &twpll_128m.hw },568 { .hw = &twpll_153m6.hw },569};570static SPRD_MUX_CLK_DATA(mm_ahb, "mm-ahb", mm_ahb_parents, 0x354,571 0, 2, SC9863A_MUX_FLAG);572 573static const struct clk_parent_data bpc_clk_parents[] = {574 { .hw = &twpll_192m.hw },575 { .hw = &twpll_307m2.hw },576 { .hw = &twpll_384m.hw },577 { .hw = &isppll_468m.hw },578 { .hw = &dpll0_622m3.hw },579};580static SPRD_MUX_CLK_DATA(bpc_clk, "bpc-clk", bpc_clk_parents, 0x358,581 0, 3, SC9863A_MUX_FLAG);582 583static const struct clk_parent_data dcam_if_parents[] = {584 { .hw = &twpll_192m.hw },585 { .hw = &twpll_256m.hw },586 { .hw = &twpll_307m2.hw },587 { .hw = &twpll_384m.hw },588};589static SPRD_MUX_CLK_DATA(dcam_if_clk, "dcam-if-clk", dcam_if_parents, 0x35c,590 0, 2, SC9863A_MUX_FLAG);591 592static const struct clk_parent_data isp_parents[] = {593 { .hw = &twpll_128m.hw },594 { .hw = &twpll_256m.hw },595 { .hw = &twpll_307m2.hw },596 { .hw = &twpll_384m.hw },597 { .hw = &isppll_468m.hw },598};599static SPRD_MUX_CLK_DATA(isp_clk, "isp-clk", isp_parents, 0x360,600 0, 3, SC9863A_MUX_FLAG);601 602static const struct clk_parent_data jpg_parents[] = {603 { .hw = &twpll_76m8.hw },604 { .hw = &twpll_128m.hw },605 { .hw = &twpll_256m.hw },606 { .hw = &twpll_307m2.hw },607};608static SPRD_MUX_CLK_DATA(jpg_clk, "jpg-clk", jpg_parents, 0x364,609 0, 2, SC9863A_MUX_FLAG);610static SPRD_MUX_CLK_DATA(cpp_clk, "cpp-clk", jpg_parents, 0x368,611 0, 2, SC9863A_MUX_FLAG);612 613static const struct clk_parent_data sensor_parents[] = {614 { .fw_name = "ext-26m" },615 { .hw = &twpll_48m.hw },616 { .hw = &twpll_76m8.hw },617 { .hw = &twpll_96m.hw },618};619static SPRD_COMP_CLK_DATA(sensor0_clk, "sensor0-clk", sensor_parents, 0x36c,620 0, 2, 8, 3, 0);621static SPRD_COMP_CLK_DATA(sensor1_clk, "sensor1-clk", sensor_parents, 0x370,622 0, 2, 8, 3, 0);623static SPRD_COMP_CLK_DATA(sensor2_clk, "sensor2-clk", sensor_parents, 0x374,624 0, 2, 8, 3, 0);625 626static const struct clk_parent_data mm_vemc_parents[] = {627 { .fw_name = "ext-26m" },628 { .hw = &twpll_307m2.hw },629 { .hw = &twpll_384m.hw },630 { .hw = &isppll_468m.hw },631};632static SPRD_MUX_CLK_DATA(mm_vemc, "mm-vemc", mm_vemc_parents, 0x378,633 0, 2, SC9863A_MUX_FLAG);634 635static SPRD_MUX_CLK_DATA(mm_vahb, "mm-vahb", mm_ahb_parents, 0x37c,636 0, 2, SC9863A_MUX_FLAG);637 638static const struct clk_parent_data vsp_parents[] = {639 { .hw = &twpll_76m8.hw },640 { .hw = &twpll_128m.hw },641 { .hw = &twpll_256m.hw },642 { .hw = &twpll_307m2.hw },643 { .hw = &twpll_384m.hw },644};645static SPRD_MUX_CLK_DATA(clk_vsp, "vsp-clk", vsp_parents, 0x380,646 0, 3, SC9863A_MUX_FLAG);647 648static const struct clk_parent_data core_parents[] = {649 { .fw_name = "ext-26m" },650 { .hw = &twpll_512m.hw },651 { .hw = &twpll_768m.hw },652 { .hw = &lpll.common.hw },653 { .hw = &dpll0.common.hw },654 { .hw = &mpll2.common.hw },655 { .hw = &mpll0.common.hw },656 { .hw = &mpll1.common.hw },657};658static SPRD_COMP_CLK_DATA(core0_clk, "core0-clk", core_parents, 0xa20,659 0, 3, 8, 3, 0);660static SPRD_COMP_CLK_DATA(core1_clk, "core1-clk", core_parents, 0xa24,661 0, 3, 8, 3, 0);662static SPRD_COMP_CLK_DATA(core2_clk, "core2-clk", core_parents, 0xa28,663 0, 3, 8, 3, 0);664static SPRD_COMP_CLK_DATA(core3_clk, "core3-clk", core_parents, 0xa2c,665 0, 3, 8, 3, 0);666static SPRD_COMP_CLK_DATA(core4_clk, "core4-clk", core_parents, 0xa30,667 0, 3, 8, 3, 0);668static SPRD_COMP_CLK_DATA(core5_clk, "core5-clk", core_parents, 0xa34,669 0, 3, 8, 3, 0);670static SPRD_COMP_CLK_DATA(core6_clk, "core6-clk", core_parents, 0xa38,671 0, 3, 8, 3, 0);672static SPRD_COMP_CLK_DATA(core7_clk, "core7-clk", core_parents, 0xa3c,673 0, 3, 8, 3, 0);674static SPRD_COMP_CLK_DATA(scu_clk, "scu-clk", core_parents, 0xa40,675 0, 3, 8, 3, 0);676 677static SPRD_DIV_CLK_HW(ace_clk, "ace-clk", &scu_clk.common.hw, 0xa44,678 8, 3, 0);679static SPRD_DIV_CLK_HW(axi_periph_clk, "axi-periph-clk", &scu_clk.common.hw, 0xa48,680 8, 3, 0);681static SPRD_DIV_CLK_HW(axi_acp_clk, "axi-acp-clk", &scu_clk.common.hw, 0xa4c,682 8, 3, 0);683 684static const struct clk_parent_data atb_parents[] = {685 { .fw_name = "ext-26m" },686 { .hw = &twpll_384m.hw },687 { .hw = &twpll_512m.hw },688 { .hw = &mpll2.common.hw },689};690static SPRD_COMP_CLK_DATA(atb_clk, "atb-clk", atb_parents, 0xa50,691 0, 2, 8, 3, 0);692static SPRD_DIV_CLK_HW(debug_apb_clk, "debug-apb-clk", &atb_clk.common.hw, 0xa54,693 8, 3, 0);694 695static const struct clk_parent_data gic_parents[] = {696 { .fw_name = "ext-26m" },697 { .hw = &twpll_153m6.hw },698 { .hw = &twpll_384m.hw },699 { .hw = &twpll_512m.hw },700};701static SPRD_COMP_CLK_DATA(gic_clk, "gic-clk", gic_parents, 0xa58,702 0, 2, 8, 3, 0);703static SPRD_COMP_CLK_DATA(periph_clk, "periph-clk", gic_parents, 0xa5c,704 0, 2, 8, 3, 0);705 706static struct sprd_clk_common *sc9863a_aon_clks[] = {707 /* address base is 0x402d0000 */708 &emc_clk.common,709 &aon_apb.common,710 &adi_clk.common,711 &aux0_clk.common,712 &aux1_clk.common,713 &aux2_clk.common,714 &probe_clk.common,715 &pwm0_clk.common,716 &pwm1_clk.common,717 &pwm2_clk.common,718 &aon_thm_clk.common,719 &audif_clk.common,720 &cpu_dap_clk.common,721 &cpu_ts_clk.common,722 &djtag_tck_clk.common,723 &emc_ref_clk.common,724 &cssys_clk.common,725 &aon_pmu_clk.common,726 &pmu_26m_clk.common,727 &aon_tmr_clk.common,728 &power_cpu_clk.common,729 &ap_axi.common,730 &sdio0_2x.common,731 &sdio1_2x.common,732 &sdio2_2x.common,733 &emmc_2x.common,734 &dpu_clk.common,735 &dpu_dpi.common,736 &otg_ref_clk.common,737 &sdphy_apb_clk.common,738 &alg_io_apb_clk.common,739 &gpu_core.common,740 &gpu_soc.common,741 &mm_emc.common,742 &mm_ahb.common,743 &bpc_clk.common,744 &dcam_if_clk.common,745 &isp_clk.common,746 &jpg_clk.common,747 &cpp_clk.common,748 &sensor0_clk.common,749 &sensor1_clk.common,750 &sensor2_clk.common,751 &mm_vemc.common,752 &mm_vahb.common,753 &clk_vsp.common,754 &core0_clk.common,755 &core1_clk.common,756 &core2_clk.common,757 &core3_clk.common,758 &core4_clk.common,759 &core5_clk.common,760 &core6_clk.common,761 &core7_clk.common,762 &scu_clk.common,763 &ace_clk.common,764 &axi_periph_clk.common,765 &axi_acp_clk.common,766 &atb_clk.common,767 &debug_apb_clk.common,768 &gic_clk.common,769 &periph_clk.common,770};771 772static struct clk_hw_onecell_data sc9863a_aon_clk_hws = {773 .hws = {774 [CLK_13M] = &clk_13m.hw,775 [CLK_6M5] = &clk_6m5.hw,776 [CLK_4M3] = &clk_4m3.hw,777 [CLK_2M] = &clk_2m.hw,778 [CLK_250K] = &clk_250k.hw,779 [CLK_RCO_25M] = &rco_25m.hw,780 [CLK_RCO_4M] = &rco_4m.hw,781 [CLK_RCO_2M] = &rco_2m.hw,782 [CLK_EMC] = &emc_clk.common.hw,783 [CLK_AON_APB] = &aon_apb.common.hw,784 [CLK_ADI] = &adi_clk.common.hw,785 [CLK_AUX0] = &aux0_clk.common.hw,786 [CLK_AUX1] = &aux1_clk.common.hw,787 [CLK_AUX2] = &aux2_clk.common.hw,788 [CLK_PROBE] = &probe_clk.common.hw,789 [CLK_PWM0] = &pwm0_clk.common.hw,790 [CLK_PWM1] = &pwm1_clk.common.hw,791 [CLK_PWM2] = &pwm2_clk.common.hw,792 [CLK_AON_THM] = &aon_thm_clk.common.hw,793 [CLK_AUDIF] = &audif_clk.common.hw,794 [CLK_CPU_DAP] = &cpu_dap_clk.common.hw,795 [CLK_CPU_TS] = &cpu_ts_clk.common.hw,796 [CLK_DJTAG_TCK] = &djtag_tck_clk.common.hw,797 [CLK_EMC_REF] = &emc_ref_clk.common.hw,798 [CLK_CSSYS] = &cssys_clk.common.hw,799 [CLK_AON_PMU] = &aon_pmu_clk.common.hw,800 [CLK_PMU_26M] = &pmu_26m_clk.common.hw,801 [CLK_AON_TMR] = &aon_tmr_clk.common.hw,802 [CLK_POWER_CPU] = &power_cpu_clk.common.hw,803 [CLK_AP_AXI] = &ap_axi.common.hw,804 [CLK_SDIO0_2X] = &sdio0_2x.common.hw,805 [CLK_SDIO1_2X] = &sdio1_2x.common.hw,806 [CLK_SDIO2_2X] = &sdio2_2x.common.hw,807 [CLK_EMMC_2X] = &emmc_2x.common.hw,808 [CLK_DPU] = &dpu_clk.common.hw,809 [CLK_DPU_DPI] = &dpu_dpi.common.hw,810 [CLK_OTG_REF] = &otg_ref_clk.common.hw,811 [CLK_SDPHY_APB] = &sdphy_apb_clk.common.hw,812 [CLK_ALG_IO_APB] = &alg_io_apb_clk.common.hw,813 [CLK_GPU_CORE] = &gpu_core.common.hw,814 [CLK_GPU_SOC] = &gpu_soc.common.hw,815 [CLK_MM_EMC] = &mm_emc.common.hw,816 [CLK_MM_AHB] = &mm_ahb.common.hw,817 [CLK_BPC] = &bpc_clk.common.hw,818 [CLK_DCAM_IF] = &dcam_if_clk.common.hw,819 [CLK_ISP] = &isp_clk.common.hw,820 [CLK_JPG] = &jpg_clk.common.hw,821 [CLK_CPP] = &cpp_clk.common.hw,822 [CLK_SENSOR0] = &sensor0_clk.common.hw,823 [CLK_SENSOR1] = &sensor1_clk.common.hw,824 [CLK_SENSOR2] = &sensor2_clk.common.hw,825 [CLK_MM_VEMC] = &mm_vemc.common.hw,826 [CLK_MM_VAHB] = &mm_vahb.common.hw,827 [CLK_VSP] = &clk_vsp.common.hw,828 [CLK_CORE0] = &core0_clk.common.hw,829 [CLK_CORE1] = &core1_clk.common.hw,830 [CLK_CORE2] = &core2_clk.common.hw,831 [CLK_CORE3] = &core3_clk.common.hw,832 [CLK_CORE4] = &core4_clk.common.hw,833 [CLK_CORE5] = &core5_clk.common.hw,834 [CLK_CORE6] = &core6_clk.common.hw,835 [CLK_CORE7] = &core7_clk.common.hw,836 [CLK_SCU] = &scu_clk.common.hw,837 [CLK_ACE] = &ace_clk.common.hw,838 [CLK_AXI_PERIPH] = &axi_periph_clk.common.hw,839 [CLK_AXI_ACP] = &axi_acp_clk.common.hw,840 [CLK_ATB] = &atb_clk.common.hw,841 [CLK_DEBUG_APB] = &debug_apb_clk.common.hw,842 [CLK_GIC] = &gic_clk.common.hw,843 [CLK_PERIPH] = &periph_clk.common.hw,844 },845 .num = CLK_AON_CLK_NUM,846};847 848static const struct sprd_clk_desc sc9863a_aon_clk_desc = {849 .clk_clks = sc9863a_aon_clks,850 .num_clk_clks = ARRAY_SIZE(sc9863a_aon_clks),851 .hw_clks = &sc9863a_aon_clk_hws,852};853 854static const struct clk_parent_data ap_apb_parents[] = {855 { .fw_name = "ext-26m" },856 { .hw = &twpll_64m.hw },857 { .hw = &twpll_96m.hw },858 { .hw = &twpll_128m.hw },859};860static SPRD_MUX_CLK_DATA(ap_apb, "ap-apb", ap_apb_parents, 0x20,861 0, 2, SC9863A_MUX_FLAG);862 863static const struct clk_parent_data ap_ce_parents[] = {864 { .fw_name = "ext-26m" },865 { .hw = &twpll_256m.hw },866};867static SPRD_COMP_CLK_DATA(ap_ce, "ap-ce", ap_ce_parents, 0x24,868 0, 1, 8, 3, 0);869 870static const struct clk_parent_data nandc_ecc_parents[] = {871 { .fw_name = "ext-26m" },872 { .hw = &twpll_256m.hw },873 { .hw = &twpll_307m2.hw },874};875static SPRD_COMP_CLK_DATA(nandc_ecc, "nandc-ecc", nandc_ecc_parents, 0x28,876 0, 2, 8, 3, 0);877 878static const struct clk_parent_data nandc_26m_parents[] = {879 { .fw_name = "ext-32k" },880 { .fw_name = "ext-26m" },881};882static SPRD_MUX_CLK_DATA(nandc_26m, "nandc-26m", nandc_26m_parents, 0x2c,883 0, 1, SC9863A_MUX_FLAG);884static SPRD_MUX_CLK_DATA(emmc_32k, "emmc-32k", nandc_26m_parents, 0x30,885 0, 1, SC9863A_MUX_FLAG);886static SPRD_MUX_CLK_DATA(sdio0_32k, "sdio0-32k", nandc_26m_parents, 0x34,887 0, 1, SC9863A_MUX_FLAG);888static SPRD_MUX_CLK_DATA(sdio1_32k, "sdio1-32k", nandc_26m_parents, 0x38,889 0, 1, SC9863A_MUX_FLAG);890static SPRD_MUX_CLK_DATA(sdio2_32k, "sdio2-32k", nandc_26m_parents, 0x3c,891 0, 1, SC9863A_MUX_FLAG);892 893static SPRD_GATE_CLK_HW(otg_utmi, "otg-utmi", &aon_apb.common.hw, 0x40,894 BIT(16), 0, 0);895 896static const struct clk_parent_data ap_uart_parents[] = {897 { .fw_name = "ext-26m" },898 { .hw = &twpll_48m.hw },899 { .hw = &twpll_51m2.hw },900 { .hw = &twpll_96m.hw },901};902static SPRD_COMP_CLK_DATA(ap_uart0, "ap-uart0", ap_uart_parents, 0x44,903 0, 2, 8, 3, 0);904static SPRD_COMP_CLK_DATA(ap_uart1, "ap-uart1", ap_uart_parents, 0x48,905 0, 2, 8, 3, 0);906static SPRD_COMP_CLK_DATA(ap_uart2, "ap-uart2", ap_uart_parents, 0x4c,907 0, 2, 8, 3, 0);908static SPRD_COMP_CLK_DATA(ap_uart3, "ap-uart3", ap_uart_parents, 0x50,909 0, 2, 8, 3, 0);910static SPRD_COMP_CLK_DATA(ap_uart4, "ap-uart4", ap_uart_parents, 0x54,911 0, 2, 8, 3, 0);912 913static const struct clk_parent_data i2c_parents[] = {914 { .fw_name = "ext-26m" },915 { .hw = &twpll_48m.hw },916 { .hw = &twpll_51m2.hw },917 { .hw = &twpll_153m6.hw },918};919static SPRD_COMP_CLK_DATA(ap_i2c0, "ap-i2c0", i2c_parents, 0x58,920 0, 2, 8, 3, 0);921static SPRD_COMP_CLK_DATA(ap_i2c1, "ap-i2c1", i2c_parents, 0x5c,922 0, 2, 8, 3, 0);923static SPRD_COMP_CLK_DATA(ap_i2c2, "ap-i2c2", i2c_parents, 0x60,924 0, 2, 8, 3, 0);925static SPRD_COMP_CLK_DATA(ap_i2c3, "ap-i2c3", i2c_parents, 0x64,926 0, 2, 8, 3, 0);927static SPRD_COMP_CLK_DATA(ap_i2c4, "ap-i2c4", i2c_parents, 0x68,928 0, 2, 8, 3, 0);929static SPRD_COMP_CLK_DATA(ap_i2c5, "ap-i2c5", i2c_parents, 0x6c,930 0, 2, 8, 3, 0);931static SPRD_COMP_CLK_DATA(ap_i2c6, "ap-i2c6", i2c_parents, 0x70,932 0, 2, 8, 3, 0);933 934static const struct clk_parent_data spi_parents[] = {935 { .fw_name = "ext-26m" },936 { .hw = &twpll_128m.hw },937 { .hw = &twpll_153m6.hw },938 { .hw = &twpll_192m.hw },939};940static SPRD_COMP_CLK_DATA(ap_spi0, "ap-spi0", spi_parents, 0x74,941 0, 2, 8, 3, 0);942static SPRD_COMP_CLK_DATA(ap_spi1, "ap-spi1", spi_parents, 0x78,943 0, 2, 8, 3, 0);944static SPRD_COMP_CLK_DATA(ap_spi2, "ap-spi2", spi_parents, 0x7c,945 0, 2, 8, 3, 0);946static SPRD_COMP_CLK_DATA(ap_spi3, "ap-spi3", spi_parents, 0x80,947 0, 2, 8, 3, 0);948 949static const struct clk_parent_data iis_parents[] = {950 { .fw_name = "ext-26m" },951 { .hw = &twpll_128m.hw },952 { .hw = &twpll_153m6.hw },953};954static SPRD_COMP_CLK_DATA(ap_iis0, "ap-iis0", iis_parents, 0x84,955 0, 2, 8, 3, 0);956static SPRD_COMP_CLK_DATA(ap_iis1, "ap-iis1", iis_parents, 0x88,957 0, 2, 8, 3, 0);958static SPRD_COMP_CLK_DATA(ap_iis2, "ap-iis2", iis_parents, 0x8c,959 0, 2, 8, 3, 0);960 961static const struct clk_parent_data sim0_parents[] = {962 { .fw_name = "ext-26m" },963 { .hw = &twpll_51m2.hw },964 { .hw = &twpll_64m.hw },965 { .hw = &twpll_96m.hw },966 { .hw = &twpll_128m.hw },967};968static SPRD_COMP_CLK_DATA(sim0, "sim0", sim0_parents, 0x90,969 0, 3, 8, 3, 0);970 971static const struct clk_parent_data sim0_32k_parents[] = {972 { .fw_name = "ext-32k" },973 { .fw_name = "ext-26m" },974};975static SPRD_MUX_CLK_DATA(sim0_32k, "sim0-32k", sim0_32k_parents, 0x94,976 0, 1, SC9863A_MUX_FLAG);977 978static struct sprd_clk_common *sc9863a_ap_clks[] = {979 /* address base is 0x21500000 */980 &ap_apb.common,981 &ap_ce.common,982 &nandc_ecc.common,983 &nandc_26m.common,984 &emmc_32k.common,985 &sdio0_32k.common,986 &sdio1_32k.common,987 &sdio2_32k.common,988 &otg_utmi.common,989 &ap_uart0.common,990 &ap_uart1.common,991 &ap_uart2.common,992 &ap_uart3.common,993 &ap_uart4.common,994 &ap_i2c0.common,995 &ap_i2c1.common,996 &ap_i2c2.common,997 &ap_i2c3.common,998 &ap_i2c4.common,999 &ap_i2c5.common,1000 &ap_i2c6.common,1001 &ap_spi0.common,1002 &ap_spi1.common,1003 &ap_spi2.common,1004 &ap_spi3.common,1005 &ap_iis0.common,1006 &ap_iis1.common,1007 &ap_iis2.common,1008 &sim0.common,1009 &sim0_32k.common,1010};1011 1012static struct clk_hw_onecell_data sc9863a_ap_clk_hws = {1013 .hws = {1014 [CLK_AP_APB] = &ap_apb.common.hw,1015 [CLK_AP_CE] = &ap_ce.common.hw,1016 [CLK_NANDC_ECC] = &nandc_ecc.common.hw,1017 [CLK_NANDC_26M] = &nandc_26m.common.hw,1018 [CLK_EMMC_32K] = &emmc_32k.common.hw,1019 [CLK_SDIO0_32K] = &sdio0_32k.common.hw,1020 [CLK_SDIO1_32K] = &sdio1_32k.common.hw,1021 [CLK_SDIO2_32K] = &sdio2_32k.common.hw,1022 [CLK_OTG_UTMI] = &otg_utmi.common.hw,1023 [CLK_AP_UART0] = &ap_uart0.common.hw,1024 [CLK_AP_UART1] = &ap_uart1.common.hw,1025 [CLK_AP_UART2] = &ap_uart2.common.hw,1026 [CLK_AP_UART3] = &ap_uart3.common.hw,1027 [CLK_AP_UART4] = &ap_uart4.common.hw,1028 [CLK_AP_I2C0] = &ap_i2c0.common.hw,1029 [CLK_AP_I2C1] = &ap_i2c1.common.hw,1030 [CLK_AP_I2C2] = &ap_i2c2.common.hw,1031 [CLK_AP_I2C3] = &ap_i2c3.common.hw,1032 [CLK_AP_I2C4] = &ap_i2c4.common.hw,1033 [CLK_AP_I2C5] = &ap_i2c5.common.hw,1034 [CLK_AP_I2C6] = &ap_i2c6.common.hw,1035 [CLK_AP_SPI0] = &ap_spi0.common.hw,1036 [CLK_AP_SPI1] = &ap_spi1.common.hw,1037 [CLK_AP_SPI2] = &ap_spi2.common.hw,1038 [CLK_AP_SPI3] = &ap_spi3.common.hw,1039 [CLK_AP_IIS0] = &ap_iis0.common.hw,1040 [CLK_AP_IIS1] = &ap_iis1.common.hw,1041 [CLK_AP_IIS2] = &ap_iis2.common.hw,1042 [CLK_SIM0] = &sim0.common.hw,1043 [CLK_SIM0_32K] = &sim0_32k.common.hw,1044 },1045 .num = CLK_AP_CLK_NUM,1046};1047 1048static const struct sprd_clk_desc sc9863a_ap_clk_desc = {1049 .clk_clks = sc9863a_ap_clks,1050 .num_clk_clks = ARRAY_SIZE(sc9863a_ap_clks),1051 .hw_clks = &sc9863a_ap_clk_hws,1052};1053 1054static SPRD_SC_GATE_CLK_HW(otg_eb, "otg-eb", &ap_axi.common.hw, 0x0, 0x1000,1055 BIT(4), 0, 0);1056static SPRD_SC_GATE_CLK_HW(dma_eb, "dma-eb", &ap_axi.common.hw, 0x0, 0x1000,1057 BIT(5), 0, 0);1058static SPRD_SC_GATE_CLK_HW(ce_eb, "ce-eb", &ap_axi.common.hw, 0x0, 0x1000,1059 BIT(6), 0, 0);1060static SPRD_SC_GATE_CLK_HW(nandc_eb, "nandc-eb", &ap_axi.common.hw, 0x0, 0x1000,1061 BIT(7), 0, 0);1062static SPRD_SC_GATE_CLK_HW(sdio0_eb, "sdio0-eb", &ap_axi.common.hw, 0x0, 0x1000,1063 BIT(8), 0, 0);1064static SPRD_SC_GATE_CLK_HW(sdio1_eb, "sdio1-eb", &ap_axi.common.hw, 0x0, 0x1000,1065 BIT(9), 0, 0);1066static SPRD_SC_GATE_CLK_HW(sdio2_eb, "sdio2-eb", &ap_axi.common.hw, 0x0, 0x1000,1067 BIT(10), 0, 0);1068static SPRD_SC_GATE_CLK_HW(emmc_eb, "emmc-eb", &ap_axi.common.hw, 0x0, 0x1000,1069 BIT(11), 0, 0);1070static SPRD_SC_GATE_CLK_HW(emmc_32k_eb, "emmc-32k-eb", &ap_axi.common.hw, 0x0,1071 0x1000, BIT(27), 0, 0);1072static SPRD_SC_GATE_CLK_HW(sdio0_32k_eb, "sdio0-32k-eb", &ap_axi.common.hw, 0x0,1073 0x1000, BIT(28), 0, 0);1074static SPRD_SC_GATE_CLK_HW(sdio1_32k_eb, "sdio1-32k-eb", &ap_axi.common.hw, 0x0,1075 0x1000, BIT(29), 0, 0);1076static SPRD_SC_GATE_CLK_HW(sdio2_32k_eb, "sdio2-32k-eb", &ap_axi.common.hw, 0x0,1077 0x1000, BIT(30), 0, 0);1078static SPRD_SC_GATE_CLK_HW(nandc_26m_eb, "nandc-26m-eb", &ap_axi.common.hw, 0x0,1079 0x1000, BIT(31), 0, 0);1080static SPRD_SC_GATE_CLK_HW(dma_eb2, "dma-eb2", &ap_axi.common.hw, 0x18,1081 0x1000, BIT(0), 0, 0);1082static SPRD_SC_GATE_CLK_HW(ce_eb2, "ce-eb2", &ap_axi.common.hw, 0x18,1083 0x1000, BIT(1), 0, 0);1084 1085static struct sprd_clk_common *sc9863a_apahb_gate_clks[] = {1086 /* address base is 0x20e00000 */1087 &otg_eb.common,1088 &dma_eb.common,1089 &ce_eb.common,1090 &nandc_eb.common,1091 &sdio0_eb.common,1092 &sdio1_eb.common,1093 &sdio2_eb.common,1094 &emmc_eb.common,1095 &emmc_32k_eb.common,1096 &sdio0_32k_eb.common,1097 &sdio1_32k_eb.common,1098 &sdio2_32k_eb.common,1099 &nandc_26m_eb.common,1100 &dma_eb2.common,1101 &ce_eb2.common,1102};1103 1104static struct clk_hw_onecell_data sc9863a_apahb_gate_hws = {1105 .hws = {1106 [CLK_OTG_EB] = &otg_eb.common.hw,1107 [CLK_DMA_EB] = &dma_eb.common.hw,1108 [CLK_CE_EB] = &ce_eb.common.hw,1109 [CLK_NANDC_EB] = &nandc_eb.common.hw,1110 [CLK_SDIO0_EB] = &sdio0_eb.common.hw,1111 [CLK_SDIO1_EB] = &sdio1_eb.common.hw,1112 [CLK_SDIO2_EB] = &sdio2_eb.common.hw,1113 [CLK_EMMC_EB] = &emmc_eb.common.hw,1114 [CLK_EMMC_32K_EB] = &emmc_32k_eb.common.hw,1115 [CLK_SDIO0_32K_EB] = &sdio0_32k_eb.common.hw,1116 [CLK_SDIO1_32K_EB] = &sdio1_32k_eb.common.hw,1117 [CLK_SDIO2_32K_EB] = &sdio2_32k_eb.common.hw,1118 [CLK_NANDC_26M_EB] = &nandc_26m_eb.common.hw,1119 [CLK_DMA_EB2] = &dma_eb2.common.hw,1120 [CLK_CE_EB2] = &ce_eb2.common.hw,1121 },1122 .num = CLK_AP_AHB_GATE_NUM,1123};1124 1125static const struct sprd_clk_desc sc9863a_apahb_gate_desc = {1126 .clk_clks = sc9863a_apahb_gate_clks,1127 .num_clk_clks = ARRAY_SIZE(sc9863a_apahb_gate_clks),1128 .hw_clks = &sc9863a_apahb_gate_hws,1129};1130 1131/* aon gate clocks */1132static SPRD_SC_GATE_CLK_HW(gpio_eb, "gpio-eb", &aon_apb.common.hw,1133 0x0, 0x1000, BIT(3), 0, 0);1134static SPRD_SC_GATE_CLK_HW(pwm0_eb, "pwm0-eb", &aon_apb.common.hw,1135 0x0, 0x1000, BIT(4), 0, 0);1136static SPRD_SC_GATE_CLK_HW(pwm1_eb, "pwm1-eb", &aon_apb.common.hw,1137 0x0, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);1138static SPRD_SC_GATE_CLK_HW(pwm2_eb, "pwm2-eb", &aon_apb.common.hw, 0x0,1139 0x1000, BIT(6), 0, 0);1140static SPRD_SC_GATE_CLK_HW(pwm3_eb, "pwm3-eb", &aon_apb.common.hw, 0x0,1141 0x1000, BIT(7), 0, 0);1142static SPRD_SC_GATE_CLK_HW(kpd_eb, "kpd-eb", &aon_apb.common.hw, 0x0,1143 0x1000, BIT(8), 0, 0);1144static SPRD_SC_GATE_CLK_HW(aon_syst_eb, "aon-syst-eb", &aon_apb.common.hw, 0x0,1145 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);1146static SPRD_SC_GATE_CLK_HW(ap_syst_eb, "ap-syst-eb", &aon_apb.common.hw, 0x0,1147 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);1148static SPRD_SC_GATE_CLK_HW(aon_tmr_eb, "aon-tmr-eb", &aon_apb.common.hw, 0x0,1149 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);1150static SPRD_SC_GATE_CLK_HW(efuse_eb, "efuse-eb", &aon_apb.common.hw, 0x0,1151 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);1152static SPRD_SC_GATE_CLK_HW(eic_eb, "eic-eb", &aon_apb.common.hw, 0x0,1153 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);1154static SPRD_SC_GATE_CLK_HW(intc_eb, "intc-eb", &aon_apb.common.hw, 0x0,1155 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);1156static SPRD_SC_GATE_CLK_HW(adi_eb, "adi-eb", &aon_apb.common.hw, 0x0,1157 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);1158static SPRD_SC_GATE_CLK_HW(audif_eb, "audif-eb", &aon_apb.common.hw, 0x0,1159 0x1000, BIT(17), 0, 0);1160static SPRD_SC_GATE_CLK_HW(aud_eb, "aud-eb", &aon_apb.common.hw, 0x0,1161 0x1000, BIT(18), 0, 0);1162static SPRD_SC_GATE_CLK_HW(vbc_eb, "vbc-eb", &aon_apb.common.hw, 0x0,1163 0x1000, BIT(19), 0, 0);1164static SPRD_SC_GATE_CLK_HW(pin_eb, "pin-eb", &aon_apb.common.hw, 0x0,1165 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);1166static SPRD_SC_GATE_CLK_HW(ap_wdg_eb, "ap-wdg-eb", &aon_apb.common.hw, 0x0,1167 0x1000, BIT(24), 0, 0);1168static SPRD_SC_GATE_CLK_HW(mm_eb, "mm-eb", &aon_apb.common.hw, 0x0,1169 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);1170static SPRD_SC_GATE_CLK_HW(aon_apb_ckg_eb, "aon-apb-ckg-eb", &aon_apb.common.hw,1171 0x0, 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);1172static SPRD_SC_GATE_CLK_HW(ca53_ts0_eb, "ca53-ts0-eb", &aon_apb.common.hw,1173 0x0, 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);1174static SPRD_SC_GATE_CLK_HW(ca53_ts1_eb, "ca53-ts1-eb", &aon_apb.common.hw,1175 0x0, 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);1176static SPRD_SC_GATE_CLK_HW(ca53_dap_eb, "ca53-dap-eb", &aon_apb.common.hw,1177 0x0, 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);1178static SPRD_SC_GATE_CLK_HW(pmu_eb, "pmu-eb", &aon_apb.common.hw,1179 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);1180static SPRD_SC_GATE_CLK_HW(thm_eb, "thm-eb", &aon_apb.common.hw,1181 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);1182static SPRD_SC_GATE_CLK_HW(aux0_eb, "aux0-eb", &aon_apb.common.hw,1183 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);1184static SPRD_SC_GATE_CLK_HW(aux1_eb, "aux1-eb", &aon_apb.common.hw,1185 0x4, 0x1000, BIT(3), 0, 0);1186static SPRD_SC_GATE_CLK_HW(aux2_eb, "aux2-eb", &aon_apb.common.hw,1187 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);1188static SPRD_SC_GATE_CLK_HW(probe_eb, "probe-eb", &aon_apb.common.hw,1189 0x4, 0x1000, BIT(5), 0, 0);1190static SPRD_SC_GATE_CLK_HW(emc_ref_eb, "emc-ref-eb", &aon_apb.common.hw,1191 0x4, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);1192static SPRD_SC_GATE_CLK_HW(ca53_wdg_eb, "ca53-wdg-eb", &aon_apb.common.hw,1193 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);1194static SPRD_SC_GATE_CLK_HW(ap_tmr1_eb, "ap-tmr1-eb", &aon_apb.common.hw,1195 0x4, 0x1000, BIT(9), 0, 0);1196static SPRD_SC_GATE_CLK_HW(ap_tmr2_eb, "ap-tmr2-eb", &aon_apb.common.hw,1197 0x4, 0x1000, BIT(10), 0, 0);1198static SPRD_SC_GATE_CLK_HW(disp_emc_eb, "disp-emc-eb", &aon_apb.common.hw,1199 0x4, 0x1000, BIT(11), 0, 0);1200static SPRD_SC_GATE_CLK_HW(zip_emc_eb, "zip-emc-eb", &aon_apb.common.hw,1201 0x4, 0x1000, BIT(12), 0, 0);1202static SPRD_SC_GATE_CLK_HW(gsp_emc_eb, "gsp-emc-eb", &aon_apb.common.hw,1203 0x4, 0x1000, BIT(13), 0, 0);1204static SPRD_SC_GATE_CLK_HW(mm_vsp_eb, "mm-vsp-eb", &aon_apb.common.hw,1205 0x4, 0x1000, BIT(14), 0, 0);1206static SPRD_SC_GATE_CLK_HW(mdar_eb, "mdar-eb", &aon_apb.common.hw,1207 0x4, 0x1000, BIT(17), 0, 0);1208static SPRD_SC_GATE_CLK_HW(rtc4m0_cal_eb, "rtc4m0-cal-eb", &aon_apb.common.hw,1209 0x4, 0x1000, BIT(18), 0, 0);1210static SPRD_SC_GATE_CLK_HW(rtc4m1_cal_eb, "rtc4m1-cal-eb", &aon_apb.common.hw,1211 0x4, 0x1000, BIT(19), 0, 0);1212static SPRD_SC_GATE_CLK_HW(djtag_eb, "djtag-eb", &aon_apb.common.hw,1213 0x4, 0x1000, BIT(20), 0, 0);1214static SPRD_SC_GATE_CLK_HW(mbox_eb, "mbox-eb", &aon_apb.common.hw,1215 0x4, 0x1000, BIT(21), 0, 0);1216static SPRD_SC_GATE_CLK_HW(aon_dma_eb, "aon-dma-eb", &aon_apb.common.hw,1217 0x4, 0x1000, BIT(22), 0, 0);1218static SPRD_SC_GATE_CLK_HW(aon_apb_def_eb, "aon-apb-def-eb", &aon_apb.common.hw,1219 0x4, 0x1000, BIT(25), 0, 0);1220static SPRD_SC_GATE_CLK_HW(ca5_ts0_eb, "ca5-ts0-eb", &aon_apb.common.hw,1221 0x4, 0x1000, BIT(26), 0, 0);1222static SPRD_SC_GATE_CLK_HW(dbg_eb, "dbg-eb", &aon_apb.common.hw,1223 0x4, 0x1000, BIT(28), 0, 0);1224static SPRD_SC_GATE_CLK_HW(dbg_emc_eb, "dbg-emc-eb", &aon_apb.common.hw,1225 0x4, 0x1000, BIT(29), 0, 0);1226static SPRD_SC_GATE_CLK_HW(cross_trig_eb, "cross-trig-eb", &aon_apb.common.hw,1227 0x4, 0x1000, BIT(30), 0, 0);1228static SPRD_SC_GATE_CLK_HW(serdes_dphy_eb, "serdes-dphy-eb", &aon_apb.common.hw,1229 0x4, 0x1000, BIT(31), 0, 0);1230static SPRD_SC_GATE_CLK_HW(arch_rtc_eb, "arch-rtc-eb", &aon_apb.common.hw,1231 0x10, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);1232static SPRD_SC_GATE_CLK_HW(kpd_rtc_eb, "kpd-rtc-eb", &aon_apb.common.hw,1233 0x10, 0x1000, BIT(1), 0, 0);1234static SPRD_SC_GATE_CLK_HW(aon_syst_rtc_eb, "aon-syst-rtc-eb", &aon_apb.common.hw,1235 0x10, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);1236static SPRD_SC_GATE_CLK_HW(ap_syst_rtc_eb, "ap-syst-rtc-eb", &aon_apb.common.hw,1237 0x10, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);1238static SPRD_SC_GATE_CLK_HW(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", &aon_apb.common.hw,1239 0x10, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);1240static SPRD_SC_GATE_CLK_HW(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", &aon_apb.common.hw,1241 0x10, 0x1000, BIT(5), 0, 0);1242static SPRD_SC_GATE_CLK_HW(eic_rtc_eb, "eic-rtc-eb", &aon_apb.common.hw,1243 0x10, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);1244static SPRD_SC_GATE_CLK_HW(eic_rtcdv5_eb, "eic-rtcdv5-eb", &aon_apb.common.hw,1245 0x10, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);1246static SPRD_SC_GATE_CLK_HW(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", &aon_apb.common.hw,1247 0x10, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);1248static SPRD_SC_GATE_CLK_HW(ca53_wdg_rtc_eb, "ca53-wdg-rtc-eb", &aon_apb.common.hw,1249 0x10, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);1250static SPRD_SC_GATE_CLK_HW(thm_rtc_eb, "thm-rtc-eb", &aon_apb.common.hw,1251 0x10, 0x1000, BIT(10), 0, 0);1252static SPRD_SC_GATE_CLK_HW(athma_rtc_eb, "athma-rtc-eb", &aon_apb.common.hw,1253 0x10, 0x1000, BIT(11), 0, 0);1254static SPRD_SC_GATE_CLK_HW(gthma_rtc_eb, "gthma-rtc-eb", &aon_apb.common.hw,1255 0x10, 0x1000, BIT(12), 0, 0);1256static SPRD_SC_GATE_CLK_HW(athma_rtc_a_eb, "athma-rtc-a-eb", &aon_apb.common.hw,1257 0x10, 0x1000, BIT(13), 0, 0);1258static SPRD_SC_GATE_CLK_HW(gthma_rtc_a_eb, "gthma-rtc-a-eb", &aon_apb.common.hw,1259 0x10, 0x1000, BIT(14), 0, 0);1260static SPRD_SC_GATE_CLK_HW(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", &aon_apb.common.hw,1261 0x10, 0x1000, BIT(15), 0, 0);1262static SPRD_SC_GATE_CLK_HW(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", &aon_apb.common.hw,1263 0x10, 0x1000, BIT(16), 0, 0);1264static SPRD_SC_GATE_CLK_HW(dxco_lc_rtc_eb, "dxco-lc-rtc-eb", &aon_apb.common.hw,1265 0x10, 0x1000, BIT(17), 0, 0);1266static SPRD_SC_GATE_CLK_HW(bb_cal_rtc_eb, "bb-cal-rtc-eb", &aon_apb.common.hw,1267 0x10, 0x1000, BIT(18), 0, 0);1268static SPRD_SC_GATE_CLK_HW(gpu_eb, "gpu-eb", &aon_apb.common.hw, 0x50,1269 0x1000, BIT(0), 0, 0);1270static SPRD_SC_GATE_CLK_HW(disp_eb, "disp-eb", &aon_apb.common.hw, 0x50,1271 0x1000, BIT(2), 0, 0);1272static SPRD_SC_GATE_CLK_HW(mm_emc_eb, "mm-emc-eb", &aon_apb.common.hw, 0x50,1273 0x1000, BIT(3), 0, 0);1274static SPRD_SC_GATE_CLK_HW(power_cpu_eb, "power-cpu-eb", &aon_apb.common.hw, 0x50,1275 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);1276static SPRD_SC_GATE_CLK_HW(hw_i2c_eb, "hw-i2c-eb", &aon_apb.common.hw, 0x50,1277 0x1000, BIT(11), 0, 0);1278static SPRD_SC_GATE_CLK_HW(mm_vsp_emc_eb, "mm-vsp-emc-eb", &aon_apb.common.hw, 0x50,1279 0x1000, BIT(14), 0, 0);1280static SPRD_SC_GATE_CLK_HW(vsp_eb, "vsp-eb", &aon_apb.common.hw, 0x50,1281 0x1000, BIT(16), 0, 0);1282static SPRD_SC_GATE_CLK_HW(cssys_eb, "cssys-eb", &aon_apb.common.hw, 0xb0,1283 0x1000, BIT(4), 0, 0);1284static SPRD_SC_GATE_CLK_HW(dmc_eb, "dmc-eb", &aon_apb.common.hw, 0xb0,1285 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);1286static SPRD_SC_GATE_CLK_HW(rosc_eb, "rosc-eb", &aon_apb.common.hw, 0xb0,1287 0x1000, BIT(7), 0, 0);1288static SPRD_SC_GATE_CLK_HW(s_d_cfg_eb, "s-d-cfg-eb", &aon_apb.common.hw, 0xb0,1289 0x1000, BIT(8), 0, 0);1290static SPRD_SC_GATE_CLK_HW(s_d_ref_eb, "s-d-ref-eb", &aon_apb.common.hw, 0xb0,1291 0x1000, BIT(9), 0, 0);1292static SPRD_SC_GATE_CLK_HW(b_dma_eb, "b-dma-eb", &aon_apb.common.hw, 0xb0,1293 0x1000, BIT(10), 0, 0);1294static SPRD_SC_GATE_CLK_HW(anlg_eb, "anlg-eb", &aon_apb.common.hw, 0xb0,1295 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);1296static SPRD_SC_GATE_CLK_HW(anlg_apb_eb, "anlg-apb-eb", &aon_apb.common.hw, 0xb0,1297 0x1000, BIT(13), 0, 0);1298static SPRD_SC_GATE_CLK_HW(bsmtmr_eb, "bsmtmr-eb", &aon_apb.common.hw, 0xb0,1299 0x1000, BIT(14), 0, 0);1300static SPRD_SC_GATE_CLK_HW(ap_axi_eb, "ap-axi-eb", &aon_apb.common.hw, 0xb0,1301 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);1302static SPRD_SC_GATE_CLK_HW(ap_intc0_eb, "ap-intc0-eb", &aon_apb.common.hw, 0xb0,1303 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);1304static SPRD_SC_GATE_CLK_HW(ap_intc1_eb, "ap-intc1-eb", &aon_apb.common.hw, 0xb0,1305 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);1306static SPRD_SC_GATE_CLK_HW(ap_intc2_eb, "ap-intc2-eb", &aon_apb.common.hw, 0xb0,1307 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);1308static SPRD_SC_GATE_CLK_HW(ap_intc3_eb, "ap-intc3-eb", &aon_apb.common.hw, 0xb0,1309 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);1310static SPRD_SC_GATE_CLK_HW(ap_intc4_eb, "ap-intc4-eb", &aon_apb.common.hw, 0xb0,1311 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);1312static SPRD_SC_GATE_CLK_HW(ap_intc5_eb, "ap-intc5-eb", &aon_apb.common.hw, 0xb0,1313 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);1314static SPRD_SC_GATE_CLK_HW(scc_eb, "scc-eb", &aon_apb.common.hw, 0xb0,1315 0x1000, BIT(22), 0, 0);1316static SPRD_SC_GATE_CLK_HW(dphy_cfg_eb, "dphy-cfg-eb", &aon_apb.common.hw, 0xb0,1317 0x1000, BIT(23), 0, 0);1318static SPRD_SC_GATE_CLK_HW(dphy_ref_eb, "dphy-ref-eb", &aon_apb.common.hw, 0xb0,1319 0x1000, BIT(24), 0, 0);1320static SPRD_SC_GATE_CLK_HW(cphy_cfg_eb, "cphy-cfg-eb", &aon_apb.common.hw, 0xb0,1321 0x1000, BIT(25), 0, 0);1322static SPRD_SC_GATE_CLK_HW(otg_ref_eb, "otg-ref-eb", &aon_apb.common.hw, 0xb0,1323 0x1000, BIT(26), 0, 0);1324static SPRD_SC_GATE_CLK_HW(serdes_eb, "serdes-eb", &aon_apb.common.hw, 0xb0,1325 0x1000, BIT(27), 0, 0);1326static SPRD_SC_GATE_CLK_HW(aon_ap_emc_eb, "aon-ap-emc-eb", &aon_apb.common.hw, 0xb0,1327 0x1000, BIT(28), 0, 0);1328static struct sprd_clk_common *sc9863a_aonapb_gate_clks[] = {1329 /* address base is 0x402e0000 */1330 &gpio_eb.common,1331 &pwm0_eb.common,1332 &pwm1_eb.common,1333 &pwm2_eb.common,1334 &pwm3_eb.common,1335 &kpd_eb.common,1336 &aon_syst_eb.common,1337 &ap_syst_eb.common,1338 &aon_tmr_eb.common,1339 &efuse_eb.common,1340 &eic_eb.common,1341 &intc_eb.common,1342 &adi_eb.common,1343 &audif_eb.common,1344 &aud_eb.common,1345 &vbc_eb.common,1346 &pin_eb.common,1347 &ap_wdg_eb.common,1348 &mm_eb.common,1349 &aon_apb_ckg_eb.common,1350 &ca53_ts0_eb.common,1351 &ca53_ts1_eb.common,1352 &ca53_dap_eb.common,1353 &pmu_eb.common,1354 &thm_eb.common,1355 &aux0_eb.common,1356 &aux1_eb.common,1357 &aux2_eb.common,1358 &probe_eb.common,1359 &emc_ref_eb.common,1360 &ca53_wdg_eb.common,1361 &ap_tmr1_eb.common,1362 &ap_tmr2_eb.common,1363 &disp_emc_eb.common,1364 &zip_emc_eb.common,1365 &gsp_emc_eb.common,1366 &mm_vsp_eb.common,1367 &mdar_eb.common,1368 &rtc4m0_cal_eb.common,1369 &rtc4m1_cal_eb.common,1370 &djtag_eb.common,1371 &mbox_eb.common,1372 &aon_dma_eb.common,1373 &aon_apb_def_eb.common,1374 &ca5_ts0_eb.common,1375 &dbg_eb.common,1376 &dbg_emc_eb.common,1377 &cross_trig_eb.common,1378 &serdes_dphy_eb.common,1379 &arch_rtc_eb.common,1380 &kpd_rtc_eb.common,1381 &aon_syst_rtc_eb.common,1382 &ap_syst_rtc_eb.common,1383 &aon_tmr_rtc_eb.common,1384 &ap_tmr0_rtc_eb.common,1385 &eic_rtc_eb.common,1386 &eic_rtcdv5_eb.common,1387 &ap_wdg_rtc_eb.common,1388 &ca53_wdg_rtc_eb.common,1389 &thm_rtc_eb.common,1390 &athma_rtc_eb.common,1391 >hma_rtc_eb.common,1392 &athma_rtc_a_eb.common,1393 >hma_rtc_a_eb.common,1394 &ap_tmr1_rtc_eb.common,1395 &ap_tmr2_rtc_eb.common,1396 &dxco_lc_rtc_eb.common,1397 &bb_cal_rtc_eb.common,1398 &gpu_eb.common,1399 &disp_eb.common,1400 &mm_emc_eb.common,1401 &power_cpu_eb.common,1402 &hw_i2c_eb.common,1403 &mm_vsp_emc_eb.common,1404 &vsp_eb.common,1405 &cssys_eb.common,1406 &dmc_eb.common,1407 &rosc_eb.common,1408 &s_d_cfg_eb.common,1409 &s_d_ref_eb.common,1410 &b_dma_eb.common,1411 &anlg_eb.common,1412 &anlg_apb_eb.common,1413 &bsmtmr_eb.common,1414 &ap_axi_eb.common,1415 &ap_intc0_eb.common,1416 &ap_intc1_eb.common,1417 &ap_intc2_eb.common,1418 &ap_intc3_eb.common,1419 &ap_intc4_eb.common,1420 &ap_intc5_eb.common,1421 &scc_eb.common,1422 &dphy_cfg_eb.common,1423 &dphy_ref_eb.common,1424 &cphy_cfg_eb.common,1425 &otg_ref_eb.common,1426 &serdes_eb.common,1427 &aon_ap_emc_eb.common,1428};1429 1430static struct clk_hw_onecell_data sc9863a_aonapb_gate_hws = {1431 .hws = {1432 [CLK_GPIO_EB] = &gpio_eb.common.hw,1433 [CLK_PWM0_EB] = &pwm0_eb.common.hw,1434 [CLK_PWM1_EB] = &pwm1_eb.common.hw,1435 [CLK_PWM2_EB] = &pwm2_eb.common.hw,1436 [CLK_PWM3_EB] = &pwm3_eb.common.hw,1437 [CLK_KPD_EB] = &kpd_eb.common.hw,1438 [CLK_AON_SYST_EB] = &aon_syst_eb.common.hw,1439 [CLK_AP_SYST_EB] = &ap_syst_eb.common.hw,1440 [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,1441 [CLK_EFUSE_EB] = &efuse_eb.common.hw,1442 [CLK_EIC_EB] = &eic_eb.common.hw,1443 [CLK_INTC_EB] = &intc_eb.common.hw,1444 [CLK_ADI_EB] = &adi_eb.common.hw,1445 [CLK_AUDIF_EB] = &audif_eb.common.hw,1446 [CLK_AUD_EB] = &aud_eb.common.hw,1447 [CLK_VBC_EB] = &vbc_eb.common.hw,1448 [CLK_PIN_EB] = &pin_eb.common.hw,1449 [CLK_AP_WDG_EB] = &ap_wdg_eb.common.hw,1450 [CLK_MM_EB] = &mm_eb.common.hw,1451 [CLK_AON_APB_CKG_EB] = &aon_apb_ckg_eb.common.hw,1452 [CLK_CA53_TS0_EB] = &ca53_ts0_eb.common.hw,1453 [CLK_CA53_TS1_EB] = &ca53_ts1_eb.common.hw,1454 [CLK_CS53_DAP_EB] = &ca53_dap_eb.common.hw,1455 [CLK_PMU_EB] = &pmu_eb.common.hw,1456 [CLK_THM_EB] = &thm_eb.common.hw,1457 [CLK_AUX0_EB] = &aux0_eb.common.hw,1458 [CLK_AUX1_EB] = &aux1_eb.common.hw,1459 [CLK_AUX2_EB] = &aux2_eb.common.hw,1460 [CLK_PROBE_EB] = &probe_eb.common.hw,1461 [CLK_EMC_REF_EB] = &emc_ref_eb.common.hw,1462 [CLK_CA53_WDG_EB] = &ca53_wdg_eb.common.hw,1463 [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,1464 [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,1465 [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw,1466 [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw,1467 [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw,1468 [CLK_MM_VSP_EB] = &mm_vsp_eb.common.hw,1469 [CLK_MDAR_EB] = &mdar_eb.common.hw,1470 [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw,1471 [CLK_RTC4M1_CAL_EB] = &rtc4m1_cal_eb.common.hw,1472 [CLK_DJTAG_EB] = &djtag_eb.common.hw,1473 [CLK_MBOX_EB] = &mbox_eb.common.hw,1474 [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw,1475 [CLK_AON_APB_DEF_EB] = &aon_apb_def_eb.common.hw,1476 [CLK_CA5_TS0_EB] = &ca5_ts0_eb.common.hw,1477 [CLK_DBG_EB] = &dbg_eb.common.hw,1478 [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw,1479 [CLK_CROSS_TRIG_EB] = &cross_trig_eb.common.hw,1480 [CLK_SERDES_DPHY_EB] = &serdes_dphy_eb.common.hw,1481 [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,1482 [CLK_KPD_RTC_EB] = &kpd_rtc_eb.common.hw,1483 [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,1484 [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,1485 [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,1486 [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,1487 [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,1488 [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,1489 [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,1490 [CLK_CA53_WDG_RTC_EB] = &ca53_wdg_rtc_eb.common.hw,1491 [CLK_THM_RTC_EB] = &thm_rtc_eb.common.hw,1492 [CLK_ATHMA_RTC_EB] = &athma_rtc_eb.common.hw,1493 [CLK_GTHMA_RTC_EB] = >hma_rtc_eb.common.hw,1494 [CLK_ATHMA_RTC_A_EB] = &athma_rtc_a_eb.common.hw,1495 [CLK_GTHMA_RTC_A_EB] = >hma_rtc_a_eb.common.hw,1496 [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,1497 [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,1498 [CLK_DXCO_LC_RTC_EB] = &dxco_lc_rtc_eb.common.hw,1499 [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,1500 [CLK_GNU_EB] = &gpu_eb.common.hw,1501 [CLK_DISP_EB] = &disp_eb.common.hw,1502 [CLK_MM_EMC_EB] = &mm_emc_eb.common.hw,1503 [CLK_POWER_CPU_EB] = &power_cpu_eb.common.hw,1504 [CLK_HW_I2C_EB] = &hw_i2c_eb.common.hw,1505 [CLK_MM_VSP_EMC_EB] = &mm_vsp_emc_eb.common.hw,1506 [CLK_VSP_EB] = &vsp_eb.common.hw,1507 [CLK_CSSYS_EB] = &cssys_eb.common.hw,1508 [CLK_DMC_EB] = &dmc_eb.common.hw,1509 [CLK_ROSC_EB] = &rosc_eb.common.hw,1510 [CLK_S_D_CFG_EB] = &s_d_cfg_eb.common.hw,1511 [CLK_S_D_REF_EB] = &s_d_ref_eb.common.hw,1512 [CLK_B_DMA_EB] = &b_dma_eb.common.hw,1513 [CLK_ANLG_EB] = &anlg_eb.common.hw,1514 [CLK_ANLG_APB_EB] = &anlg_apb_eb.common.hw,1515 [CLK_BSMTMR_EB] = &bsmtmr_eb.common.hw,1516 [CLK_AP_AXI_EB] = &ap_axi_eb.common.hw,1517 [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,1518 [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,1519 [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,1520 [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,1521 [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,1522 [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,1523 [CLK_SCC_EB] = &scc_eb.common.hw,1524 [CLK_DPHY_CFG_EB] = &dphy_cfg_eb.common.hw,1525 [CLK_DPHY_REF_EB] = &dphy_ref_eb.common.hw,1526 [CLK_CPHY_CFG_EB] = &cphy_cfg_eb.common.hw,1527 [CLK_OTG_REF_EB] = &otg_ref_eb.common.hw,1528 [CLK_SERDES_EB] = &serdes_eb.common.hw,1529 [CLK_AON_AP_EMC_EB] = &aon_ap_emc_eb.common.hw,1530 },1531 .num = CLK_AON_APB_GATE_NUM,1532};1533 1534static const struct sprd_clk_desc sc9863a_aonapb_gate_desc = {1535 .clk_clks = sc9863a_aonapb_gate_clks,1536 .num_clk_clks = ARRAY_SIZE(sc9863a_aonapb_gate_clks),1537 .hw_clks = &sc9863a_aonapb_gate_hws,1538};1539 1540/* mm gate clocks */1541static SPRD_SC_GATE_CLK_HW(mahb_ckg_eb, "mahb-ckg-eb", &mm_ahb.common.hw, 0x0, 0x1000,1542 BIT(0), 0, 0);1543static SPRD_SC_GATE_CLK_HW(mdcam_eb, "mdcam-eb", &mm_ahb.common.hw, 0x0, 0x1000,1544 BIT(1), 0, 0);1545static SPRD_SC_GATE_CLK_HW(misp_eb, "misp-eb", &mm_ahb.common.hw, 0x0, 0x1000,1546 BIT(2), 0, 0);1547static SPRD_SC_GATE_CLK_HW(mahbcsi_eb, "mahbcsi-eb", &mm_ahb.common.hw, 0x0, 0x1000,1548 BIT(3), 0, 0);1549static SPRD_SC_GATE_CLK_HW(mcsi_s_eb, "mcsi-s-eb", &mm_ahb.common.hw, 0x0, 0x1000,1550 BIT(4), 0, 0);1551static SPRD_SC_GATE_CLK_HW(mcsi_t_eb, "mcsi-t-eb", &mm_ahb.common.hw, 0x0, 0x1000,1552 BIT(5), 0, 0);1553static SPRD_GATE_CLK_HW(dcam_axi_eb, "dcam-axi-eb", &mm_ahb.common.hw, 0x8,1554 BIT(0), 0, 0);1555static SPRD_GATE_CLK_HW(isp_axi_eb, "isp-axi-eb", &mm_ahb.common.hw, 0x8,1556 BIT(1), 0, 0);1557static SPRD_GATE_CLK_HW(mcsi_eb, "mcsi-eb", &mm_ahb.common.hw, 0x8,1558 BIT(2), 0, 0);1559static SPRD_GATE_CLK_HW(mcsi_s_ckg_eb, "mcsi-s-ckg-eb", &mm_ahb.common.hw, 0x8,1560 BIT(3), 0, 0);1561static SPRD_GATE_CLK_HW(mcsi_t_ckg_eb, "mcsi-t-ckg-eb", &mm_ahb.common.hw, 0x8,1562 BIT(4), 0, 0);1563static SPRD_GATE_CLK_HW(sensor0_eb, "sensor0-eb", &mm_ahb.common.hw, 0x8,1564 BIT(5), 0, 0);1565static SPRD_GATE_CLK_HW(sensor1_eb, "sensor1-eb", &mm_ahb.common.hw, 0x8,1566 BIT(6), 0, 0);1567static SPRD_GATE_CLK_HW(sensor2_eb, "sensor2-eb", &mm_ahb.common.hw, 0x8,1568 BIT(7), 0, 0);1569static SPRD_GATE_CLK_HW(mcphy_cfg_eb, "mcphy-cfg-eb", &mm_ahb.common.hw, 0x8,1570 BIT(8), 0, 0);1571 1572static struct sprd_clk_common *sc9863a_mm_gate_clks[] = {1573 /* address base is 0x60800000 */1574 &mahb_ckg_eb.common,1575 &mdcam_eb.common,1576 &misp_eb.common,1577 &mahbcsi_eb.common,1578 &mcsi_s_eb.common,1579 &mcsi_t_eb.common,1580 &dcam_axi_eb.common,1581 &isp_axi_eb.common,1582 &mcsi_eb.common,1583 &mcsi_s_ckg_eb.common,1584 &mcsi_t_ckg_eb.common,1585 &sensor0_eb.common,1586 &sensor1_eb.common,1587 &sensor2_eb.common,1588 &mcphy_cfg_eb.common,1589};1590 1591static struct clk_hw_onecell_data sc9863a_mm_gate_hws = {1592 .hws = {1593 [CLK_MAHB_CKG_EB] = &mahb_ckg_eb.common.hw,1594 [CLK_MDCAM_EB] = &mdcam_eb.common.hw,1595 [CLK_MISP_EB] = &misp_eb.common.hw,1596 [CLK_MAHBCSI_EB] = &mahbcsi_eb.common.hw,1597 [CLK_MCSI_S_EB] = &mcsi_s_eb.common.hw,1598 [CLK_MCSI_T_EB] = &mcsi_t_eb.common.hw,1599 [CLK_DCAM_AXI_EB] = &dcam_axi_eb.common.hw,1600 [CLK_ISP_AXI_EB] = &isp_axi_eb.common.hw,1601 [CLK_MCSI_EB] = &mcsi_eb.common.hw,1602 [CLK_MCSI_S_CKG_EB] = &mcsi_s_ckg_eb.common.hw,1603 [CLK_MCSI_T_CKG_EB] = &mcsi_t_ckg_eb.common.hw,1604 [CLK_SENSOR0_EB] = &sensor0_eb.common.hw,1605 [CLK_SENSOR1_EB] = &sensor1_eb.common.hw,1606 [CLK_SENSOR2_EB] = &sensor2_eb.common.hw,1607 [CLK_MCPHY_CFG_EB] = &mcphy_cfg_eb.common.hw,1608 },1609 .num = CLK_MM_GATE_NUM,1610};1611 1612static const struct sprd_clk_desc sc9863a_mm_gate_desc = {1613 .clk_clks = sc9863a_mm_gate_clks,1614 .num_clk_clks = ARRAY_SIZE(sc9863a_mm_gate_clks),1615 .hw_clks = &sc9863a_mm_gate_hws,1616};1617 1618/* camera sensor clocks */1619static SPRD_GATE_CLK_HW(mipi_csi_clk, "mipi-csi-clk", &mahb_ckg_eb.common.hw,1620 0x20, BIT(16), 0, SPRD_GATE_NON_AON);1621static SPRD_GATE_CLK_HW(mipi_csi_s_clk, "mipi-csi-s-clk", &mahb_ckg_eb.common.hw,1622 0x24, BIT(16), 0, SPRD_GATE_NON_AON);1623static SPRD_GATE_CLK_HW(mipi_csi_m_clk, "mipi-csi-m-clk", &mahb_ckg_eb.common.hw,1624 0x28, BIT(16), 0, SPRD_GATE_NON_AON);1625 1626static struct sprd_clk_common *sc9863a_mm_clk_clks[] = {1627 /* address base is 0x60900000 */1628 &mipi_csi_clk.common,1629 &mipi_csi_s_clk.common,1630 &mipi_csi_m_clk.common,1631};1632 1633static struct clk_hw_onecell_data sc9863a_mm_clk_hws = {1634 .hws = {1635 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,1636 [CLK_MIPI_CSI_S] = &mipi_csi_s_clk.common.hw,1637 [CLK_MIPI_CSI_M] = &mipi_csi_m_clk.common.hw,1638 },1639 .num = CLK_MM_CLK_NUM,1640};1641 1642static const struct sprd_clk_desc sc9863a_mm_clk_desc = {1643 .clk_clks = sc9863a_mm_clk_clks,1644 .num_clk_clks = ARRAY_SIZE(sc9863a_mm_clk_clks),1645 .hw_clks = &sc9863a_mm_clk_hws,1646};1647 1648static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0,1649 0x1000, BIT(0), 0, 0);1650static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0,1651 0x1000, BIT(1), 0, 0);1652static SPRD_SC_GATE_CLK_FW_NAME(iis1_eb, "iis1-eb", "ext-26m", 0x0,1653 0x1000, BIT(2), 0, 0);1654static SPRD_SC_GATE_CLK_FW_NAME(iis2_eb, "iis2-eb", "ext-26m", 0x0,1655 0x1000, BIT(3), 0, 0);1656static SPRD_SC_GATE_CLK_FW_NAME(spi0_eb, "spi0-eb", "ext-26m", 0x0,1657 0x1000, BIT(5), 0, 0);1658static SPRD_SC_GATE_CLK_FW_NAME(spi1_eb, "spi1-eb", "ext-26m", 0x0,1659 0x1000, BIT(6), 0, 0);1660static SPRD_SC_GATE_CLK_FW_NAME(spi2_eb, "spi2-eb", "ext-26m", 0x0,1661 0x1000, BIT(7), 0, 0);1662static SPRD_SC_GATE_CLK_FW_NAME(i2c0_eb, "i2c0-eb", "ext-26m", 0x0,1663 0x1000, BIT(8), 0, 0);1664static SPRD_SC_GATE_CLK_FW_NAME(i2c1_eb, "i2c1-eb", "ext-26m", 0x0,1665 0x1000, BIT(9), 0, 0);1666static SPRD_SC_GATE_CLK_FW_NAME(i2c2_eb, "i2c2-eb", "ext-26m", 0x0,1667 0x1000, BIT(10), 0, 0);1668static SPRD_SC_GATE_CLK_FW_NAME(i2c3_eb, "i2c3-eb", "ext-26m", 0x0,1669 0x1000, BIT(11), 0, 0);1670static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m", 0x0,1671 0x1000, BIT(12), 0, 0);1672static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m", 0x0,1673 0x1000, BIT(13), 0, 0);1674/* uart1_eb is for console, don't gate even if unused */1675static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m", 0x0,1676 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);1677static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m", 0x0,1678 0x1000, BIT(15), 0, 0);1679static SPRD_SC_GATE_CLK_FW_NAME(uart3_eb, "uart3-eb", "ext-26m", 0x0,1680 0x1000, BIT(16), 0, 0);1681static SPRD_SC_GATE_CLK_FW_NAME(uart4_eb, "uart4-eb", "ext-26m", 0x0,1682 0x1000, BIT(17), 0, 0);1683static SPRD_SC_GATE_CLK_FW_NAME(sim0_32k_eb, "sim0_32k-eb", "ext-26m", 0x0,1684 0x1000, BIT(18), 0, 0);1685static SPRD_SC_GATE_CLK_FW_NAME(spi3_eb, "spi3-eb", "ext-26m", 0x0,1686 0x1000, BIT(19), 0, 0);1687static SPRD_SC_GATE_CLK_FW_NAME(i2c5_eb, "i2c5-eb", "ext-26m", 0x0,1688 0x1000, BIT(20), 0, 0);1689static SPRD_SC_GATE_CLK_FW_NAME(i2c6_eb, "i2c6-eb", "ext-26m", 0x0,1690 0x1000, BIT(21), 0, 0);1691 1692static struct sprd_clk_common *sc9863a_apapb_gate[] = {1693 /* address base is 0x71300000 */1694 &sim0_eb.common,1695 &iis0_eb.common,1696 &iis1_eb.common,1697 &iis2_eb.common,1698 &spi0_eb.common,1699 &spi1_eb.common,1700 &spi2_eb.common,1701 &i2c0_eb.common,1702 &i2c1_eb.common,1703 &i2c2_eb.common,1704 &i2c3_eb.common,1705 &i2c4_eb.common,1706 &uart0_eb.common,1707 &uart1_eb.common,1708 &uart2_eb.common,1709 &uart3_eb.common,1710 &uart4_eb.common,1711 &sim0_32k_eb.common,1712 &spi3_eb.common,1713 &i2c5_eb.common,1714 &i2c6_eb.common,1715};1716 1717static struct clk_hw_onecell_data sc9863a_apapb_gate_hws = {1718 .hws = {1719 [CLK_SIM0_EB] = &sim0_eb.common.hw,1720 [CLK_IIS0_EB] = &iis0_eb.common.hw,1721 [CLK_IIS1_EB] = &iis1_eb.common.hw,1722 [CLK_IIS2_EB] = &iis2_eb.common.hw,1723 [CLK_SPI0_EB] = &spi0_eb.common.hw,1724 [CLK_SPI1_EB] = &spi1_eb.common.hw,1725 [CLK_SPI2_EB] = &spi2_eb.common.hw,1726 [CLK_I2C0_EB] = &i2c0_eb.common.hw,1727 [CLK_I2C1_EB] = &i2c1_eb.common.hw,1728 [CLK_I2C2_EB] = &i2c2_eb.common.hw,1729 [CLK_I2C3_EB] = &i2c3_eb.common.hw,1730 [CLK_I2C4_EB] = &i2c4_eb.common.hw,1731 [CLK_UART0_EB] = &uart0_eb.common.hw,1732 [CLK_UART1_EB] = &uart1_eb.common.hw,1733 [CLK_UART2_EB] = &uart2_eb.common.hw,1734 [CLK_UART3_EB] = &uart3_eb.common.hw,1735 [CLK_UART4_EB] = &uart4_eb.common.hw,1736 [CLK_SIM0_32K_EB] = &sim0_32k_eb.common.hw,1737 [CLK_SPI3_EB] = &spi3_eb.common.hw,1738 [CLK_I2C5_EB] = &i2c5_eb.common.hw,1739 [CLK_I2C6_EB] = &i2c6_eb.common.hw,1740 },1741 .num = CLK_AP_APB_GATE_NUM,1742};1743 1744static const struct sprd_clk_desc sc9863a_apapb_gate_desc = {1745 .clk_clks = sc9863a_apapb_gate,1746 .num_clk_clks = ARRAY_SIZE(sc9863a_apapb_gate),1747 .hw_clks = &sc9863a_apapb_gate_hws,1748};1749 1750static const struct of_device_id sprd_sc9863a_clk_ids[] = {1751 { .compatible = "sprd,sc9863a-ap-clk", /* 0x21500000 */1752 .data = &sc9863a_ap_clk_desc },1753 { .compatible = "sprd,sc9863a-pmu-gate", /* 0x402b0000 */1754 .data = &sc9863a_pmu_gate_desc },1755 { .compatible = "sprd,sc9863a-pll", /* 0x40353000 */1756 .data = &sc9863a_pll_desc },1757 { .compatible = "sprd,sc9863a-mpll", /* 0x40359000 */1758 .data = &sc9863a_mpll_desc },1759 { .compatible = "sprd,sc9863a-rpll", /* 0x4035c000 */1760 .data = &sc9863a_rpll_desc },1761 { .compatible = "sprd,sc9863a-dpll", /* 0x40363000 */1762 .data = &sc9863a_dpll_desc },1763 { .compatible = "sprd,sc9863a-aon-clk", /* 0x402d0000 */1764 .data = &sc9863a_aon_clk_desc },1765 { .compatible = "sprd,sc9863a-apahb-gate", /* 0x20e00000 */1766 .data = &sc9863a_apahb_gate_desc },1767 { .compatible = "sprd,sc9863a-aonapb-gate", /* 0x402e0000 */1768 .data = &sc9863a_aonapb_gate_desc },1769 { .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */1770 .data = &sc9863a_mm_gate_desc },1771 { .compatible = "sprd,sc9863a-mm-clk", /* 0x60900000 */1772 .data = &sc9863a_mm_clk_desc },1773 { .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */1774 .data = &sc9863a_apapb_gate_desc },1775 { }1776};1777MODULE_DEVICE_TABLE(of, sprd_sc9863a_clk_ids);1778 1779static int sc9863a_clk_probe(struct platform_device *pdev)1780{1781 const struct sprd_clk_desc *desc;1782 int ret;1783 1784 desc = device_get_match_data(&pdev->dev);1785 if (!desc)1786 return -ENODEV;1787 1788 ret = sprd_clk_regmap_init(pdev, desc);1789 if (ret)1790 return ret;1791 1792 return sprd_clk_probe(&pdev->dev, desc->hw_clks);1793}1794 1795static struct platform_driver sc9863a_clk_driver = {1796 .probe = sc9863a_clk_probe,1797 .driver = {1798 .name = "sc9863a-clk",1799 .of_match_table = sprd_sc9863a_clk_ids,1800 },1801};1802module_platform_driver(sc9863a_clk_driver);1803 1804MODULE_DESCRIPTION("Spreadtrum SC9863A Clock Driver");1805MODULE_LICENSE("GPL v2");1806