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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.5 */6 7#include <linux/clk.h>8#include <linux/delay.h>9#include <linux/device.h>10#include <linux/err.h>11#include <linux/io.h>12#include <linux/of.h>13#include <linux/of_address.h>14#include <linux/slab.h>15#include <linux/spinlock.h>16 17#include "clk-stm32-core.h"18#include "reset-stm32.h"19 20static DEFINE_SPINLOCK(rlock);21 22static int stm32_rcc_clock_init(struct device *dev,23 const struct of_device_id *match,24 void __iomem *base)25{26 const struct stm32_rcc_match_data *data = match->data;27 struct clk_hw_onecell_data *clk_data = data->hw_clks;28 struct clk_hw **hws;29 int n, max_binding;30 31 max_binding = data->maxbinding;32 33 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);34 if (!clk_data)35 return -ENOMEM;36 37 clk_data->num = max_binding;38 39 hws = clk_data->hws;40 41 for (n = 0; n < max_binding; n++)42 hws[n] = ERR_PTR(-ENOENT);43 44 for (n = 0; n < data->num_clocks; n++) {45 const struct clock_config *cfg_clock = &data->tab_clocks[n];46 struct clk_hw *hw = ERR_PTR(-ENOENT);47 48 if (data->check_security &&49 data->check_security(dev->of_node, base, cfg_clock))50 continue;51 52 if (cfg_clock->func)53 hw = (*cfg_clock->func)(dev, data, base, &rlock,54 cfg_clock);55 56 if (IS_ERR(hw)) {57 dev_err(dev, "Can't register clk %d: %ld\n", n,58 PTR_ERR(hw));59 return PTR_ERR(hw);60 }61 62 if (cfg_clock->id != NO_ID)63 hws[cfg_clock->id] = hw;64 }65 66 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);67}68 69int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,70 void __iomem *base)71{72 const struct stm32_rcc_match_data *rcc_match_data;73 const struct of_device_id *match;74 int err;75 76 match = of_match_node(match_data, dev_of_node(dev));77 if (!match) {78 dev_err(dev, "match data not found\n");79 return -ENODEV;80 }81 82 rcc_match_data = match->data;83 84 /* RCC Reset Configuration */85 err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base);86 if (err) {87 pr_err("stm32 reset failed to initialize\n");88 return err;89 }90 91 /* RCC Clock Configuration */92 err = stm32_rcc_clock_init(dev, match, base);93 if (err) {94 pr_err("stm32 clock failed to initialize\n");95 return err;96 }97 98 return 0;99}100 101static u8 stm32_mux_get_parent(void __iomem *base,102 struct clk_stm32_clock_data *data,103 u16 mux_id)104{105 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];106 u32 mask = BIT(mux->width) - 1;107 u32 val;108 109 val = readl(base + mux->offset) >> mux->shift;110 val &= mask;111 112 return val;113}114 115static int stm32_mux_set_parent(void __iomem *base,116 struct clk_stm32_clock_data *data,117 u16 mux_id, u8 index)118{119 const struct stm32_mux_cfg *mux = &data->muxes[mux_id];120 121 u32 mask = BIT(mux->width) - 1;122 u32 reg = readl(base + mux->offset);123 u32 val = index << mux->shift;124 125 reg &= ~(mask << mux->shift);126 reg |= val;127 128 writel(reg, base + mux->offset);129 130 return 0;131}132 133static void stm32_gate_endisable(void __iomem *base,134 struct clk_stm32_clock_data *data,135 u16 gate_id, int enable)136{137 const struct stm32_gate_cfg *gate = &data->gates[gate_id];138 void __iomem *addr = base + gate->offset;139 140 if (enable) {141 if (data->gate_cpt[gate_id]++ > 0)142 return;143 144 if (gate->set_clr != 0)145 writel(BIT(gate->bit_idx), addr);146 else147 writel(readl(addr) | BIT(gate->bit_idx), addr);148 } else {149 if (--data->gate_cpt[gate_id] > 0)150 return;151 152 if (gate->set_clr != 0)153 writel(BIT(gate->bit_idx), addr + gate->set_clr);154 else155 writel(readl(addr) & ~BIT(gate->bit_idx), addr);156 }157}158 159static void stm32_gate_disable_unused(void __iomem *base,160 struct clk_stm32_clock_data *data,161 u16 gate_id)162{163 const struct stm32_gate_cfg *gate = &data->gates[gate_id];164 void __iomem *addr = base + gate->offset;165 166 if (data->gate_cpt[gate_id] > 0)167 return;168 169 if (gate->set_clr != 0)170 writel(BIT(gate->bit_idx), addr + gate->set_clr);171 else172 writel(readl(addr) & ~BIT(gate->bit_idx), addr);173}174 175static int stm32_gate_is_enabled(void __iomem *base,176 struct clk_stm32_clock_data *data,177 u16 gate_id)178{179 const struct stm32_gate_cfg *gate = &data->gates[gate_id];180 181 return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;182}183 184static unsigned int _get_table_div(const struct clk_div_table *table,185 unsigned int val)186{187 const struct clk_div_table *clkt;188 189 for (clkt = table; clkt->div; clkt++)190 if (clkt->val == val)191 return clkt->div;192 return 0;193}194 195static unsigned int _get_div(const struct clk_div_table *table,196 unsigned int val, unsigned long flags, u8 width)197{198 if (flags & CLK_DIVIDER_ONE_BASED)199 return val;200 if (flags & CLK_DIVIDER_POWER_OF_TWO)201 return 1 << val;202 if (table)203 return _get_table_div(table, val);204 return val + 1;205}206 207static unsigned long stm32_divider_get_rate(void __iomem *base,208 struct clk_stm32_clock_data *data,209 u16 div_id,210 unsigned long parent_rate)211{212 const struct stm32_div_cfg *divider = &data->dividers[div_id];213 unsigned int val;214 unsigned int div;215 216 val = readl(base + divider->offset) >> divider->shift;217 val &= clk_div_mask(divider->width);218 div = _get_div(divider->table, val, divider->flags, divider->width);219 220 if (!div) {221 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),222 "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",223 div_id);224 return parent_rate;225 }226 227 return DIV_ROUND_UP_ULL((u64)parent_rate, div);228}229 230static int stm32_divider_set_rate(void __iomem *base,231 struct clk_stm32_clock_data *data,232 u16 div_id, unsigned long rate,233 unsigned long parent_rate)234{235 const struct stm32_div_cfg *divider = &data->dividers[div_id];236 int value;237 u32 val;238 239 value = divider_get_val(rate, parent_rate, divider->table,240 divider->width, divider->flags);241 if (value < 0)242 return value;243 244 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {245 val = clk_div_mask(divider->width) << (divider->shift + 16);246 } else {247 val = readl(base + divider->offset);248 val &= ~(clk_div_mask(divider->width) << divider->shift);249 }250 251 val |= (u32)value << divider->shift;252 253 writel(val, base + divider->offset);254 255 return 0;256}257 258static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)259{260 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);261 262 return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);263}264 265static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)266{267 struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);268 unsigned long flags = 0;269 270 spin_lock_irqsave(mux->lock, flags);271 272 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);273 274 spin_unlock_irqrestore(mux->lock, flags);275 276 return 0;277}278 279const struct clk_ops clk_stm32_mux_ops = {280 .determine_rate = __clk_mux_determine_rate,281 .get_parent = clk_stm32_mux_get_parent,282 .set_parent = clk_stm32_mux_set_parent,283};284 285static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)286{287 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);288 unsigned long flags = 0;289 290 spin_lock_irqsave(gate->lock, flags);291 292 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);293 294 spin_unlock_irqrestore(gate->lock, flags);295}296 297static int clk_stm32_gate_enable(struct clk_hw *hw)298{299 clk_stm32_gate_endisable(hw, 1);300 301 return 0;302}303 304static void clk_stm32_gate_disable(struct clk_hw *hw)305{306 clk_stm32_gate_endisable(hw, 0);307}308 309static int clk_stm32_gate_is_enabled(struct clk_hw *hw)310{311 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);312 313 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);314}315 316static void clk_stm32_gate_disable_unused(struct clk_hw *hw)317{318 struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);319 unsigned long flags = 0;320 321 spin_lock_irqsave(gate->lock, flags);322 323 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);324 325 spin_unlock_irqrestore(gate->lock, flags);326}327 328const struct clk_ops clk_stm32_gate_ops = {329 .enable = clk_stm32_gate_enable,330 .disable = clk_stm32_gate_disable,331 .is_enabled = clk_stm32_gate_is_enabled,332 .disable_unused = clk_stm32_gate_disable_unused,333};334 335static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,336 unsigned long parent_rate)337{338 struct clk_stm32_div *div = to_clk_stm32_divider(hw);339 unsigned long flags = 0;340 int ret;341 342 if (div->div_id == NO_STM32_DIV)343 return rate;344 345 spin_lock_irqsave(div->lock, flags);346 347 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);348 349 spin_unlock_irqrestore(div->lock, flags);350 351 return ret;352}353 354static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,355 unsigned long *prate)356{357 struct clk_stm32_div *div = to_clk_stm32_divider(hw);358 const struct stm32_div_cfg *divider;359 360 if (div->div_id == NO_STM32_DIV)361 return rate;362 363 divider = &div->clock_data->dividers[div->div_id];364 365 /* if read only, just return current value */366 if (divider->flags & CLK_DIVIDER_READ_ONLY) {367 u32 val;368 369 val = readl(div->base + divider->offset) >> divider->shift;370 val &= clk_div_mask(divider->width);371 372 return divider_ro_round_rate(hw, rate, prate, divider->table,373 divider->width, divider->flags,374 val);375 }376 377 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),378 rate, prate, divider->table,379 divider->width, divider->flags);380}381 382static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,383 unsigned long parent_rate)384{385 struct clk_stm32_div *div = to_clk_stm32_divider(hw);386 387 if (div->div_id == NO_STM32_DIV)388 return parent_rate;389 390 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);391}392 393const struct clk_ops clk_stm32_divider_ops = {394 .recalc_rate = clk_stm32_divider_recalc_rate,395 .round_rate = clk_stm32_divider_round_rate,396 .set_rate = clk_stm32_divider_set_rate,397};398 399static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,400 unsigned long parent_rate)401{402 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);403 unsigned long flags = 0;404 int ret;405 406 if (composite->div_id == NO_STM32_DIV)407 return rate;408 409 spin_lock_irqsave(composite->lock, flags);410 411 ret = stm32_divider_set_rate(composite->base, composite->clock_data,412 composite->div_id, rate, parent_rate);413 414 spin_unlock_irqrestore(composite->lock, flags);415 416 return ret;417}418 419static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,420 unsigned long parent_rate)421{422 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);423 424 if (composite->div_id == NO_STM32_DIV)425 return parent_rate;426 427 return stm32_divider_get_rate(composite->base, composite->clock_data,428 composite->div_id, parent_rate);429}430 431static int clk_stm32_composite_determine_rate(struct clk_hw *hw,432 struct clk_rate_request *req)433{434 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);435 const struct stm32_div_cfg *divider;436 long rate;437 438 if (composite->div_id == NO_STM32_DIV)439 return 0;440 441 divider = &composite->clock_data->dividers[composite->div_id];442 443 /* if read only, just return current value */444 if (divider->flags & CLK_DIVIDER_READ_ONLY) {445 u32 val;446 447 val = readl(composite->base + divider->offset) >> divider->shift;448 val &= clk_div_mask(divider->width);449 450 rate = divider_ro_round_rate(hw, req->rate, &req->best_parent_rate,451 divider->table, divider->width, divider->flags,452 val);453 if (rate < 0)454 return rate;455 456 req->rate = rate;457 return 0;458 }459 460 rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),461 req->rate, &req->best_parent_rate,462 divider->table, divider->width, divider->flags);463 if (rate < 0)464 return rate;465 466 req->rate = rate;467 return 0;468}469 470static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)471{472 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);473 474 return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);475}476 477static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)478{479 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);480 unsigned long flags = 0;481 482 spin_lock_irqsave(composite->lock, flags);483 484 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);485 486 spin_unlock_irqrestore(composite->lock, flags);487 488 if (composite->clock_data->is_multi_mux) {489 struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);490 491 if (other_mux_hw) {492 struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);493 494 clk_hw_reparent(other_mux_hw, hwp);495 }496 }497 498 return 0;499}500 501static int clk_stm32_composite_is_enabled(struct clk_hw *hw)502{503 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);504 505 if (composite->gate_id == NO_STM32_GATE)506 return (__clk_get_enable_count(hw->clk) > 0);507 508 return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);509}510 511#define MUX_SAFE_POSITION 0512 513static int clk_stm32_has_safe_mux(struct clk_hw *hw)514{515 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);516 const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];517 518 return !!(mux->flags & MUX_SAFE);519}520 521static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)522{523 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);524 525 if (!clk_stm32_composite_is_enabled(hw)) {526 unsigned long flags = 0;527 528 if (composite->clock_data->is_multi_mux) {529 struct clk_hw *other_mux_hw = NULL;530 531 other_mux_hw = composite->clock_data->is_multi_mux(hw);532 533 if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))534 return;535 }536 537 spin_lock_irqsave(composite->lock, flags);538 539 stm32_mux_set_parent(composite->base, composite->clock_data,540 composite->mux_id, MUX_SAFE_POSITION);541 542 spin_unlock_irqrestore(composite->lock, flags);543 }544}545 546static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)547{548 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);549 int sel = clk_hw_get_parent_index(hw);550 unsigned long flags = 0;551 552 spin_lock_irqsave(composite->lock, flags);553 554 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);555 556 spin_unlock_irqrestore(composite->lock, flags);557}558 559static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)560{561 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);562 unsigned long flags = 0;563 564 spin_lock_irqsave(composite->lock, flags);565 566 stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);567 568 spin_unlock_irqrestore(composite->lock, flags);569}570 571static int clk_stm32_composite_gate_enable(struct clk_hw *hw)572{573 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);574 575 if (composite->gate_id == NO_STM32_GATE)576 return 0;577 578 clk_stm32_composite_gate_endisable(hw, 1);579 580 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))581 clk_stm32_safe_restore_position_mux(hw);582 583 return 0;584}585 586static void clk_stm32_composite_gate_disable(struct clk_hw *hw)587{588 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);589 590 if (composite->gate_id == NO_STM32_GATE)591 return;592 593 clk_stm32_composite_gate_endisable(hw, 0);594 595 if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))596 clk_stm32_set_safe_position_mux(hw);597}598 599static void clk_stm32_composite_disable_unused(struct clk_hw *hw)600{601 struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);602 unsigned long flags = 0;603 604 if (composite->gate_id == NO_STM32_GATE)605 return;606 607 spin_lock_irqsave(composite->lock, flags);608 609 stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);610 611 spin_unlock_irqrestore(composite->lock, flags);612}613 614const struct clk_ops clk_stm32_composite_ops = {615 .set_rate = clk_stm32_composite_set_rate,616 .recalc_rate = clk_stm32_composite_recalc_rate,617 .determine_rate = clk_stm32_composite_determine_rate,618 .get_parent = clk_stm32_composite_get_parent,619 .set_parent = clk_stm32_composite_set_parent,620 .enable = clk_stm32_composite_gate_enable,621 .disable = clk_stm32_composite_gate_disable,622 .is_enabled = clk_stm32_composite_is_enabled,623 .disable_unused = clk_stm32_composite_disable_unused,624};625 626struct clk_hw *clk_stm32_mux_register(struct device *dev,627 const struct stm32_rcc_match_data *data,628 void __iomem *base,629 spinlock_t *lock,630 const struct clock_config *cfg)631{632 struct clk_stm32_mux *mux = cfg->clock_cfg;633 struct clk_hw *hw = &mux->hw;634 int err;635 636 mux->base = base;637 mux->lock = lock;638 mux->clock_data = data->clock_data;639 640 err = devm_clk_hw_register(dev, hw);641 if (err)642 return ERR_PTR(err);643 644 return hw;645}646 647struct clk_hw *clk_stm32_gate_register(struct device *dev,648 const struct stm32_rcc_match_data *data,649 void __iomem *base,650 spinlock_t *lock,651 const struct clock_config *cfg)652{653 struct clk_stm32_gate *gate = cfg->clock_cfg;654 struct clk_hw *hw = &gate->hw;655 int err;656 657 gate->base = base;658 gate->lock = lock;659 gate->clock_data = data->clock_data;660 661 err = devm_clk_hw_register(dev, hw);662 if (err)663 return ERR_PTR(err);664 665 return hw;666}667 668struct clk_hw *clk_stm32_div_register(struct device *dev,669 const struct stm32_rcc_match_data *data,670 void __iomem *base,671 spinlock_t *lock,672 const struct clock_config *cfg)673{674 struct clk_stm32_div *div = cfg->clock_cfg;675 struct clk_hw *hw = &div->hw;676 int err;677 678 div->base = base;679 div->lock = lock;680 div->clock_data = data->clock_data;681 682 err = devm_clk_hw_register(dev, hw);683 if (err)684 return ERR_PTR(err);685 686 return hw;687}688 689struct clk_hw *clk_stm32_composite_register(struct device *dev,690 const struct stm32_rcc_match_data *data,691 void __iomem *base,692 spinlock_t *lock,693 const struct clock_config *cfg)694{695 struct clk_stm32_composite *composite = cfg->clock_cfg;696 struct clk_hw *hw = &composite->hw;697 int err;698 699 composite->base = base;700 composite->lock = lock;701 composite->clock_data = data->clock_data;702 703 err = devm_clk_hw_register(dev, hw);704 if (err)705 return ERR_PTR(err);706 707 return hw;708}709