2002 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.5 */6 7#include <linux/bus/stm32_firewall_device.h>8#include <linux/clk-provider.h>9#include <linux/io.h>10#include <linux/platform_device.h>11 12#include "clk-stm32-core.h"13#include "reset-stm32.h"14#include "stm32mp25_rcc.h"15 16#include <dt-bindings/clock/st,stm32mp25-rcc.h>17#include <dt-bindings/reset/st,stm32mp25-rcc.h>18 19/* Clock security definition */20#define SECF_NONE -121 22#define RCC_REG_SIZE 3223#define RCC_SECCFGR(x) (((x) / RCC_REG_SIZE) * 0x4 + RCC_SECCFGR0)24#define RCC_CIDCFGR(x) ((x) * 0x8 + RCC_R0CIDCFGR)25#define RCC_SEMCR(x) ((x) * 0x8 + RCC_R0SEMCR)26#define RCC_CID1 127 28/* Register: RIFSC_CIDCFGR */29#define RCC_CIDCFGR_CFEN BIT(0)30#define RCC_CIDCFGR_SEM_EN BIT(1)31#define RCC_CIDCFGR_SEMWLC1_EN BIT(17)32#define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4)33 34/* Register: RIFSC_SEMCR */35#define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4)36 37#define MP25_RIF_RCC_IS2M 10738#define MP25_RIF_RCC_MCO1 10839#define MP25_RIF_RCC_MCO2 10940 41#define SEC_RIFSC_FLAG BIT(31)42#define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG)43 44enum {45 HSE,46 HSI,47 MSI,48 LSE,49 LSI,50 HSE_DIV2,51 ICN_HS_MCU,52 ICN_LS_MCU,53 ICN_SDMMC,54 ICN_DDR,55 ICN_DISPLAY,56 ICN_HSL,57 ICN_NIC,58 ICN_VID,59 FLEXGEN_07,60 FLEXGEN_08,61 FLEXGEN_09,62 FLEXGEN_10,63 FLEXGEN_11,64 FLEXGEN_12,65 FLEXGEN_13,66 FLEXGEN_14,67 FLEXGEN_15,68 FLEXGEN_16,69 FLEXGEN_17,70 FLEXGEN_18,71 FLEXGEN_19,72 FLEXGEN_20,73 FLEXGEN_21,74 FLEXGEN_22,75 FLEXGEN_23,76 FLEXGEN_24,77 FLEXGEN_25,78 FLEXGEN_26,79 FLEXGEN_27,80 FLEXGEN_28,81 FLEXGEN_29,82 FLEXGEN_30,83 FLEXGEN_31,84 FLEXGEN_32,85 FLEXGEN_33,86 FLEXGEN_34,87 FLEXGEN_35,88 FLEXGEN_36,89 FLEXGEN_37,90 FLEXGEN_38,91 FLEXGEN_39,92 FLEXGEN_40,93 FLEXGEN_41,94 FLEXGEN_42,95 FLEXGEN_43,96 FLEXGEN_44,97 FLEXGEN_45,98 FLEXGEN_46,99 FLEXGEN_47,100 FLEXGEN_48,101 FLEXGEN_49,102 FLEXGEN_50,103 FLEXGEN_51,104 FLEXGEN_52,105 FLEXGEN_53,106 FLEXGEN_54,107 FLEXGEN_55,108 FLEXGEN_56,109 FLEXGEN_57,110 FLEXGEN_58,111 FLEXGEN_59,112 FLEXGEN_60,113 FLEXGEN_61,114 FLEXGEN_62,115 FLEXGEN_63,116 ICN_APB1,117 ICN_APB2,118 ICN_APB3,119 ICN_APB4,120 ICN_APBDBG,121 TIMG1,122 TIMG2,123 PLL3,124 DSI_TXBYTE,125};126 127static const struct clk_parent_data adc12_src[] = {128 { .index = FLEXGEN_46 },129 { .index = ICN_LS_MCU },130};131 132static const struct clk_parent_data adc3_src[] = {133 { .index = FLEXGEN_47 },134 { .index = ICN_LS_MCU },135 { .index = FLEXGEN_46 },136};137 138static const struct clk_parent_data usb2phy1_src[] = {139 { .index = FLEXGEN_57 },140 { .index = HSE_DIV2 },141};142 143static const struct clk_parent_data usb2phy2_src[] = {144 { .index = FLEXGEN_58 },145 { .index = HSE_DIV2 },146};147 148static const struct clk_parent_data usb3pciphy_src[] = {149 { .index = FLEXGEN_34 },150 { .index = HSE_DIV2 },151};152 153static struct clk_stm32_gate ck_ker_ltdc;154 155static const struct clk_parent_data dsiblane_src[] = {156 { .index = DSI_TXBYTE },157 { .hw = &ck_ker_ltdc.hw },158};159 160static const struct clk_parent_data dsiphy_src[] = {161 { .index = FLEXGEN_28 },162 { .index = HSE },163};164 165static const struct clk_parent_data lvdsphy_src[] = {166 { .index = FLEXGEN_32 },167 { .index = HSE },168};169 170static const struct clk_parent_data dts_src[] = {171 { .index = HSI },172 { .index = HSE },173 { .index = MSI },174};175 176static const struct clk_parent_data mco1_src[] = {177 { .index = FLEXGEN_61 },178};179 180static const struct clk_parent_data mco2_src[] = {181 { .index = FLEXGEN_62 },182};183 184enum enum_mux_cfg {185 MUX_ADC12,186 MUX_ADC3,187 MUX_DSIBLANE,188 MUX_DSIPHY,189 MUX_DTS,190 MUX_LVDSPHY,191 MUX_MCO1,192 MUX_MCO2,193 MUX_USB2PHY1,194 MUX_USB2PHY2,195 MUX_USB3PCIEPHY,196 MUX_NB197};198 199#define MUX_CFG(id, _offset, _shift, _witdh) \200 [id] = { \201 .offset = (_offset), \202 .shift = (_shift), \203 .width = (_witdh), \204 }205 206static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = {207 MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1),208 MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2),209 MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1),210 MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1),211 MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2),212 MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1),213 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1),214 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1),215 MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1),216 MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1),217 MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1),218};219 220enum enum_gate_cfg {221 GATE_ADC12,222 GATE_ADC3,223 GATE_ADF1,224 GATE_CCI,225 GATE_CRC,226 GATE_CRYP1,227 GATE_CRYP2,228 GATE_CSI,229 GATE_DCMIPP,230 GATE_DSI,231 GATE_DTS,232 GATE_ETH1,233 GATE_ETH1MAC,234 GATE_ETH1RX,235 GATE_ETH1STP,236 GATE_ETH1TX,237 GATE_ETH2,238 GATE_ETH2MAC,239 GATE_ETH2RX,240 GATE_ETH2STP,241 GATE_ETH2TX,242 GATE_ETHSW,243 GATE_ETHSWACMCFG,244 GATE_ETHSWACMMSG,245 GATE_ETHSWMAC,246 GATE_ETHSWREF,247 GATE_FDCAN,248 GATE_GPU,249 GATE_HASH,250 GATE_HDP,251 GATE_I2C1,252 GATE_I2C2,253 GATE_I2C3,254 GATE_I2C4,255 GATE_I2C5,256 GATE_I2C6,257 GATE_I2C7,258 GATE_I2C8,259 GATE_I3C1,260 GATE_I3C2,261 GATE_I3C3,262 GATE_I3C4,263 GATE_IS2M,264 GATE_IWDG1,265 GATE_IWDG2,266 GATE_IWDG3,267 GATE_IWDG4,268 GATE_IWDG5,269 GATE_LPTIM1,270 GATE_LPTIM2,271 GATE_LPTIM3,272 GATE_LPTIM4,273 GATE_LPTIM5,274 GATE_LPUART1,275 GATE_LTDC,276 GATE_LVDS,277 GATE_MCO1,278 GATE_MCO2,279 GATE_MDF1,280 GATE_OSPIIOM,281 GATE_PCIE,282 GATE_PKA,283 GATE_RNG,284 GATE_SAES,285 GATE_SAI1,286 GATE_SAI2,287 GATE_SAI3,288 GATE_SAI4,289 GATE_SDMMC1,290 GATE_SDMMC2,291 GATE_SDMMC3,292 GATE_SERC,293 GATE_SPDIFRX,294 GATE_SPI1,295 GATE_SPI2,296 GATE_SPI3,297 GATE_SPI4,298 GATE_SPI5,299 GATE_SPI6,300 GATE_SPI7,301 GATE_SPI8,302 GATE_TIM1,303 GATE_TIM10,304 GATE_TIM11,305 GATE_TIM12,306 GATE_TIM13,307 GATE_TIM14,308 GATE_TIM15,309 GATE_TIM16,310 GATE_TIM17,311 GATE_TIM2,312 GATE_TIM20,313 GATE_TIM3,314 GATE_TIM4,315 GATE_TIM5,316 GATE_TIM6,317 GATE_TIM7,318 GATE_TIM8,319 GATE_UART4,320 GATE_UART5,321 GATE_UART7,322 GATE_UART8,323 GATE_UART9,324 GATE_USART1,325 GATE_USART2,326 GATE_USART3,327 GATE_USART6,328 GATE_USBH,329 GATE_USB2PHY1,330 GATE_USB2PHY2,331 GATE_USB3DR,332 GATE_USB3PCIEPHY,333 GATE_USBTC,334 GATE_VDEC,335 GATE_VENC,336 GATE_VREF,337 GATE_WWDG1,338 GATE_WWDG2,339 GATE_NB340};341 342#define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \343 [id] = { \344 .offset = (_offset), \345 .bit_idx = (_bit_idx), \346 .set_clr = (_offset_clr), \347 }348 349static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = {350 GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0),351 GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0),352 GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0),353 GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0),354 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),355 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),356 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),357 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),358 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),359 GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0),360 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),361 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),362 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),363 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),364 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),365 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),366 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),367 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),368 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),369 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),370 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),371 GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0),372 GATE_CFG(GATE_ETHSWACMCFG, RCC_ETHSWACMCFGR, 1, 0),373 GATE_CFG(GATE_ETHSWACMMSG, RCC_ETHSWACMMSGCFGR, 1, 0),374 GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0),375 GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0),376 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),377 GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0),378 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),379 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),380 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),381 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),382 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),383 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),384 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),385 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),386 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),387 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),388 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),389 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),390 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),391 GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0),392 GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0),393 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),394 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),395 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),396 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),397 GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0),398 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),399 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),400 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),401 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),402 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),403 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),404 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),405 GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0),406 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),407 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),408 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),409 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),410 GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0),411 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),412 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),413 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),414 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),415 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),416 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),417 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),418 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),419 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),420 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),421 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),422 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),423 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),424 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),425 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),426 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),427 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),428 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),429 GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0),430 GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0),431 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),432 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),433 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),434 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),435 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),436 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),437 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),438 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),439 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),440 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),441 GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0),442 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),443 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),444 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),445 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),446 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),447 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),448 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),449 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),450 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),451 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),452 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),453 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),454 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),455 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),456 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),457 GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0),458 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),459 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),460 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),461 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),462 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),463 GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0),464 GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0),465 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),466 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),467 GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0),468};469 470#define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags) \471 (&(struct clk_init_data) { \472 .flags = _flags, \473 .name = _name, \474 .parent_data = (const struct clk_parent_data[]) { \475 { .index = _parent }, \476 }, \477 .num_parents = 1, \478 .ops = _ops, \479 })480 481/* ADC */482static struct clk_stm32_gate ck_icn_p_adc12 = {483 .gate_id = GATE_ADC12,484 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc12", ICN_LS_MCU, &clk_stm32_gate_ops, 0),485};486 487static struct clk_stm32_composite ck_ker_adc12 = {488 .gate_id = GATE_ADC12,489 .mux_id = MUX_ADC12,490 .div_id = NO_STM32_DIV,491 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc12", adc12_src, &clk_stm32_composite_ops, 0),492};493 494static struct clk_stm32_gate ck_icn_p_adc3 = {495 .gate_id = GATE_ADC3,496 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),497};498 499static struct clk_stm32_composite ck_ker_adc3 = {500 .gate_id = GATE_ADC3,501 .mux_id = MUX_ADC3,502 .div_id = NO_STM32_DIV,503 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc3", adc3_src, &clk_stm32_composite_ops, 0),504};505 506/* ADF */507static struct clk_stm32_gate ck_icn_p_adf1 = {508 .gate_id = GATE_ADF1,509 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),510};511 512static struct clk_stm32_gate ck_ker_adf1 = {513 .gate_id = GATE_ADF1,514 .hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),515};516 517/* DCMI */518static struct clk_stm32_gate ck_icn_p_cci = {519 .gate_id = GATE_CCI,520 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cci", ICN_LS_MCU, &clk_stm32_gate_ops, 0),521};522 523/* CSI-HOST */524static struct clk_stm32_gate ck_icn_p_csi = {525 .gate_id = GATE_CSI,526 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0),527};528 529static struct clk_stm32_gate ck_ker_csi = {530 .gate_id = GATE_CSI,531 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0),532};533 534static struct clk_stm32_gate ck_ker_csitxesc = {535 .gate_id = GATE_CSI,536 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0),537};538 539/* CSI-PHY */540static struct clk_stm32_gate ck_ker_csiphy = {541 .gate_id = GATE_CSI,542 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0),543};544 545/* DCMIPP */546static struct clk_stm32_gate ck_icn_p_dcmipp = {547 .gate_id = GATE_DCMIPP,548 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0),549};550 551/* CRC */552static struct clk_stm32_gate ck_icn_p_crc = {553 .gate_id = GATE_CRC,554 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0),555};556 557/* CRYP */558static struct clk_stm32_gate ck_icn_p_cryp1 = {559 .gate_id = GATE_CRYP1,560 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),561};562 563static struct clk_stm32_gate ck_icn_p_cryp2 = {564 .gate_id = GATE_CRYP2,565 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),566};567 568/* DBG & TRACE*/569/* Trace and debug clocks are managed by SCMI */570 571/* LTDC */572static struct clk_stm32_gate ck_icn_p_ltdc = {573 .gate_id = GATE_LTDC,574 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0),575};576 577static struct clk_stm32_gate ck_ker_ltdc = {578 .gate_id = GATE_LTDC,579 .hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops,580 CLK_SET_RATE_PARENT),581};582 583/* DSI */584static struct clk_stm32_gate ck_icn_p_dsi = {585 .gate_id = GATE_DSI,586 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dsi", ICN_APB4, &clk_stm32_gate_ops, 0),587};588 589static struct clk_stm32_composite clk_lanebyte = {590 .gate_id = GATE_DSI,591 .mux_id = MUX_DSIBLANE,592 .div_id = NO_STM32_DIV,593 .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_lanebyte", dsiblane_src,594 &clk_stm32_composite_ops, 0),595};596 597/* LVDS */598static struct clk_stm32_gate ck_icn_p_lvds = {599 .gate_id = GATE_LVDS,600 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lvds", ICN_APB4, &clk_stm32_gate_ops, 0),601};602 603/* DSI PHY */604static struct clk_stm32_composite clk_phy_dsi = {605 .gate_id = GATE_DSI,606 .mux_id = MUX_DSIPHY,607 .div_id = NO_STM32_DIV,608 .hw.init = CLK_HW_INIT_PARENTS_DATA("clk_phy_dsi", dsiphy_src,609 &clk_stm32_composite_ops, 0),610};611 612/* LVDS PHY */613static struct clk_stm32_composite ck_ker_lvdsphy = {614 .gate_id = GATE_LVDS,615 .mux_id = MUX_LVDSPHY,616 .div_id = NO_STM32_DIV,617 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_lvdsphy", lvdsphy_src,618 &clk_stm32_composite_ops, 0),619};620 621/* DTS */622static struct clk_stm32_composite ck_ker_dts = {623 .gate_id = GATE_DTS,624 .mux_id = MUX_DTS,625 .div_id = NO_STM32_DIV,626 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src,627 &clk_stm32_composite_ops, 0),628};629 630/* ETHERNET */631static struct clk_stm32_gate ck_icn_p_eth1 = {632 .gate_id = GATE_ETH1,633 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),634};635 636static struct clk_stm32_gate ck_ker_eth1stp = {637 .gate_id = GATE_ETH1STP,638 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),639};640 641static struct clk_stm32_gate ck_ker_eth1 = {642 .gate_id = GATE_ETH1,643 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0),644};645 646static struct clk_stm32_gate ck_ker_eth1ptp = {647 .gate_id = GATE_ETH1,648 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),649};650 651static struct clk_stm32_gate ck_ker_eth1mac = {652 .gate_id = GATE_ETH1MAC,653 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),654};655 656static struct clk_stm32_gate ck_ker_eth1tx = {657 .gate_id = GATE_ETH1TX,658 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),659};660 661static struct clk_stm32_gate ck_ker_eth1rx = {662 .gate_id = GATE_ETH1RX,663 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),664};665 666static struct clk_stm32_gate ck_icn_p_eth2 = {667 .gate_id = GATE_ETH2,668 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),669};670 671static struct clk_stm32_gate ck_ker_eth2stp = {672 .gate_id = GATE_ETH2STP,673 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0),674};675 676static struct clk_stm32_gate ck_ker_eth2 = {677 .gate_id = GATE_ETH2,678 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0),679};680 681static struct clk_stm32_gate ck_ker_eth2ptp = {682 .gate_id = GATE_ETH2,683 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0),684};685 686static struct clk_stm32_gate ck_ker_eth2mac = {687 .gate_id = GATE_ETH2MAC,688 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0),689};690 691static struct clk_stm32_gate ck_ker_eth2tx = {692 .gate_id = GATE_ETH2TX,693 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),694};695 696static struct clk_stm32_gate ck_ker_eth2rx = {697 .gate_id = GATE_ETH2RX,698 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0),699};700 701static struct clk_stm32_gate ck_icn_p_ethsw = {702 .gate_id = GATE_ETHSWMAC,703 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw", ICN_LS_MCU, &clk_stm32_gate_ops, 0),704};705 706static struct clk_stm32_gate ck_ker_ethsw = {707 .gate_id = GATE_ETHSW,708 .hw.init = CLK_HW_INIT_INDEX("ck_ker_ethsw", FLEXGEN_54, &clk_stm32_gate_ops, 0),709};710 711static struct clk_stm32_gate ck_ker_ethswref = {712 .gate_id = GATE_ETHSWREF,713 .hw.init = CLK_HW_INIT_INDEX("ck_ker_ethswref", FLEXGEN_60, &clk_stm32_gate_ops, 0),714};715 716static struct clk_stm32_gate ck_icn_p_ethsw_acm_cfg = {717 .gate_id = GATE_ETHSWACMCFG,718 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_cfg", ICN_LS_MCU,719 &clk_stm32_gate_ops, 0),720};721 722static struct clk_stm32_gate ck_icn_p_ethsw_acm_msg = {723 .gate_id = GATE_ETHSWACMMSG,724 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ethsw_acm_msg", ICN_LS_MCU,725 &clk_stm32_gate_ops, 0),726};727 728/* FDCAN */729static struct clk_stm32_gate ck_icn_p_fdcan = {730 .gate_id = GATE_FDCAN,731 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0),732};733 734static struct clk_stm32_gate ck_ker_fdcan = {735 .gate_id = GATE_FDCAN,736 .hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0),737};738 739/* GPU */740static struct clk_stm32_gate ck_icn_m_gpu = {741 .gate_id = GATE_GPU,742 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_gpu", FLEXGEN_59, &clk_stm32_gate_ops, 0),743};744 745static struct clk_stm32_gate ck_ker_gpu = {746 .gate_id = GATE_GPU,747 .hw.init = CLK_HW_INIT_INDEX("ck_ker_gpu", PLL3, &clk_stm32_gate_ops, 0),748};749 750/* HASH */751static struct clk_stm32_gate ck_icn_p_hash = {752 .gate_id = GATE_HASH,753 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash", ICN_LS_MCU, &clk_stm32_gate_ops, 0),754};755 756/* HDP */757static struct clk_stm32_gate ck_icn_p_hdp = {758 .gate_id = GATE_HDP,759 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0),760};761 762/* I2C */763static struct clk_stm32_gate ck_icn_p_i2c8 = {764 .gate_id = GATE_I2C8,765 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),766};767 768static struct clk_stm32_gate ck_icn_p_i2c1 = {769 .gate_id = GATE_I2C1,770 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0),771};772 773static struct clk_stm32_gate ck_icn_p_i2c2 = {774 .gate_id = GATE_I2C2,775 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0),776};777 778static struct clk_stm32_gate ck_icn_p_i2c3 = {779 .gate_id = GATE_I2C3,780 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB1, &clk_stm32_gate_ops, 0),781};782 783static struct clk_stm32_gate ck_icn_p_i2c4 = {784 .gate_id = GATE_I2C4,785 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c4", ICN_APB1, &clk_stm32_gate_ops, 0),786};787 788static struct clk_stm32_gate ck_icn_p_i2c5 = {789 .gate_id = GATE_I2C5,790 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c5", ICN_APB1, &clk_stm32_gate_ops, 0),791};792 793static struct clk_stm32_gate ck_icn_p_i2c6 = {794 .gate_id = GATE_I2C6,795 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c6", ICN_APB1, &clk_stm32_gate_ops, 0),796};797 798static struct clk_stm32_gate ck_icn_p_i2c7 = {799 .gate_id = GATE_I2C7,800 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c7", ICN_APB1, &clk_stm32_gate_ops, 0),801};802 803static struct clk_stm32_gate ck_ker_i2c1 = {804 .gate_id = GATE_I2C1,805 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),806};807 808static struct clk_stm32_gate ck_ker_i2c2 = {809 .gate_id = GATE_I2C2,810 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),811};812 813static struct clk_stm32_gate ck_ker_i2c3 = {814 .gate_id = GATE_I2C3,815 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),816};817 818static struct clk_stm32_gate ck_ker_i2c5 = {819 .gate_id = GATE_I2C5,820 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c5", FLEXGEN_13, &clk_stm32_gate_ops, 0),821};822 823static struct clk_stm32_gate ck_ker_i2c4 = {824 .gate_id = GATE_I2C4,825 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c4", FLEXGEN_14, &clk_stm32_gate_ops, 0),826};827 828static struct clk_stm32_gate ck_ker_i2c6 = {829 .gate_id = GATE_I2C6,830 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c6", FLEXGEN_14, &clk_stm32_gate_ops, 0),831};832 833static struct clk_stm32_gate ck_ker_i2c7 = {834 .gate_id = GATE_I2C7,835 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c7", FLEXGEN_15, &clk_stm32_gate_ops, 0),836};837 838static struct clk_stm32_gate ck_ker_i2c8 = {839 .gate_id = GATE_I2C8,840 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c8", FLEXGEN_38, &clk_stm32_gate_ops, 0),841};842 843/* I3C */844static struct clk_stm32_gate ck_icn_p_i3c1 = {845 .gate_id = GATE_I3C1,846 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0),847};848 849static struct clk_stm32_gate ck_icn_p_i3c2 = {850 .gate_id = GATE_I3C2,851 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0),852};853 854static struct clk_stm32_gate ck_icn_p_i3c3 = {855 .gate_id = GATE_I3C3,856 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB1, &clk_stm32_gate_ops, 0),857};858 859static struct clk_stm32_gate ck_icn_p_i3c4 = {860 .gate_id = GATE_I3C4,861 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),862};863 864static struct clk_stm32_gate ck_ker_i3c1 = {865 .gate_id = GATE_I3C1,866 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_12, &clk_stm32_gate_ops, 0),867};868 869static struct clk_stm32_gate ck_ker_i3c2 = {870 .gate_id = GATE_I3C2,871 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_12, &clk_stm32_gate_ops, 0),872};873 874static struct clk_stm32_gate ck_ker_i3c3 = {875 .gate_id = GATE_I3C3,876 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_13, &clk_stm32_gate_ops, 0),877};878 879static struct clk_stm32_gate ck_ker_i3c4 = {880 .gate_id = GATE_I3C4,881 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c4", FLEXGEN_36, &clk_stm32_gate_ops, 0),882};883 884/* I2S */885static struct clk_stm32_gate ck_icn_p_is2m = {886 .gate_id = GATE_IS2M,887 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_is2m", ICN_APB3, &clk_stm32_gate_ops, 0),888};889 890/* IWDG */891static struct clk_stm32_gate ck_icn_p_iwdg1 = {892 .gate_id = GATE_IWDG1,893 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),894};895 896static struct clk_stm32_gate ck_icn_p_iwdg2 = {897 .gate_id = GATE_IWDG2,898 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),899};900 901static struct clk_stm32_gate ck_icn_p_iwdg3 = {902 .gate_id = GATE_IWDG3,903 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0),904};905 906static struct clk_stm32_gate ck_icn_p_iwdg4 = {907 .gate_id = GATE_IWDG4,908 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0),909};910 911static struct clk_stm32_gate ck_icn_p_iwdg5 = {912 .gate_id = GATE_IWDG5,913 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),914};915 916/* LPTIM */917static struct clk_stm32_gate ck_icn_p_lptim1 = {918 .gate_id = GATE_LPTIM1,919 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0),920};921 922static struct clk_stm32_gate ck_icn_p_lptim2 = {923 .gate_id = GATE_LPTIM2,924 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0),925};926 927static struct clk_stm32_gate ck_icn_p_lptim3 = {928 .gate_id = GATE_LPTIM3,929 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),930};931 932static struct clk_stm32_gate ck_icn_p_lptim4 = {933 .gate_id = GATE_LPTIM4,934 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0),935};936 937static struct clk_stm32_gate ck_icn_p_lptim5 = {938 .gate_id = GATE_LPTIM5,939 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0),940};941 942static struct clk_stm32_gate ck_ker_lptim1 = {943 .gate_id = GATE_LPTIM1,944 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0),945};946 947static struct clk_stm32_gate ck_ker_lptim2 = {948 .gate_id = GATE_LPTIM2,949 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0),950};951 952static struct clk_stm32_gate ck_ker_lptim3 = {953 .gate_id = GATE_LPTIM3,954 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0),955};956 957static struct clk_stm32_gate ck_ker_lptim4 = {958 .gate_id = GATE_LPTIM4,959 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0),960};961 962static struct clk_stm32_gate ck_ker_lptim5 = {963 .gate_id = GATE_LPTIM5,964 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_41, &clk_stm32_gate_ops, 0),965};966 967/* LPUART */968static struct clk_stm32_gate ck_icn_p_lpuart1 = {969 .gate_id = GATE_LPUART1,970 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),971};972 973static struct clk_stm32_gate ck_ker_lpuart1 = {974 .gate_id = GATE_LPUART1,975 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0),976};977 978/* MCO1 & MCO2 */979static struct clk_stm32_composite ck_mco1 = {980 .gate_id = GATE_MCO1,981 .mux_id = MUX_MCO1,982 .div_id = NO_STM32_DIV,983 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0),984};985 986static struct clk_stm32_composite ck_mco2 = {987 .gate_id = GATE_MCO2,988 .mux_id = MUX_MCO2,989 .div_id = NO_STM32_DIV,990 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0),991};992 993/* MDF */994static struct clk_stm32_gate ck_icn_p_mdf1 = {995 .gate_id = GATE_MDF1,996 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0),997};998 999static struct clk_stm32_gate ck_ker_mdf1 = {1000 .gate_id = GATE_MDF1,1001 .hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_23, &clk_stm32_gate_ops, 0),1002};1003 1004/* OSPI */1005static struct clk_stm32_gate ck_icn_p_ospiiom = {1006 .gate_id = GATE_OSPIIOM,1007 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ospiiom", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1008};1009 1010/* PCIE */1011static struct clk_stm32_gate ck_icn_p_pcie = {1012 .gate_id = GATE_PCIE,1013 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pcie", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1014};1015 1016/* PKA */1017static struct clk_stm32_gate ck_icn_p_pka = {1018 .gate_id = GATE_PKA,1019 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pka", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1020};1021 1022/* RNG */1023static struct clk_stm32_gate ck_icn_p_rng = {1024 .gate_id = GATE_RNG,1025 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1026};1027 1028/* SAES */1029static struct clk_stm32_gate ck_icn_p_saes = {1030 .gate_id = GATE_SAES,1031 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_saes", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1032};1033 1034/* SAI */1035static struct clk_stm32_gate ck_icn_p_sai1 = {1036 .gate_id = GATE_SAI1,1037 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0),1038};1039 1040static struct clk_stm32_gate ck_icn_p_sai2 = {1041 .gate_id = GATE_SAI2,1042 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0),1043};1044 1045static struct clk_stm32_gate ck_icn_p_sai3 = {1046 .gate_id = GATE_SAI3,1047 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0),1048};1049 1050static struct clk_stm32_gate ck_icn_p_sai4 = {1051 .gate_id = GATE_SAI4,1052 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0),1053};1054 1055static struct clk_stm32_gate ck_ker_sai1 = {1056 .gate_id = GATE_SAI1,1057 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_23, &clk_stm32_gate_ops,1058 CLK_SET_RATE_PARENT),1059};1060 1061static struct clk_stm32_gate ck_ker_sai2 = {1062 .gate_id = GATE_SAI2,1063 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_24, &clk_stm32_gate_ops,1064 CLK_SET_RATE_PARENT),1065};1066 1067static struct clk_stm32_gate ck_ker_sai3 = {1068 .gate_id = GATE_SAI3,1069 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_25, &clk_stm32_gate_ops,1070 CLK_SET_RATE_PARENT),1071};1072 1073static struct clk_stm32_gate ck_ker_sai4 = {1074 .gate_id = GATE_SAI4,1075 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops,1076 CLK_SET_RATE_PARENT),1077};1078 1079/* SDMMC */1080static struct clk_stm32_gate ck_icn_m_sdmmc1 = {1081 .gate_id = GATE_SDMMC1,1082 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0),1083};1084 1085static struct clk_stm32_gate ck_icn_m_sdmmc2 = {1086 .gate_id = GATE_SDMMC2,1087 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0),1088};1089 1090static struct clk_stm32_gate ck_icn_m_sdmmc3 = {1091 .gate_id = GATE_SDMMC3,1092 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0),1093};1094 1095static struct clk_stm32_gate ck_ker_sdmmc1 = {1096 .gate_id = GATE_SDMMC1,1097 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0),1098};1099 1100static struct clk_stm32_gate ck_ker_sdmmc2 = {1101 .gate_id = GATE_SDMMC2,1102 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0),1103};1104 1105static struct clk_stm32_gate ck_ker_sdmmc3 = {1106 .gate_id = GATE_SDMMC3,1107 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),1108};1109 1110/* SERC */1111static struct clk_stm32_gate ck_icn_p_serc = {1112 .gate_id = GATE_SERC,1113 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_serc", ICN_APB3, &clk_stm32_gate_ops, 0),1114};1115 1116/* SPDIF */1117static struct clk_stm32_gate ck_icn_p_spdifrx = {1118 .gate_id = GATE_SPDIFRX,1119 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0),1120};1121 1122static struct clk_stm32_gate ck_ker_spdifrx = {1123 .gate_id = GATE_SPDIFRX,1124 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_11, &clk_stm32_gate_ops, 0),1125};1126 1127/* SPI */1128static struct clk_stm32_gate ck_icn_p_spi1 = {1129 .gate_id = GATE_SPI1,1130 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0),1131};1132 1133static struct clk_stm32_gate ck_icn_p_spi2 = {1134 .gate_id = GATE_SPI2,1135 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0),1136};1137 1138static struct clk_stm32_gate ck_icn_p_spi3 = {1139 .gate_id = GATE_SPI3,1140 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0),1141};1142 1143static struct clk_stm32_gate ck_icn_p_spi4 = {1144 .gate_id = GATE_SPI4,1145 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0),1146};1147 1148static struct clk_stm32_gate ck_icn_p_spi5 = {1149 .gate_id = GATE_SPI5,1150 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0),1151};1152 1153static struct clk_stm32_gate ck_icn_p_spi6 = {1154 .gate_id = GATE_SPI6,1155 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0),1156};1157 1158static struct clk_stm32_gate ck_icn_p_spi7 = {1159 .gate_id = GATE_SPI7,1160 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi7", ICN_APB2, &clk_stm32_gate_ops, 0),1161};1162 1163static struct clk_stm32_gate ck_icn_p_spi8 = {1164 .gate_id = GATE_SPI8,1165 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi8", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1166};1167 1168static struct clk_stm32_gate ck_ker_spi1 = {1169 .gate_id = GATE_SPI1,1170 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops,1171 CLK_SET_RATE_PARENT),1172};1173 1174static struct clk_stm32_gate ck_ker_spi2 = {1175 .gate_id = GATE_SPI2,1176 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops,1177 CLK_SET_RATE_PARENT),1178};1179 1180static struct clk_stm32_gate ck_ker_spi3 = {1181 .gate_id = GATE_SPI3,1182 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_10, &clk_stm32_gate_ops,1183 CLK_SET_RATE_PARENT),1184};1185 1186static struct clk_stm32_gate ck_ker_spi4 = {1187 .gate_id = GATE_SPI4,1188 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0),1189};1190 1191static struct clk_stm32_gate ck_ker_spi5 = {1192 .gate_id = GATE_SPI5,1193 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0),1194};1195 1196static struct clk_stm32_gate ck_ker_spi6 = {1197 .gate_id = GATE_SPI6,1198 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_18, &clk_stm32_gate_ops, 0),1199};1200 1201static struct clk_stm32_gate ck_ker_spi7 = {1202 .gate_id = GATE_SPI7,1203 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi7", FLEXGEN_18, &clk_stm32_gate_ops, 0),1204};1205 1206static struct clk_stm32_gate ck_ker_spi8 = {1207 .gate_id = GATE_SPI8,1208 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi8", FLEXGEN_37, &clk_stm32_gate_ops, 0),1209};1210 1211/* Timers */1212static struct clk_stm32_gate ck_icn_p_tim2 = {1213 .gate_id = GATE_TIM2,1214 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0),1215};1216 1217static struct clk_stm32_gate ck_icn_p_tim3 = {1218 .gate_id = GATE_TIM3,1219 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0),1220};1221 1222static struct clk_stm32_gate ck_icn_p_tim4 = {1223 .gate_id = GATE_TIM4,1224 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0),1225};1226 1227static struct clk_stm32_gate ck_icn_p_tim5 = {1228 .gate_id = GATE_TIM5,1229 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0),1230};1231 1232static struct clk_stm32_gate ck_icn_p_tim6 = {1233 .gate_id = GATE_TIM6,1234 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0),1235};1236 1237static struct clk_stm32_gate ck_icn_p_tim7 = {1238 .gate_id = GATE_TIM7,1239 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0),1240};1241 1242static struct clk_stm32_gate ck_icn_p_tim10 = {1243 .gate_id = GATE_TIM10,1244 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0),1245};1246 1247static struct clk_stm32_gate ck_icn_p_tim11 = {1248 .gate_id = GATE_TIM11,1249 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0),1250};1251 1252static struct clk_stm32_gate ck_icn_p_tim12 = {1253 .gate_id = GATE_TIM12,1254 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0),1255};1256 1257static struct clk_stm32_gate ck_icn_p_tim13 = {1258 .gate_id = GATE_TIM13,1259 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0),1260};1261 1262static struct clk_stm32_gate ck_icn_p_tim14 = {1263 .gate_id = GATE_TIM14,1264 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0),1265};1266 1267static struct clk_stm32_gate ck_icn_p_tim1 = {1268 .gate_id = GATE_TIM1,1269 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0),1270};1271 1272static struct clk_stm32_gate ck_icn_p_tim8 = {1273 .gate_id = GATE_TIM8,1274 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0),1275};1276 1277static struct clk_stm32_gate ck_icn_p_tim15 = {1278 .gate_id = GATE_TIM15,1279 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0),1280};1281 1282static struct clk_stm32_gate ck_icn_p_tim16 = {1283 .gate_id = GATE_TIM16,1284 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0),1285};1286 1287static struct clk_stm32_gate ck_icn_p_tim17 = {1288 .gate_id = GATE_TIM17,1289 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0),1290};1291 1292static struct clk_stm32_gate ck_icn_p_tim20 = {1293 .gate_id = GATE_TIM20,1294 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim20", ICN_APB2, &clk_stm32_gate_ops, 0),1295};1296 1297static struct clk_stm32_gate ck_ker_tim2 = {1298 .gate_id = GATE_TIM2,1299 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0),1300};1301 1302static struct clk_stm32_gate ck_ker_tim3 = {1303 .gate_id = GATE_TIM3,1304 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0),1305};1306 1307static struct clk_stm32_gate ck_ker_tim4 = {1308 .gate_id = GATE_TIM4,1309 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0),1310};1311 1312static struct clk_stm32_gate ck_ker_tim5 = {1313 .gate_id = GATE_TIM5,1314 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0),1315};1316 1317static struct clk_stm32_gate ck_ker_tim6 = {1318 .gate_id = GATE_TIM6,1319 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0),1320};1321 1322static struct clk_stm32_gate ck_ker_tim7 = {1323 .gate_id = GATE_TIM7,1324 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0),1325};1326 1327static struct clk_stm32_gate ck_ker_tim10 = {1328 .gate_id = GATE_TIM10,1329 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0),1330};1331 1332static struct clk_stm32_gate ck_ker_tim11 = {1333 .gate_id = GATE_TIM11,1334 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0),1335};1336 1337static struct clk_stm32_gate ck_ker_tim12 = {1338 .gate_id = GATE_TIM12,1339 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0),1340};1341 1342static struct clk_stm32_gate ck_ker_tim13 = {1343 .gate_id = GATE_TIM13,1344 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0),1345};1346 1347static struct clk_stm32_gate ck_ker_tim14 = {1348 .gate_id = GATE_TIM14,1349 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0),1350};1351 1352static struct clk_stm32_gate ck_ker_tim1 = {1353 .gate_id = GATE_TIM1,1354 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0),1355};1356 1357static struct clk_stm32_gate ck_ker_tim8 = {1358 .gate_id = GATE_TIM8,1359 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0),1360};1361 1362static struct clk_stm32_gate ck_ker_tim15 = {1363 .gate_id = GATE_TIM15,1364 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0),1365};1366 1367static struct clk_stm32_gate ck_ker_tim16 = {1368 .gate_id = GATE_TIM16,1369 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0),1370};1371 1372static struct clk_stm32_gate ck_ker_tim17 = {1373 .gate_id = GATE_TIM17,1374 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0),1375};1376 1377static struct clk_stm32_gate ck_ker_tim20 = {1378 .gate_id = GATE_TIM20,1379 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim20", TIMG2, &clk_stm32_gate_ops, 0),1380};1381 1382/* UART/USART */1383static struct clk_stm32_gate ck_icn_p_usart2 = {1384 .gate_id = GATE_USART2,1385 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0),1386};1387 1388static struct clk_stm32_gate ck_icn_p_usart3 = {1389 .gate_id = GATE_USART3,1390 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0),1391};1392 1393static struct clk_stm32_gate ck_icn_p_uart4 = {1394 .gate_id = GATE_UART4,1395 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0),1396};1397 1398static struct clk_stm32_gate ck_icn_p_uart5 = {1399 .gate_id = GATE_UART5,1400 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0),1401};1402 1403static struct clk_stm32_gate ck_icn_p_usart1 = {1404 .gate_id = GATE_USART1,1405 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0),1406};1407 1408static struct clk_stm32_gate ck_icn_p_usart6 = {1409 .gate_id = GATE_USART6,1410 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0),1411};1412 1413static struct clk_stm32_gate ck_icn_p_uart7 = {1414 .gate_id = GATE_UART7,1415 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0),1416};1417 1418static struct clk_stm32_gate ck_icn_p_uart8 = {1419 .gate_id = GATE_UART8,1420 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart8", ICN_APB2, &clk_stm32_gate_ops, 0),1421};1422 1423static struct clk_stm32_gate ck_icn_p_uart9 = {1424 .gate_id = GATE_UART9,1425 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart9", ICN_APB2, &clk_stm32_gate_ops, 0),1426};1427 1428static struct clk_stm32_gate ck_ker_usart2 = {1429 .gate_id = GATE_USART2,1430 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0),1431};1432 1433static struct clk_stm32_gate ck_ker_uart4 = {1434 .gate_id = GATE_UART4,1435 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0),1436};1437 1438static struct clk_stm32_gate ck_ker_usart3 = {1439 .gate_id = GATE_USART3,1440 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0),1441};1442 1443static struct clk_stm32_gate ck_ker_uart5 = {1444 .gate_id = GATE_UART5,1445 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0),1446};1447 1448static struct clk_stm32_gate ck_ker_usart1 = {1449 .gate_id = GATE_USART1,1450 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_19, &clk_stm32_gate_ops, 0),1451};1452 1453static struct clk_stm32_gate ck_ker_usart6 = {1454 .gate_id = GATE_USART6,1455 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_20, &clk_stm32_gate_ops, 0),1456};1457 1458static struct clk_stm32_gate ck_ker_uart7 = {1459 .gate_id = GATE_UART7,1460 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_21, &clk_stm32_gate_ops, 0),1461};1462 1463static struct clk_stm32_gate ck_ker_uart8 = {1464 .gate_id = GATE_UART8,1465 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart8", FLEXGEN_21, &clk_stm32_gate_ops, 0),1466};1467 1468static struct clk_stm32_gate ck_ker_uart9 = {1469 .gate_id = GATE_UART9,1470 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart9", FLEXGEN_22, &clk_stm32_gate_ops, 0),1471};1472 1473/* USB2PHY1 */1474static struct clk_stm32_composite ck_ker_usb2phy1 = {1475 .gate_id = GATE_USB2PHY1,1476 .mux_id = MUX_USB2PHY1,1477 .div_id = NO_STM32_DIV,1478 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src,1479 &clk_stm32_composite_ops, 0),1480};1481 1482/* USB2H */1483static struct clk_stm32_gate ck_icn_m_usb2ehci = {1484 .gate_id = GATE_USBH,1485 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ehci", ICN_HSL, &clk_stm32_gate_ops, 0),1486};1487 1488static struct clk_stm32_gate ck_icn_m_usb2ohci = {1489 .gate_id = GATE_USBH,1490 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb2ohci", ICN_HSL, &clk_stm32_gate_ops, 0),1491};1492 1493/* USB2PHY2 */1494static struct clk_stm32_composite ck_ker_usb2phy2_en = {1495 .gate_id = GATE_USB2PHY2,1496 .mux_id = MUX_USB2PHY2,1497 .div_id = NO_STM32_DIV,1498 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src,1499 &clk_stm32_composite_ops, 0),1500};1501 1502/* USB3 PCIe COMBOPHY */1503static struct clk_stm32_gate ck_icn_p_usb3pciephy = {1504 .gate_id = GATE_USB3PCIEPHY,1505 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usb3pciephy", ICN_APB4, &clk_stm32_gate_ops, 0),1506};1507 1508static struct clk_stm32_composite ck_ker_usb3pciephy = {1509 .gate_id = GATE_USB3PCIEPHY,1510 .mux_id = MUX_USB3PCIEPHY,1511 .div_id = NO_STM32_DIV,1512 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb3pciephy", usb3pciphy_src,1513 &clk_stm32_composite_ops, 0),1514};1515 1516/* USB3 DRD */1517static struct clk_stm32_gate ck_icn_m_usb3dr = {1518 .gate_id = GATE_USB3DR,1519 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usb3dr", ICN_HSL, &clk_stm32_gate_ops, 0),1520};1521 1522static struct clk_stm32_gate ck_ker_usb2phy2 = {1523 .gate_id = GATE_USB3DR,1524 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usb2phy2", FLEXGEN_58, &clk_stm32_gate_ops, 0),1525};1526 1527/* USBTC */1528static struct clk_stm32_gate ck_icn_p_usbtc = {1529 .gate_id = GATE_USBTC,1530 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usbtc", ICN_APB4, &clk_stm32_gate_ops, 0),1531};1532 1533static struct clk_stm32_gate ck_ker_usbtc = {1534 .gate_id = GATE_USBTC,1535 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usbtc", FLEXGEN_35, &clk_stm32_gate_ops, 0),1536};1537 1538/* VDEC / VENC */1539static struct clk_stm32_gate ck_icn_p_vdec = {1540 .gate_id = GATE_VDEC,1541 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vdec", ICN_APB4, &clk_stm32_gate_ops, 0),1542};1543 1544static struct clk_stm32_gate ck_icn_p_venc = {1545 .gate_id = GATE_VENC,1546 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_venc", ICN_APB4, &clk_stm32_gate_ops, 0),1547};1548 1549/* VREF */1550static struct clk_stm32_gate ck_icn_p_vref = {1551 .gate_id = GATE_VREF,1552 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0),1553};1554 1555/* WWDG */1556static struct clk_stm32_gate ck_icn_p_wwdg1 = {1557 .gate_id = GATE_WWDG1,1558 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),1559};1560 1561static struct clk_stm32_gate ck_icn_p_wwdg2 = {1562 .gate_id = GATE_WWDG2,1563 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg2", ICN_LS_MCU, &clk_stm32_gate_ops, 0),1564};1565 1566static struct stm32_firewall firewall;1567 1568static int stm32_rcc_get_access(void __iomem *base, u32 index)1569{1570 u32 seccfgr, cidcfgr, semcr;1571 int bit, cid;1572 1573 bit = index % RCC_REG_SIZE;1574 1575 seccfgr = readl(base + RCC_SECCFGR(index));1576 if (seccfgr & BIT(bit))1577 return -EACCES;1578 1579 cidcfgr = readl(base + RCC_CIDCFGR(index));1580 if (!(cidcfgr & RCC_CIDCFGR_CFEN))1581 /* CID filtering is turned off: access granted */1582 return 0;1583 1584 if (!(cidcfgr & RCC_CIDCFGR_SEM_EN)) {1585 /* Static CID mode */1586 cid = FIELD_GET(RCC_CIDCFGR_SCID_MASK, cidcfgr);1587 if (cid != RCC_CID1)1588 return -EACCES;1589 return 0;1590 }1591 1592 /* Pass-list with semaphore mode */1593 if (!(cidcfgr & RCC_CIDCFGR_SEMWLC1_EN))1594 return -EACCES;1595 1596 semcr = readl(base + RCC_SEMCR(index));1597 1598 cid = FIELD_GET(RCC_SEMCR_SEMCID_MASK, semcr);1599 if (cid != RCC_CID1)1600 return -EACCES;1601 1602 return 0;1603}1604 1605static int stm32mp25_check_security(struct device_node *np, void __iomem *base,1606 const struct clock_config *cfg)1607{1608 int ret = 0;1609 1610 if (cfg->sec_id != SECF_NONE) {1611 u32 index = (u32)cfg->sec_id;1612 1613 if (index & SEC_RIFSC_FLAG) {1614 ret = stm32_firewall_grant_access_by_id(&firewall, index & ~SEC_RIFSC_FLAG);1615 1616 /* If firewall is not present, assume that we have access */1617 if (ret == -ENODEV)1618 return 0;1619 } else {1620 ret = stm32_rcc_get_access(base, cfg->sec_id & ~SEC_RIFSC_FLAG);1621 }1622 }1623 1624 return ret;1625}1626 1627static const struct clock_config stm32mp25_clock_cfg[] = {1628 STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SEC_RIFSC(60)),1629 STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SEC_RIFSC(61)),1630 STM32_GATE_CFG(CK_BUS_PCIE, ck_icn_p_pcie, SEC_RIFSC(68)),1631 STM32_GATE_CFG(CK_BUS_ETHSW, ck_icn_p_ethsw, SEC_RIFSC(70)),1632 STM32_GATE_CFG(CK_BUS_ADC12, ck_icn_p_adc12, SEC_RIFSC(58)),1633 STM32_GATE_CFG(CK_BUS_ADC3, ck_icn_p_adc3, SEC_RIFSC(59)),1634 STM32_GATE_CFG(CK_BUS_CCI, ck_icn_p_cci, SEC_RIFSC(88)),1635 STM32_GATE_CFG(CK_BUS_CRC, ck_icn_p_crc, SEC_RIFSC(109)),1636 STM32_GATE_CFG(CK_BUS_MDF1, ck_icn_p_mdf1, SEC_RIFSC(54)),1637 STM32_GATE_CFG(CK_BUS_OSPIIOM, ck_icn_p_ospiiom, SEC_RIFSC(111)),1638 STM32_GATE_CFG(CK_BUS_HASH, ck_icn_p_hash, SEC_RIFSC(95)),1639 STM32_GATE_CFG(CK_BUS_RNG, ck_icn_p_rng, SEC_RIFSC(92)),1640 STM32_GATE_CFG(CK_BUS_CRYP1, ck_icn_p_cryp1, SEC_RIFSC(96)),1641 STM32_GATE_CFG(CK_BUS_CRYP2, ck_icn_p_cryp2, SEC_RIFSC(97)),1642 STM32_GATE_CFG(CK_BUS_SAES, ck_icn_p_saes, SEC_RIFSC(94)),1643 STM32_GATE_CFG(CK_BUS_PKA, ck_icn_p_pka, SEC_RIFSC(93)),1644 STM32_GATE_CFG(CK_BUS_ADF1, ck_icn_p_adf1, SEC_RIFSC(55)),1645 STM32_GATE_CFG(CK_BUS_SPI8, ck_icn_p_spi8, SEC_RIFSC(29)),1646 STM32_GATE_CFG(CK_BUS_LPUART1, ck_icn_p_lpuart1, SEC_RIFSC(40)),1647 STM32_GATE_CFG(CK_BUS_I2C8, ck_icn_p_i2c8, SEC_RIFSC(48)),1648 STM32_GATE_CFG(CK_BUS_LPTIM3, ck_icn_p_lptim3, SEC_RIFSC(19)),1649 STM32_GATE_CFG(CK_BUS_LPTIM4, ck_icn_p_lptim4, SEC_RIFSC(20)),1650 STM32_GATE_CFG(CK_BUS_LPTIM5, ck_icn_p_lptim5, SEC_RIFSC(21)),1651 STM32_GATE_CFG(CK_BUS_IWDG5, ck_icn_p_iwdg5, SEC_RIFSC(102)),1652 STM32_GATE_CFG(CK_BUS_WWDG2, ck_icn_p_wwdg2, SEC_RIFSC(104)),1653 STM32_GATE_CFG(CK_BUS_I3C4, ck_icn_p_i3c4, SEC_RIFSC(117)),1654 STM32_GATE_CFG(CK_BUS_SDMMC1, ck_icn_m_sdmmc1, SEC_RIFSC(76)),1655 STM32_GATE_CFG(CK_BUS_SDMMC2, ck_icn_m_sdmmc2, SEC_RIFSC(77)),1656 STM32_GATE_CFG(CK_BUS_SDMMC3, ck_icn_m_sdmmc3, SEC_RIFSC(78)),1657 STM32_GATE_CFG(CK_BUS_USB2OHCI, ck_icn_m_usb2ohci, SEC_RIFSC(63)),1658 STM32_GATE_CFG(CK_BUS_USB2EHCI, ck_icn_m_usb2ehci, SEC_RIFSC(63)),1659 STM32_GATE_CFG(CK_BUS_USB3DR, ck_icn_m_usb3dr, SEC_RIFSC(66)),1660 STM32_GATE_CFG(CK_BUS_TIM2, ck_icn_p_tim2, SEC_RIFSC(1)),1661 STM32_GATE_CFG(CK_BUS_TIM3, ck_icn_p_tim3, SEC_RIFSC(2)),1662 STM32_GATE_CFG(CK_BUS_TIM4, ck_icn_p_tim4, SEC_RIFSC(3)),1663 STM32_GATE_CFG(CK_BUS_TIM5, ck_icn_p_tim5, SEC_RIFSC(4)),1664 STM32_GATE_CFG(CK_BUS_TIM6, ck_icn_p_tim6, SEC_RIFSC(5)),1665 STM32_GATE_CFG(CK_BUS_TIM7, ck_icn_p_tim7, SEC_RIFSC(6)),1666 STM32_GATE_CFG(CK_BUS_TIM10, ck_icn_p_tim10, SEC_RIFSC(8)),1667 STM32_GATE_CFG(CK_BUS_TIM11, ck_icn_p_tim11, SEC_RIFSC(9)),1668 STM32_GATE_CFG(CK_BUS_TIM12, ck_icn_p_tim12, SEC_RIFSC(10)),1669 STM32_GATE_CFG(CK_BUS_TIM13, ck_icn_p_tim13, SEC_RIFSC(11)),1670 STM32_GATE_CFG(CK_BUS_TIM14, ck_icn_p_tim14, SEC_RIFSC(12)),1671 STM32_GATE_CFG(CK_BUS_LPTIM1, ck_icn_p_lptim1, SEC_RIFSC(17)),1672 STM32_GATE_CFG(CK_BUS_LPTIM2, ck_icn_p_lptim2, SEC_RIFSC(18)),1673 STM32_GATE_CFG(CK_BUS_SPI2, ck_icn_p_spi2, SEC_RIFSC(23)),1674 STM32_GATE_CFG(CK_BUS_SPI3, ck_icn_p_spi3, SEC_RIFSC(24)),1675 STM32_GATE_CFG(CK_BUS_SPDIFRX, ck_icn_p_spdifrx, SEC_RIFSC(30)),1676 STM32_GATE_CFG(CK_BUS_USART2, ck_icn_p_usart2, SEC_RIFSC(32)),1677 STM32_GATE_CFG(CK_BUS_USART3, ck_icn_p_usart3, SEC_RIFSC(33)),1678 STM32_GATE_CFG(CK_BUS_UART4, ck_icn_p_uart4, SEC_RIFSC(34)),1679 STM32_GATE_CFG(CK_BUS_UART5, ck_icn_p_uart5, SEC_RIFSC(35)),1680 STM32_GATE_CFG(CK_BUS_I2C1, ck_icn_p_i2c1, SEC_RIFSC(41)),1681 STM32_GATE_CFG(CK_BUS_I2C2, ck_icn_p_i2c2, SEC_RIFSC(42)),1682 STM32_GATE_CFG(CK_BUS_I2C3, ck_icn_p_i2c3, SEC_RIFSC(43)),1683 STM32_GATE_CFG(CK_BUS_I2C4, ck_icn_p_i2c4, SEC_RIFSC(44)),1684 STM32_GATE_CFG(CK_BUS_I2C5, ck_icn_p_i2c5, SEC_RIFSC(45)),1685 STM32_GATE_CFG(CK_BUS_I2C6, ck_icn_p_i2c6, SEC_RIFSC(46)),1686 STM32_GATE_CFG(CK_BUS_I2C7, ck_icn_p_i2c7, SEC_RIFSC(47)),1687 STM32_GATE_CFG(CK_BUS_I3C1, ck_icn_p_i3c1, SEC_RIFSC(114)),1688 STM32_GATE_CFG(CK_BUS_I3C2, ck_icn_p_i3c2, SEC_RIFSC(115)),1689 STM32_GATE_CFG(CK_BUS_I3C3, ck_icn_p_i3c3, SEC_RIFSC(116)),1690 STM32_GATE_CFG(CK_BUS_TIM1, ck_icn_p_tim1, SEC_RIFSC(0)),1691 STM32_GATE_CFG(CK_BUS_TIM8, ck_icn_p_tim8, SEC_RIFSC(7)),1692 STM32_GATE_CFG(CK_BUS_TIM15, ck_icn_p_tim15, SEC_RIFSC(13)),1693 STM32_GATE_CFG(CK_BUS_TIM16, ck_icn_p_tim16, SEC_RIFSC(14)),1694 STM32_GATE_CFG(CK_BUS_TIM17, ck_icn_p_tim17, SEC_RIFSC(15)),1695 STM32_GATE_CFG(CK_BUS_TIM20, ck_icn_p_tim20, SEC_RIFSC(16)),1696 STM32_GATE_CFG(CK_BUS_SAI1, ck_icn_p_sai1, SEC_RIFSC(49)),1697 STM32_GATE_CFG(CK_BUS_SAI2, ck_icn_p_sai2, SEC_RIFSC(50)),1698 STM32_GATE_CFG(CK_BUS_SAI3, ck_icn_p_sai3, SEC_RIFSC(51)),1699 STM32_GATE_CFG(CK_BUS_SAI4, ck_icn_p_sai4, SEC_RIFSC(52)),1700 STM32_GATE_CFG(CK_BUS_USART1, ck_icn_p_usart1, SEC_RIFSC(31)),1701 STM32_GATE_CFG(CK_BUS_USART6, ck_icn_p_usart6, SEC_RIFSC(36)),1702 STM32_GATE_CFG(CK_BUS_UART7, ck_icn_p_uart7, SEC_RIFSC(37)),1703 STM32_GATE_CFG(CK_BUS_UART8, ck_icn_p_uart8, SEC_RIFSC(38)),1704 STM32_GATE_CFG(CK_BUS_UART9, ck_icn_p_uart9, SEC_RIFSC(39)),1705 STM32_GATE_CFG(CK_BUS_FDCAN, ck_icn_p_fdcan, SEC_RIFSC(56)),1706 STM32_GATE_CFG(CK_BUS_SPI1, ck_icn_p_spi1, SEC_RIFSC(22)),1707 STM32_GATE_CFG(CK_BUS_SPI4, ck_icn_p_spi4, SEC_RIFSC(25)),1708 STM32_GATE_CFG(CK_BUS_SPI5, ck_icn_p_spi5, SEC_RIFSC(26)),1709 STM32_GATE_CFG(CK_BUS_SPI6, ck_icn_p_spi6, SEC_RIFSC(27)),1710 STM32_GATE_CFG(CK_BUS_SPI7, ck_icn_p_spi7, SEC_RIFSC(28)),1711 STM32_GATE_CFG(CK_BUS_IWDG1, ck_icn_p_iwdg1, SEC_RIFSC(98)),1712 STM32_GATE_CFG(CK_BUS_IWDG2, ck_icn_p_iwdg2, SEC_RIFSC(99)),1713 STM32_GATE_CFG(CK_BUS_IWDG3, ck_icn_p_iwdg3, SEC_RIFSC(100)),1714 STM32_GATE_CFG(CK_BUS_IWDG4, ck_icn_p_iwdg4, SEC_RIFSC(101)),1715 STM32_GATE_CFG(CK_BUS_WWDG1, ck_icn_p_wwdg1, SEC_RIFSC(103)),1716 STM32_GATE_CFG(CK_BUS_VREF, ck_icn_p_vref, SEC_RIFSC(106)),1717 STM32_GATE_CFG(CK_BUS_SERC, ck_icn_p_serc, SEC_RIFSC(110)),1718 STM32_GATE_CFG(CK_BUS_HDP, ck_icn_p_hdp, SEC_RIFSC(57)),1719 STM32_GATE_CFG(CK_BUS_IS2M, ck_icn_p_is2m, MP25_RIF_RCC_IS2M),1720 STM32_GATE_CFG(CK_BUS_DSI, ck_icn_p_dsi, SEC_RIFSC(81)),1721 STM32_GATE_CFG(CK_BUS_LTDC, ck_icn_p_ltdc, SEC_RIFSC(80)),1722 STM32_GATE_CFG(CK_BUS_CSI, ck_icn_p_csi, SEC_RIFSC(86)),1723 STM32_GATE_CFG(CK_BUS_DCMIPP, ck_icn_p_dcmipp, SEC_RIFSC(87)),1724 STM32_GATE_CFG(CK_BUS_LVDS, ck_icn_p_lvds, SEC_RIFSC(84)),1725 STM32_GATE_CFG(CK_BUS_USBTC, ck_icn_p_usbtc, SEC_RIFSC(69)),1726 STM32_GATE_CFG(CK_BUS_USB3PCIEPHY, ck_icn_p_usb3pciephy, SEC_RIFSC(67)),1727 STM32_GATE_CFG(CK_BUS_VDEC, ck_icn_p_vdec, SEC_RIFSC(89)),1728 STM32_GATE_CFG(CK_BUS_VENC, ck_icn_p_venc, SEC_RIFSC(90)),1729 STM32_GATE_CFG(CK_KER_TIM2, ck_ker_tim2, SEC_RIFSC(1)),1730 STM32_GATE_CFG(CK_KER_TIM3, ck_ker_tim3, SEC_RIFSC(2)),1731 STM32_GATE_CFG(CK_KER_TIM4, ck_ker_tim4, SEC_RIFSC(3)),1732 STM32_GATE_CFG(CK_KER_TIM5, ck_ker_tim5, SEC_RIFSC(4)),1733 STM32_GATE_CFG(CK_KER_TIM6, ck_ker_tim6, SEC_RIFSC(5)),1734 STM32_GATE_CFG(CK_KER_TIM7, ck_ker_tim7, SEC_RIFSC(6)),1735 STM32_GATE_CFG(CK_KER_TIM10, ck_ker_tim10, SEC_RIFSC(8)),1736 STM32_GATE_CFG(CK_KER_TIM11, ck_ker_tim11, SEC_RIFSC(9)),1737 STM32_GATE_CFG(CK_KER_TIM12, ck_ker_tim12, SEC_RIFSC(10)),1738 STM32_GATE_CFG(CK_KER_TIM13, ck_ker_tim13, SEC_RIFSC(11)),1739 STM32_GATE_CFG(CK_KER_TIM14, ck_ker_tim14, SEC_RIFSC(12)),1740 STM32_GATE_CFG(CK_KER_TIM1, ck_ker_tim1, SEC_RIFSC(0)),1741 STM32_GATE_CFG(CK_KER_TIM8, ck_ker_tim8, SEC_RIFSC(7)),1742 STM32_GATE_CFG(CK_KER_TIM15, ck_ker_tim15, SEC_RIFSC(13)),1743 STM32_GATE_CFG(CK_KER_TIM16, ck_ker_tim16, SEC_RIFSC(14)),1744 STM32_GATE_CFG(CK_KER_TIM17, ck_ker_tim17, SEC_RIFSC(15)),1745 STM32_GATE_CFG(CK_KER_TIM20, ck_ker_tim20, SEC_RIFSC(16)),1746 STM32_GATE_CFG(CK_KER_LPTIM1, ck_ker_lptim1, SEC_RIFSC(17)),1747 STM32_GATE_CFG(CK_KER_LPTIM2, ck_ker_lptim2, SEC_RIFSC(18)),1748 STM32_GATE_CFG(CK_KER_USART2, ck_ker_usart2, SEC_RIFSC(32)),1749 STM32_GATE_CFG(CK_KER_UART4, ck_ker_uart4, SEC_RIFSC(34)),1750 STM32_GATE_CFG(CK_KER_USART3, ck_ker_usart3, SEC_RIFSC(33)),1751 STM32_GATE_CFG(CK_KER_UART5, ck_ker_uart5, SEC_RIFSC(35)),1752 STM32_GATE_CFG(CK_KER_SPI2, ck_ker_spi2, SEC_RIFSC(23)),1753 STM32_GATE_CFG(CK_KER_SPI3, ck_ker_spi3, SEC_RIFSC(24)),1754 STM32_GATE_CFG(CK_KER_SPDIFRX, ck_ker_spdifrx, SEC_RIFSC(30)),1755 STM32_GATE_CFG(CK_KER_I2C1, ck_ker_i2c1, SEC_RIFSC(41)),1756 STM32_GATE_CFG(CK_KER_I2C2, ck_ker_i2c2, SEC_RIFSC(42)),1757 STM32_GATE_CFG(CK_KER_I3C1, ck_ker_i3c1, SEC_RIFSC(114)),1758 STM32_GATE_CFG(CK_KER_I3C2, ck_ker_i3c2, SEC_RIFSC(115)),1759 STM32_GATE_CFG(CK_KER_I2C3, ck_ker_i2c3, SEC_RIFSC(43)),1760 STM32_GATE_CFG(CK_KER_I2C5, ck_ker_i2c5, SEC_RIFSC(45)),1761 STM32_GATE_CFG(CK_KER_I3C3, ck_ker_i3c3, SEC_RIFSC(116)),1762 STM32_GATE_CFG(CK_KER_I2C4, ck_ker_i2c4, SEC_RIFSC(44)),1763 STM32_GATE_CFG(CK_KER_I2C6, ck_ker_i2c6, SEC_RIFSC(46)),1764 STM32_GATE_CFG(CK_KER_I2C7, ck_ker_i2c7, SEC_RIFSC(47)),1765 STM32_GATE_CFG(CK_KER_SPI1, ck_ker_spi1, SEC_RIFSC(22)),1766 STM32_GATE_CFG(CK_KER_SPI4, ck_ker_spi4, SEC_RIFSC(25)),1767 STM32_GATE_CFG(CK_KER_SPI5, ck_ker_spi5, SEC_RIFSC(26)),1768 STM32_GATE_CFG(CK_KER_SPI6, ck_ker_spi6, SEC_RIFSC(27)),1769 STM32_GATE_CFG(CK_KER_SPI7, ck_ker_spi7, SEC_RIFSC(28)),1770 STM32_GATE_CFG(CK_KER_USART1, ck_ker_usart1, SEC_RIFSC(31)),1771 STM32_GATE_CFG(CK_KER_USART6, ck_ker_usart6, SEC_RIFSC(36)),1772 STM32_GATE_CFG(CK_KER_UART7, ck_ker_uart7, SEC_RIFSC(37)),1773 STM32_GATE_CFG(CK_KER_UART8, ck_ker_uart8, SEC_RIFSC(38)),1774 STM32_GATE_CFG(CK_KER_UART9, ck_ker_uart9, SEC_RIFSC(39)),1775 STM32_GATE_CFG(CK_KER_MDF1, ck_ker_mdf1, SEC_RIFSC(54)),1776 STM32_GATE_CFG(CK_KER_SAI1, ck_ker_sai1, SEC_RIFSC(49)),1777 STM32_GATE_CFG(CK_KER_SAI2, ck_ker_sai2, SEC_RIFSC(50)),1778 STM32_GATE_CFG(CK_KER_SAI3, ck_ker_sai3, SEC_RIFSC(51)),1779 STM32_GATE_CFG(CK_KER_SAI4, ck_ker_sai4, SEC_RIFSC(52)),1780 STM32_GATE_CFG(CK_KER_FDCAN, ck_ker_fdcan, SEC_RIFSC(56)),1781 STM32_GATE_CFG(CK_KER_CSI, ck_ker_csi, SEC_RIFSC(86)),1782 STM32_GATE_CFG(CK_KER_CSITXESC, ck_ker_csitxesc, SEC_RIFSC(86)),1783 STM32_GATE_CFG(CK_KER_CSIPHY, ck_ker_csiphy, SEC_RIFSC(86)),1784 STM32_GATE_CFG(CK_KER_USBTC, ck_ker_usbtc, SEC_RIFSC(69)),1785 STM32_GATE_CFG(CK_KER_I3C4, ck_ker_i3c4, SEC_RIFSC(117)),1786 STM32_GATE_CFG(CK_KER_SPI8, ck_ker_spi8, SEC_RIFSC(29)),1787 STM32_GATE_CFG(CK_KER_I2C8, ck_ker_i2c8, SEC_RIFSC(48)),1788 STM32_GATE_CFG(CK_KER_LPUART1, ck_ker_lpuart1, SEC_RIFSC(40)),1789 STM32_GATE_CFG(CK_KER_LPTIM3, ck_ker_lptim3, SEC_RIFSC(19)),1790 STM32_GATE_CFG(CK_KER_LPTIM4, ck_ker_lptim4, SEC_RIFSC(20)),1791 STM32_GATE_CFG(CK_KER_LPTIM5, ck_ker_lptim5, SEC_RIFSC(21)),1792 STM32_GATE_CFG(CK_KER_ADF1, ck_ker_adf1, SEC_RIFSC(55)),1793 STM32_GATE_CFG(CK_KER_SDMMC1, ck_ker_sdmmc1, SEC_RIFSC(76)),1794 STM32_GATE_CFG(CK_KER_SDMMC2, ck_ker_sdmmc2, SEC_RIFSC(77)),1795 STM32_GATE_CFG(CK_KER_SDMMC3, ck_ker_sdmmc3, SEC_RIFSC(78)),1796 STM32_GATE_CFG(CK_KER_ETH1, ck_ker_eth1, SEC_RIFSC(60)),1797 STM32_GATE_CFG(CK_ETH1_STP, ck_ker_eth1stp, SEC_RIFSC(60)),1798 STM32_GATE_CFG(CK_KER_ETHSW, ck_ker_ethsw, SEC_RIFSC(70)),1799 STM32_GATE_CFG(CK_KER_ETH2, ck_ker_eth2, SEC_RIFSC(61)),1800 STM32_GATE_CFG(CK_ETH2_STP, ck_ker_eth2stp, SEC_RIFSC(61)),1801 STM32_GATE_CFG(CK_KER_ETH1PTP, ck_ker_eth1ptp, SEC_RIFSC(60)),1802 STM32_GATE_CFG(CK_KER_ETH2PTP, ck_ker_eth2ptp, SEC_RIFSC(61)),1803 STM32_GATE_CFG(CK_BUS_GPU, ck_icn_m_gpu, SEC_RIFSC(79)),1804 STM32_GATE_CFG(CK_KER_GPU, ck_ker_gpu, SEC_RIFSC(79)),1805 STM32_GATE_CFG(CK_KER_ETHSWREF, ck_ker_ethswref, SEC_RIFSC(70)),1806 STM32_GATE_CFG(CK_BUS_ETHSWACMCFG, ck_icn_p_ethsw_acm_cfg, SEC_RIFSC(71)),1807 STM32_GATE_CFG(CK_BUS_ETHSWACMMSG, ck_icn_p_ethsw_acm_msg, SEC_RIFSC(72)),1808 STM32_GATE_CFG(CK_ETH1_MAC, ck_ker_eth1mac, SEC_RIFSC(60)),1809 STM32_GATE_CFG(CK_ETH1_TX, ck_ker_eth1tx, SEC_RIFSC(60)),1810 STM32_GATE_CFG(CK_ETH1_RX, ck_ker_eth1rx, SEC_RIFSC(60)),1811 STM32_GATE_CFG(CK_ETH2_MAC, ck_ker_eth2mac, SEC_RIFSC(61)),1812 STM32_GATE_CFG(CK_ETH2_TX, ck_ker_eth2tx, SEC_RIFSC(61)),1813 STM32_GATE_CFG(CK_ETH2_RX, ck_ker_eth2rx, SEC_RIFSC(61)),1814 STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, MP25_RIF_RCC_MCO1),1815 STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, MP25_RIF_RCC_MCO1),1816 STM32_COMPOSITE_CFG(CK_KER_ADC12, ck_ker_adc12, SEC_RIFSC(58)),1817 STM32_COMPOSITE_CFG(CK_KER_ADC3, ck_ker_adc3, SEC_RIFSC(59)),1818 STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SEC_RIFSC(63)),1819 STM32_GATE_CFG(CK_KER_USB2PHY2, ck_ker_usb2phy2, SEC_RIFSC(63)),1820 STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SEC_RIFSC(63)),1821 STM32_COMPOSITE_CFG(CK_KER_USB3PCIEPHY, ck_ker_usb3pciephy, SEC_RIFSC(67)),1822 STM32_COMPOSITE_CFG(CK_KER_DSIBLANE, clk_lanebyte, SEC_RIFSC(81)),1823 STM32_COMPOSITE_CFG(CK_KER_DSIPHY, clk_phy_dsi, SEC_RIFSC(81)),1824 STM32_COMPOSITE_CFG(CK_KER_LVDSPHY, ck_ker_lvdsphy, SEC_RIFSC(84)),1825 STM32_COMPOSITE_CFG(CK_KER_DTS, ck_ker_dts, SEC_RIFSC(107)),1826 STM32_GATE_CFG(CK_KER_LTDC, ck_ker_ltdc, SEC_RIFSC(80)),1827};1828 1829#define RESET_MP25(id, _offset, _bit_idx, _set_clr) \1830 [id] = &(struct stm32_reset_cfg){ \1831 .offset = (_offset), \1832 .bit_idx = (_bit_idx), \1833 .set_clr = (_set_clr), \1834 }1835 1836static const struct stm32_reset_cfg *stm32mp25_reset_cfg[STM32MP25_LAST_RESET] = {1837 RESET_MP25(TIM1_R, RCC_TIM1CFGR, 0, 0),1838 RESET_MP25(TIM2_R, RCC_TIM2CFGR, 0, 0),1839 RESET_MP25(TIM3_R, RCC_TIM3CFGR, 0, 0),1840 RESET_MP25(TIM4_R, RCC_TIM4CFGR, 0, 0),1841 RESET_MP25(TIM5_R, RCC_TIM5CFGR, 0, 0),1842 RESET_MP25(TIM6_R, RCC_TIM6CFGR, 0, 0),1843 RESET_MP25(TIM7_R, RCC_TIM7CFGR, 0, 0),1844 RESET_MP25(TIM8_R, RCC_TIM8CFGR, 0, 0),1845 RESET_MP25(TIM10_R, RCC_TIM10CFGR, 0, 0),1846 RESET_MP25(TIM11_R, RCC_TIM11CFGR, 0, 0),1847 RESET_MP25(TIM12_R, RCC_TIM12CFGR, 0, 0),1848 RESET_MP25(TIM13_R, RCC_TIM13CFGR, 0, 0),1849 RESET_MP25(TIM14_R, RCC_TIM14CFGR, 0, 0),1850 RESET_MP25(TIM15_R, RCC_TIM15CFGR, 0, 0),1851 RESET_MP25(TIM16_R, RCC_TIM16CFGR, 0, 0),1852 RESET_MP25(TIM17_R, RCC_TIM17CFGR, 0, 0),1853 RESET_MP25(TIM20_R, RCC_TIM20CFGR, 0, 0),1854 RESET_MP25(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0),1855 RESET_MP25(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0),1856 RESET_MP25(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0),1857 RESET_MP25(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0),1858 RESET_MP25(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0),1859 RESET_MP25(SPI1_R, RCC_SPI1CFGR, 0, 0),1860 RESET_MP25(SPI2_R, RCC_SPI2CFGR, 0, 0),1861 RESET_MP25(SPI3_R, RCC_SPI3CFGR, 0, 0),1862 RESET_MP25(SPI4_R, RCC_SPI4CFGR, 0, 0),1863 RESET_MP25(SPI5_R, RCC_SPI5CFGR, 0, 0),1864 RESET_MP25(SPI6_R, RCC_SPI6CFGR, 0, 0),1865 RESET_MP25(SPI7_R, RCC_SPI7CFGR, 0, 0),1866 RESET_MP25(SPI8_R, RCC_SPI8CFGR, 0, 0),1867 RESET_MP25(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0),1868 RESET_MP25(USART1_R, RCC_USART1CFGR, 0, 0),1869 RESET_MP25(USART2_R, RCC_USART2CFGR, 0, 0),1870 RESET_MP25(USART3_R, RCC_USART3CFGR, 0, 0),1871 RESET_MP25(UART4_R, RCC_UART4CFGR, 0, 0),1872 RESET_MP25(UART5_R, RCC_UART5CFGR, 0, 0),1873 RESET_MP25(USART6_R, RCC_USART6CFGR, 0, 0),1874 RESET_MP25(UART7_R, RCC_UART7CFGR, 0, 0),1875 RESET_MP25(UART8_R, RCC_UART8CFGR, 0, 0),1876 RESET_MP25(UART9_R, RCC_UART9CFGR, 0, 0),1877 RESET_MP25(LPUART1_R, RCC_LPUART1CFGR, 0, 0),1878 RESET_MP25(IS2M_R, RCC_IS2MCFGR, 0, 0),1879 RESET_MP25(I2C1_R, RCC_I2C1CFGR, 0, 0),1880 RESET_MP25(I2C2_R, RCC_I2C2CFGR, 0, 0),1881 RESET_MP25(I2C3_R, RCC_I2C3CFGR, 0, 0),1882 RESET_MP25(I2C4_R, RCC_I2C4CFGR, 0, 0),1883 RESET_MP25(I2C5_R, RCC_I2C5CFGR, 0, 0),1884 RESET_MP25(I2C6_R, RCC_I2C6CFGR, 0, 0),1885 RESET_MP25(I2C7_R, RCC_I2C7CFGR, 0, 0),1886 RESET_MP25(I2C8_R, RCC_I2C8CFGR, 0, 0),1887 RESET_MP25(SAI1_R, RCC_SAI1CFGR, 0, 0),1888 RESET_MP25(SAI2_R, RCC_SAI2CFGR, 0, 0),1889 RESET_MP25(SAI3_R, RCC_SAI3CFGR, 0, 0),1890 RESET_MP25(SAI4_R, RCC_SAI4CFGR, 0, 0),1891 RESET_MP25(MDF1_R, RCC_MDF1CFGR, 0, 0),1892 RESET_MP25(MDF2_R, RCC_ADF1CFGR, 0, 0),1893 RESET_MP25(FDCAN_R, RCC_FDCANCFGR, 0, 0),1894 RESET_MP25(HDP_R, RCC_HDPCFGR, 0, 0),1895 RESET_MP25(ADC12_R, RCC_ADC12CFGR, 0, 0),1896 RESET_MP25(ADC3_R, RCC_ADC3CFGR, 0, 0),1897 RESET_MP25(ETH1_R, RCC_ETH1CFGR, 0, 0),1898 RESET_MP25(ETH2_R, RCC_ETH2CFGR, 0, 0),1899 RESET_MP25(USBH_R, RCC_USBHCFGR, 0, 0),1900 RESET_MP25(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0),1901 RESET_MP25(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0),1902 RESET_MP25(USB3DR_R, RCC_USB3DRCFGR, 0, 0),1903 RESET_MP25(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0, 0),1904 RESET_MP25(USBTC_R, RCC_USBTCCFGR, 0, 0),1905 RESET_MP25(ETHSW_R, RCC_ETHSWCFGR, 0, 0),1906 RESET_MP25(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0),1907 RESET_MP25(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0),1908 RESET_MP25(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0),1909 RESET_MP25(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0),1910 RESET_MP25(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0),1911 RESET_MP25(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0),1912 RESET_MP25(GPU_R, RCC_GPUCFGR, 0, 0),1913 RESET_MP25(LTDC_R, RCC_LTDCCFGR, 0, 0),1914 RESET_MP25(DSI_R, RCC_DSICFGR, 0, 0),1915 RESET_MP25(LVDS_R, RCC_LVDSCFGR, 0, 0),1916 RESET_MP25(CSI_R, RCC_CSICFGR, 0, 0),1917 RESET_MP25(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0),1918 RESET_MP25(CCI_R, RCC_CCICFGR, 0, 0),1919 RESET_MP25(VDEC_R, RCC_VDECCFGR, 0, 0),1920 RESET_MP25(VENC_R, RCC_VENCCFGR, 0, 0),1921 RESET_MP25(WWDG1_R, RCC_WWDG1CFGR, 0, 0),1922 RESET_MP25(WWDG2_R, RCC_WWDG2CFGR, 0, 0),1923 RESET_MP25(VREF_R, RCC_VREFCFGR, 0, 0),1924 RESET_MP25(DTS_R, RCC_DTSCFGR, 0, 0),1925 RESET_MP25(CRC_R, RCC_CRCCFGR, 0, 0),1926 RESET_MP25(SERC_R, RCC_SERCCFGR, 0, 0),1927 RESET_MP25(OSPIIOM_R, RCC_OSPIIOMCFGR, 0, 0),1928 RESET_MP25(I3C1_R, RCC_I3C1CFGR, 0, 0),1929 RESET_MP25(I3C2_R, RCC_I3C2CFGR, 0, 0),1930 RESET_MP25(I3C3_R, RCC_I3C3CFGR, 0, 0),1931 RESET_MP25(I3C4_R, RCC_I3C4CFGR, 0, 0),1932 RESET_MP25(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1),1933 RESET_MP25(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1),1934 RESET_MP25(RNG_R, RCC_RNGCFGR, 0, 0),1935 RESET_MP25(PKA_R, RCC_PKACFGR, 0, 0),1936 RESET_MP25(SAES_R, RCC_SAESCFGR, 0, 0),1937 RESET_MP25(HASH_R, RCC_HASHCFGR, 0, 0),1938 RESET_MP25(CRYP1_R, RCC_CRYP1CFGR, 0, 0),1939 RESET_MP25(CRYP2_R, RCC_CRYP2CFGR, 0, 0),1940 RESET_MP25(PCIE_R, RCC_PCIECFGR, 0, 0),1941};1942 1943static u16 stm32mp25_cpt_gate[GATE_NB];1944 1945static struct clk_stm32_clock_data stm32mp25_clock_data = {1946 .gate_cpt = stm32mp25_cpt_gate,1947 .gates = stm32mp25_gates,1948 .muxes = stm32mp25_muxes,1949};1950 1951static struct clk_stm32_reset_data stm32mp25_reset_data = {1952 .reset_lines = stm32mp25_reset_cfg,1953 .nr_lines = ARRAY_SIZE(stm32mp25_reset_cfg),1954};1955 1956static const struct stm32_rcc_match_data stm32mp25_data = {1957 .tab_clocks = stm32mp25_clock_cfg,1958 .num_clocks = ARRAY_SIZE(stm32mp25_clock_cfg),1959 .maxbinding = STM32MP25_LAST_CLK,1960 .clock_data = &stm32mp25_clock_data,1961 .reset_data = &stm32mp25_reset_data,1962 .check_security = &stm32mp25_check_security,1963};1964 1965static const struct of_device_id stm32mp25_match_data[] = {1966 { .compatible = "st,stm32mp25-rcc", .data = &stm32mp25_data, },1967 { }1968};1969MODULE_DEVICE_TABLE(of, stm32mp25_match_data);1970 1971static int stm32mp25_rcc_clocks_probe(struct platform_device *pdev)1972{1973 struct device *dev = &pdev->dev;1974 void __iomem *base;1975 int ret;1976 1977 base = devm_platform_ioremap_resource(pdev, 0);1978 if (IS_ERR(base))1979 return PTR_ERR(base);1980 1981 ret = stm32_firewall_get_firewall(dev->of_node, &firewall, 1);1982 if (ret)1983 return ret;1984 1985 return stm32_rcc_init(dev, stm32mp25_match_data, base);1986}1987 1988static struct platform_driver stm32mp25_rcc_clocks_driver = {1989 .driver = {1990 .name = "stm32mp25_rcc",1991 .of_match_table = stm32mp25_match_data,1992 },1993 .probe = stm32mp25_rcc_clocks_probe,1994};1995 1996static int __init stm32mp25_clocks_init(void)1997{1998 return platform_driver_register(&stm32mp25_rcc_clocks_driver);1999}2000 2001core_initcall(stm32mp25_clocks_init);2002