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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.4 * Copyright (c) 2017 Maxime Ripard.5 * Copyright (c) 2017 Jonathan Liu.6 */7 8#include <linux/clk-provider.h>9#include <linux/io.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/platform_device.h>13 14#include "ccu_common.h"15#include "ccu_reset.h"16 17#include "ccu_div.h"18#include "ccu_gate.h"19#include "ccu_mp.h"20#include "ccu_mult.h"21#include "ccu_nk.h"22#include "ccu_nkm.h"23#include "ccu_nkmp.h"24#include "ccu_nm.h"25#include "ccu_phase.h"26#include "ccu_sdm.h"27 28#include "ccu-sun4i-a10.h"29 30static struct ccu_nkmp pll_core_clk = {31 .enable = BIT(31),32 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),33 .k = _SUNXI_CCU_MULT(4, 2),34 .m = _SUNXI_CCU_DIV(0, 2),35 .p = _SUNXI_CCU_DIV(16, 2),36 .common = {37 .reg = 0x000,38 .hw.init = CLK_HW_INIT("pll-core",39 "hosc",40 &ccu_nkmp_ops,41 0),42 },43};44 45/*46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from47 * the base (2x, 4x and 8x), and one variable divider (the one true48 * pll audio).49 *50 * With sigma-delta modulation for fractional-N on the audio PLL,51 * we have to use specific dividers. This means the variable divider52 * can no longer be used, as the audio codec requests the exact clock53 * rates we support through this mechanism. So we now hard code the54 * variable divider to 1. This means the clock rates will no longer55 * match the clock names.56 */57#define SUN4I_PLL_AUDIO_REG 0x00858 59static struct ccu_sdm_setting pll_audio_sdm_table[] = {60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },62};63 64static struct ccu_nm pll_audio_base_clk = {65 .enable = BIT(31),66 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),68 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,69 0x00c, BIT(31)),70 .common = {71 .reg = 0x008,72 .features = CCU_FEATURE_SIGMA_DELTA_MOD,73 .hw.init = CLK_HW_INIT("pll-audio-base",74 "hosc",75 &ccu_nm_ops,76 0),77 },78 79};80 81static struct ccu_mult pll_video0_clk = {82 .enable = BIT(31),83 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),84 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),85 270000000, 297000000),86 .common = {87 .reg = 0x010,88 .features = (CCU_FEATURE_FRACTIONAL |89 CCU_FEATURE_ALL_PREDIV),90 .prediv = 8,91 .hw.init = CLK_HW_INIT("pll-video0",92 "hosc",93 &ccu_mult_ops,94 0),95 },96};97 98static struct ccu_nkmp pll_ve_sun4i_clk = {99 .enable = BIT(31),100 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),101 .k = _SUNXI_CCU_MULT(4, 2),102 .m = _SUNXI_CCU_DIV(0, 2),103 .p = _SUNXI_CCU_DIV(16, 2),104 .common = {105 .reg = 0x018,106 .hw.init = CLK_HW_INIT("pll-ve",107 "hosc",108 &ccu_nkmp_ops,109 0),110 },111};112 113static struct ccu_nk pll_ve_sun7i_clk = {114 .enable = BIT(31),115 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),116 .k = _SUNXI_CCU_MULT(4, 2),117 .common = {118 .reg = 0x018,119 .hw.init = CLK_HW_INIT("pll-ve",120 "hosc",121 &ccu_nk_ops,122 0),123 },124};125 126static struct ccu_nk pll_ddr_base_clk = {127 .enable = BIT(31),128 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),129 .k = _SUNXI_CCU_MULT(4, 2),130 .common = {131 .reg = 0x020,132 .hw.init = CLK_HW_INIT("pll-ddr-base",133 "hosc",134 &ccu_nk_ops,135 0),136 },137};138 139static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,140 CLK_IS_CRITICAL);141 142static struct ccu_div pll_ddr_other_clk = {143 .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),144 .common = {145 .reg = 0x020,146 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",147 &ccu_div_ops,148 0),149 },150};151 152static struct ccu_nk pll_periph_base_clk = {153 .enable = BIT(31),154 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),155 .k = _SUNXI_CCU_MULT(4, 2),156 .common = {157 .reg = 0x028,158 .hw.init = CLK_HW_INIT("pll-periph-base",159 "hosc",160 &ccu_nk_ops,161 0),162 },163};164 165static CLK_FIXED_FACTOR_HW(pll_periph_clk, "pll-periph",166 &pll_periph_base_clk.common.hw,167 2, 1, CLK_SET_RATE_PARENT);168 169/* Not documented on A10 */170static struct ccu_div pll_periph_sata_clk = {171 .enable = BIT(14),172 .div = _SUNXI_CCU_DIV(0, 2),173 .fixed_post_div = 6,174 .common = {175 .reg = 0x028,176 .features = CCU_FEATURE_FIXED_POSTDIV,177 .hw.init = CLK_HW_INIT("pll-periph-sata",178 "pll-periph-base",179 &ccu_div_ops, 0),180 },181};182 183static struct ccu_mult pll_video1_clk = {184 .enable = BIT(31),185 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),186 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),187 270000000, 297000000),188 .common = {189 .reg = 0x030,190 .features = (CCU_FEATURE_FRACTIONAL |191 CCU_FEATURE_ALL_PREDIV),192 .prediv = 8,193 .hw.init = CLK_HW_INIT("pll-video1",194 "hosc",195 &ccu_mult_ops,196 0),197 },198};199 200/* Not present on A10 */201static struct ccu_nk pll_gpu_clk = {202 .enable = BIT(31),203 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),204 .k = _SUNXI_CCU_MULT(4, 2),205 .common = {206 .reg = 0x040,207 .hw.init = CLK_HW_INIT("pll-gpu",208 "hosc",209 &ccu_nk_ops,210 0),211 },212};213 214static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);215 216static const char *const cpu_parents[] = { "osc32k", "hosc",217 "pll-core", "pll-periph" };218static const struct ccu_mux_fixed_prediv cpu_predivs[] = {219 { .index = 3, .div = 3, },220};221 222#define SUN4I_AHB_REG 0x054223static struct ccu_mux cpu_clk = {224 .mux = {225 .shift = 16,226 .width = 2,227 .fixed_predivs = cpu_predivs,228 .n_predivs = ARRAY_SIZE(cpu_predivs),229 },230 .common = {231 .reg = 0x054,232 .features = CCU_FEATURE_FIXED_PREDIV,233 .hw.init = CLK_HW_INIT_PARENTS("cpu",234 cpu_parents,235 &ccu_mux_ops,236 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),237 }238};239 240static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);241 242static struct ccu_div ahb_sun4i_clk = {243 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),244 .common = {245 .reg = 0x054,246 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),247 },248};249 250static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",251 "pll-periph" };252static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {253 { .index = 1, .div = 2, },254 { /* Sentinel */ },255};256static struct ccu_div ahb_sun7i_clk = {257 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),258 .mux = {259 .shift = 6,260 .width = 2,261 .fixed_predivs = ahb_sun7i_predivs,262 .n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),263 },264 265 .common = {266 .reg = 0x054,267 .hw.init = CLK_HW_INIT_PARENTS("ahb",268 ahb_sun7i_parents,269 &ccu_div_ops,270 0),271 },272};273 274static struct clk_div_table apb0_div_table[] = {275 { .val = 0, .div = 2 },276 { .val = 1, .div = 2 },277 { .val = 2, .div = 4 },278 { .val = 3, .div = 8 },279 { /* Sentinel */ },280};281static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",282 0x054, 8, 2, apb0_div_table, 0);283 284static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };285static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,286 0, 5, /* M */287 16, 2, /* P */288 24, 2, /* mux */289 0);290 291/* Not present on A20 */292static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",293 0x05c, BIT(31), 0);294 295static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",296 0x060, BIT(0), 0);297static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",298 0x060, BIT(1), 0);299static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",300 0x060, BIT(2), 0);301static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",302 0x060, BIT(3), 0);303static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",304 0x060, BIT(4), 0);305static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",306 0x060, BIT(5), 0);307static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",308 0x060, BIT(6), 0);309static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",310 0x060, BIT(7), 0);311static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",312 0x060, BIT(8), 0);313static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",314 0x060, BIT(9), 0);315static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",316 0x060, BIT(10), 0);317static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",318 0x060, BIT(11), 0);319static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",320 0x060, BIT(12), 0);321static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",322 0x060, BIT(13), 0);323static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",324 0x060, BIT(14), CLK_IS_CRITICAL);325 326static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",327 0x060, BIT(16), 0);328static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",329 0x060, BIT(17), 0);330static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",331 0x060, BIT(18), 0);332static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",333 0x060, BIT(20), 0);334static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",335 0x060, BIT(21), 0);336static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",337 0x060, BIT(22), 0);338static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",339 0x060, BIT(23), 0);340static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",341 0x060, BIT(24), 0);342/* Not documented on A20 */343static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",344 0x060, BIT(25), 0);345/* Not present on A20 */346static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",347 0x060, BIT(26), 0);348/* Not present on A10 */349static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",350 0x060, BIT(28), 0);351 352static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",353 0x064, BIT(0), 0);354static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",355 0x064, BIT(1), 0);356static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",357 0x064, BIT(2), 0);358static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",359 0x064, BIT(3), 0);360static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",361 0x064, BIT(4), 0);362static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",363 0x064, BIT(5), 0);364static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",365 0x064, BIT(8), 0);366static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",367 0x064, BIT(9), 0);368/* Not present on A10 */369static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",370 0x064, BIT(10), 0);371static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",372 0x064, BIT(11), 0);373static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",374 0x064, BIT(12), 0);375static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",376 0x064, BIT(13), 0);377static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",378 0x064, BIT(14), 0);379static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",380 0x064, BIT(15), 0);381/* Not present on A10 */382static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",383 0x064, BIT(17), 0);384static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",385 0x064, BIT(18), 0);386static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",387 0x064, BIT(20), 0);388 389static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",390 0x068, BIT(0), 0);391static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",392 0x068, BIT(1), 0);393static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",394 0x068, BIT(2), 0);395static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",396 0x068, BIT(3), 0);397/* Not present on A10 */398static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",399 0x068, BIT(4), 0);400static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",401 0x068, BIT(5), 0);402static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",403 0x068, BIT(6), 0);404static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",405 0x068, BIT(7), 0);406/* Not present on A10 */407static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",408 0x068, BIT(8), 0);409static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",410 0x068, BIT(10), 0);411 412static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",413 0x06c, BIT(0), 0);414static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",415 0x06c, BIT(1), 0);416static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",417 0x06c, BIT(2), 0);418/* Not present on A10 */419static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",420 0x06c, BIT(3), 0);421static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",422 0x06c, BIT(4), 0);423static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",424 0x06c, BIT(5), 0);425static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",426 0x06c, BIT(6), 0);427static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",428 0x06c, BIT(7), 0);429/* Not present on A10 */430static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",431 0x06c, BIT(15), 0);432static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",433 0x06c, BIT(16), 0);434static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",435 0x06c, BIT(17), 0);436static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",437 0x06c, BIT(18), 0);438static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",439 0x06c, BIT(19), 0);440static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",441 0x06c, BIT(20), 0);442static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",443 0x06c, BIT(21), 0);444static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",445 0x06c, BIT(22), 0);446static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",447 0x06c, BIT(23), 0);448 449static const char *const mod0_default_parents[] = { "hosc", "pll-periph",450 "pll-ddr-other" };451static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,452 0, 4, /* M */453 16, 2, /* P */454 24, 2, /* mux */455 BIT(31), /* gate */456 0);457 458/* Undocumented on A10 */459static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,460 0, 4, /* M */461 16, 2, /* P */462 24, 2, /* mux */463 BIT(31), /* gate */464 0);465 466static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,467 0, 4, /* M */468 16, 2, /* P */469 24, 2, /* mux */470 BIT(31), /* gate */471 0);472 473/* MMC output and sample clocks are not present on A10 */474static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",475 0x088, 8, 3, 0);476static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",477 0x088, 20, 3, 0);478 479static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,480 0, 4, /* M */481 16, 2, /* P */482 24, 2, /* mux */483 BIT(31), /* gate */484 0);485 486/* MMC output and sample clocks are not present on A10 */487static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",488 0x08c, 8, 3, 0);489static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",490 0x08c, 20, 3, 0);491 492static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,493 0, 4, /* M */494 16, 2, /* P */495 24, 2, /* mux */496 BIT(31), /* gate */497 0);498 499/* MMC output and sample clocks are not present on A10 */500static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",501 0x090, 8, 3, 0);502static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",503 0x090, 20, 3, 0);504 505static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,506 0, 4, /* M */507 16, 2, /* P */508 24, 2, /* mux */509 BIT(31), /* gate */510 0);511 512/* MMC output and sample clocks are not present on A10 */513static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",514 0x094, 8, 3, 0);515static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",516 0x094, 20, 3, 0);517 518static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,519 0, 4, /* M */520 16, 2, /* P */521 24, 2, /* mux */522 BIT(31), /* gate */523 0);524 525static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,526 0, 4, /* M */527 16, 2, /* P */528 24, 2, /* mux */529 BIT(31), /* gate */530 0);531 532static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,533 0, 4, /* M */534 16, 2, /* P */535 24, 2, /* mux */536 BIT(31), /* gate */537 0);538 539static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,540 0, 4, /* M */541 16, 2, /* P */542 24, 2, /* mux */543 BIT(31), /* gate */544 0);545 546static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,547 0, 4, /* M */548 16, 2, /* P */549 24, 2, /* mux */550 BIT(31), /* gate */551 0);552 553/* Undocumented on A10 */554static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,555 0, 4, /* M */556 16, 2, /* P */557 24, 2, /* mux */558 BIT(31), /* gate */559 0);560 561/* TODO: Check whether A10 actually supports osc32k as 4th parent? */562static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",563 "pll-ddr-other" };564static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,565 0, 4, /* M */566 16, 2, /* P */567 24, 2, /* mux */568 BIT(31), /* gate */569 0);570 571static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,572 0, 4, /* M */573 16, 2, /* P */574 24, 2, /* mux */575 BIT(31), /* gate */576 0);577static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",578 "pll-ddr-other", "osc32k" };579static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,580 0, 4, /* M */581 16, 2, /* P */582 24, 2, /* mux */583 BIT(31), /* gate */584 0);585 586static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,587 0, 4, /* M */588 16, 2, /* P */589 24, 2, /* mux */590 BIT(31), /* gate */591 0);592 593static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",594 "pll-audio-2x", "pll-audio" };595static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,596 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);597 598static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,599 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);600 601/* Undocumented on A10 */602static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,603 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);604 605static const char *const keypad_parents[] = { "hosc", "losc"};606static const u8 keypad_table[] = { 0, 2 };607static struct ccu_mp keypad_clk = {608 .enable = BIT(31),609 .m = _SUNXI_CCU_DIV(0, 5),610 .p = _SUNXI_CCU_DIV(16, 2),611 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),612 .common = {613 .reg = 0x0c4,614 .hw.init = CLK_HW_INIT_PARENTS("keypad",615 keypad_parents,616 &ccu_mp_ops,617 0),618 },619};620 621/*622 * SATA supports external clock as parent via BIT(24) and is probably an623 * optional crystal or oscillator that can be connected to the624 * SATA-CLKM / SATA-CLKP pins.625 */626static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};627static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,628 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);629 630 631static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",632 0x0cc, BIT(6), 0);633static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",634 0x0cc, BIT(7), 0);635static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",636 0x0cc, BIT(8), 0);637 638/* TODO: GPS CLK 0x0d0 */639 640static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,641 0, 4, /* M */642 16, 2, /* P */643 24, 2, /* mux */644 BIT(31), /* gate */645 0);646 647/* Not present on A10 */648static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,649 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);650 651/* Not present on A10 */652static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,653 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);654 655static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",656 0x100, BIT(0), 0);657static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",658 0x100, BIT(1), 0);659static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",660 0x100, BIT(2), 0);661static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",662 0x100, BIT(3), 0);663static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",664 0x100, BIT(4), 0);665static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",666 0x100, BIT(5), 0);667static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",668 0x100, BIT(6), 0);669 670/* Clock seems to be critical only on sun4i */671static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",672 0x100, BIT(15), CLK_IS_CRITICAL);673static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",674 0x100, BIT(24), 0);675static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",676 0x100, BIT(25), 0);677static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",678 0x100, BIT(26), 0);679static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",680 0x100, BIT(27), 0);681static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",682 0x100, BIT(28), 0);683static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",684 0x100, BIT(29), 0);685 686static const char *const de_parents[] = { "pll-video0", "pll-video1",687 "pll-ddr-other" };688static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,689 0x104, 0, 4, 24, 2, BIT(31), 0);690 691static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,692 0x108, 0, 4, 24, 2, BIT(31), 0);693 694static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,695 0x10c, 0, 4, 24, 2, BIT(31), 0);696 697static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,698 0x110, 0, 4, 24, 2, BIT(31), 0);699 700/* Undocumented on A10 */701static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,702 0x114, 0, 4, 24, 2, BIT(31), 0);703 704static const char *const disp_parents[] = { "pll-video0", "pll-video1",705 "pll-video0-2x", "pll-video1-2x" };706static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,707 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);708static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,709 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);710 711static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",712 "pll-ddr-other", "pll-periph" };713 714static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",715 csi_sclk_parents,716 0x120, 0, 4, 24, 2, BIT(31), 0);717 718/* TVD clock setup for A10 */719static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };720static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,721 0x128, 24, 1, BIT(31), 0);722 723/* TVD clock setup for A20 */724static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,725 "tvd-sclk2", tvd_parents,726 0x128,727 0, 4, /* M */728 16, 4, /* P */729 8, 1, /* mux */730 BIT(15), /* gate */731 0);732 733static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",734 0x128, 0, 4, BIT(31), 0);735 736static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",737 disp_parents,738 0x12c, 0, 4, 24, 2, BIT(31),739 CLK_SET_RATE_PARENT);740 741static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,742 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",743 0x12c, 11, 1, BIT(15),744 CLK_SET_RATE_PARENT);745 746static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",747 disp_parents,748 0x130, 0, 4, 24, 2, BIT(31),749 CLK_SET_RATE_PARENT);750 751static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,752 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",753 0x130, 11, 1, BIT(15),754 CLK_SET_RATE_PARENT);755 756static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",757 "pll-video0-2x", "pll-video1-2x"};758static const u8 csi_table[] = { 0, 1, 2, 5, 6};759static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",760 csi_parents, csi_table,761 0x134, 0, 5, 24, 3, BIT(31), 0);762 763static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",764 csi_parents, csi_table,765 0x138, 0, 5, 24, 3, BIT(31), 0);766 767static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);768 769static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",770 0x140, BIT(31), CLK_SET_RATE_PARENT);771 772static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);773 774static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };775static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,776 0x148, 0, 4, 24, 1, BIT(31), 0);777 778static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,779 0x150, 0, 4, 24, 2, BIT(31),780 CLK_SET_RATE_PARENT);781 782static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",783 "pll-ddr-other",784 "pll-video1" };785static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,786 0x154, 0, 4, 24, 2, BIT(31),787 CLK_SET_RATE_PARENT);788 789static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",790 "pll-ddr-other", "pll-video1",791 "pll-gpu" };792static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };793static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",794 gpu_parents_sun7i, gpu_table_sun7i,795 0x154, 0, 4, 24, 3, BIT(31),796 CLK_SET_RATE_PARENT);797 798static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",799 "pll-ddr-other" };800static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,801 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),802 0);803static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",804 "pll-ddr-other" };805static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,806 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),807 CLK_IS_CRITICAL);808 809static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);810 811static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };812static const u8 hdmi1_table[] = { 0, 1};813static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",814 hdmi1_parents, hdmi1_table,815 0x17c, 0, 4, 24, 2, BIT(31),816 CLK_SET_RATE_PARENT);817 818static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };819static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {820 { .index = 0, .div = 750, },821};822 823static struct ccu_mp out_a_clk = {824 .enable = BIT(31),825 .m = _SUNXI_CCU_DIV(8, 5),826 .p = _SUNXI_CCU_DIV(20, 2),827 .mux = {828 .shift = 24,829 .width = 2,830 .fixed_predivs = clk_out_predivs,831 .n_predivs = ARRAY_SIZE(clk_out_predivs),832 },833 .common = {834 .reg = 0x1f0,835 .features = CCU_FEATURE_FIXED_PREDIV,836 .hw.init = CLK_HW_INIT_PARENTS("out-a",837 out_parents,838 &ccu_mp_ops,839 0),840 },841};842static struct ccu_mp out_b_clk = {843 .enable = BIT(31),844 .m = _SUNXI_CCU_DIV(8, 5),845 .p = _SUNXI_CCU_DIV(20, 2),846 .mux = {847 .shift = 24,848 .width = 2,849 .fixed_predivs = clk_out_predivs,850 .n_predivs = ARRAY_SIZE(clk_out_predivs),851 },852 .common = {853 .reg = 0x1f4,854 .features = CCU_FEATURE_FIXED_PREDIV,855 .hw.init = CLK_HW_INIT_PARENTS("out-b",856 out_parents,857 &ccu_mp_ops,858 0),859 },860};861 862static struct ccu_common *sun4i_sun7i_ccu_clks[] = {863 &hosc_clk.common,864 &pll_core_clk.common,865 &pll_audio_base_clk.common,866 &pll_video0_clk.common,867 &pll_ve_sun4i_clk.common,868 &pll_ve_sun7i_clk.common,869 &pll_ddr_base_clk.common,870 &pll_ddr_clk.common,871 &pll_ddr_other_clk.common,872 &pll_periph_base_clk.common,873 &pll_periph_sata_clk.common,874 &pll_video1_clk.common,875 &pll_gpu_clk.common,876 &cpu_clk.common,877 &axi_clk.common,878 &axi_dram_clk.common,879 &ahb_sun4i_clk.common,880 &ahb_sun7i_clk.common,881 &apb0_clk.common,882 &apb1_clk.common,883 &ahb_otg_clk.common,884 &ahb_ehci0_clk.common,885 &ahb_ohci0_clk.common,886 &ahb_ehci1_clk.common,887 &ahb_ohci1_clk.common,888 &ahb_ss_clk.common,889 &ahb_dma_clk.common,890 &ahb_bist_clk.common,891 &ahb_mmc0_clk.common,892 &ahb_mmc1_clk.common,893 &ahb_mmc2_clk.common,894 &ahb_mmc3_clk.common,895 &ahb_ms_clk.common,896 &ahb_nand_clk.common,897 &ahb_sdram_clk.common,898 &ahb_ace_clk.common,899 &ahb_emac_clk.common,900 &ahb_ts_clk.common,901 &ahb_spi0_clk.common,902 &ahb_spi1_clk.common,903 &ahb_spi2_clk.common,904 &ahb_spi3_clk.common,905 &ahb_pata_clk.common,906 &ahb_sata_clk.common,907 &ahb_gps_clk.common,908 &ahb_hstimer_clk.common,909 &ahb_ve_clk.common,910 &ahb_tvd_clk.common,911 &ahb_tve0_clk.common,912 &ahb_tve1_clk.common,913 &ahb_lcd0_clk.common,914 &ahb_lcd1_clk.common,915 &ahb_csi0_clk.common,916 &ahb_csi1_clk.common,917 &ahb_hdmi1_clk.common,918 &ahb_hdmi0_clk.common,919 &ahb_de_be0_clk.common,920 &ahb_de_be1_clk.common,921 &ahb_de_fe0_clk.common,922 &ahb_de_fe1_clk.common,923 &ahb_gmac_clk.common,924 &ahb_mp_clk.common,925 &ahb_gpu_clk.common,926 &apb0_codec_clk.common,927 &apb0_spdif_clk.common,928 &apb0_ac97_clk.common,929 &apb0_i2s0_clk.common,930 &apb0_i2s1_clk.common,931 &apb0_pio_clk.common,932 &apb0_ir0_clk.common,933 &apb0_ir1_clk.common,934 &apb0_i2s2_clk.common,935 &apb0_keypad_clk.common,936 &apb1_i2c0_clk.common,937 &apb1_i2c1_clk.common,938 &apb1_i2c2_clk.common,939 &apb1_i2c3_clk.common,940 &apb1_can_clk.common,941 &apb1_scr_clk.common,942 &apb1_ps20_clk.common,943 &apb1_ps21_clk.common,944 &apb1_i2c4_clk.common,945 &apb1_uart0_clk.common,946 &apb1_uart1_clk.common,947 &apb1_uart2_clk.common,948 &apb1_uart3_clk.common,949 &apb1_uart4_clk.common,950 &apb1_uart5_clk.common,951 &apb1_uart6_clk.common,952 &apb1_uart7_clk.common,953 &nand_clk.common,954 &ms_clk.common,955 &mmc0_clk.common,956 &mmc0_output_clk.common,957 &mmc0_sample_clk.common,958 &mmc1_clk.common,959 &mmc1_output_clk.common,960 &mmc1_sample_clk.common,961 &mmc2_clk.common,962 &mmc2_output_clk.common,963 &mmc2_sample_clk.common,964 &mmc3_clk.common,965 &mmc3_output_clk.common,966 &mmc3_sample_clk.common,967 &ts_clk.common,968 &ss_clk.common,969 &spi0_clk.common,970 &spi1_clk.common,971 &spi2_clk.common,972 &pata_clk.common,973 &ir0_sun4i_clk.common,974 &ir1_sun4i_clk.common,975 &ir0_sun7i_clk.common,976 &ir1_sun7i_clk.common,977 &i2s0_clk.common,978 &ac97_clk.common,979 &spdif_clk.common,980 &keypad_clk.common,981 &sata_clk.common,982 &usb_ohci0_clk.common,983 &usb_ohci1_clk.common,984 &usb_phy_clk.common,985 &spi3_clk.common,986 &i2s1_clk.common,987 &i2s2_clk.common,988 &dram_ve_clk.common,989 &dram_csi0_clk.common,990 &dram_csi1_clk.common,991 &dram_ts_clk.common,992 &dram_tvd_clk.common,993 &dram_tve0_clk.common,994 &dram_tve1_clk.common,995 &dram_out_clk.common,996 &dram_de_fe1_clk.common,997 &dram_de_fe0_clk.common,998 &dram_de_be0_clk.common,999 &dram_de_be1_clk.common,1000 &dram_mp_clk.common,1001 &dram_ace_clk.common,1002 &de_be0_clk.common,1003 &de_be1_clk.common,1004 &de_fe0_clk.common,1005 &de_fe1_clk.common,1006 &de_mp_clk.common,1007 &tcon0_ch0_clk.common,1008 &tcon1_ch0_clk.common,1009 &csi_sclk_clk.common,1010 &tvd_sun4i_clk.common,1011 &tvd_sclk1_sun7i_clk.common,1012 &tvd_sclk2_sun7i_clk.common,1013 &tcon0_ch1_sclk2_clk.common,1014 &tcon0_ch1_clk.common,1015 &tcon1_ch1_sclk2_clk.common,1016 &tcon1_ch1_clk.common,1017 &csi0_clk.common,1018 &csi1_clk.common,1019 &ve_clk.common,1020 &codec_clk.common,1021 &avs_clk.common,1022 &ace_clk.common,1023 &hdmi_clk.common,1024 &gpu_sun4i_clk.common,1025 &gpu_sun7i_clk.common,1026 &mbus_sun4i_clk.common,1027 &mbus_sun7i_clk.common,1028 &hdmi1_slow_clk.common,1029 &hdmi1_clk.common,1030 &out_a_clk.common,1031 &out_b_clk.common1032};1033 1034static const struct clk_hw *clk_parent_pll_audio[] = {1035 &pll_audio_base_clk.common.hw1036};1037 1038/* Post-divider for pll-audio is hardcoded to 1 */1039static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",1040 clk_parent_pll_audio,1041 1, 1, CLK_SET_RATE_PARENT);1042static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",1043 clk_parent_pll_audio,1044 2, 1, CLK_SET_RATE_PARENT);1045static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",1046 clk_parent_pll_audio,1047 1, 1, CLK_SET_RATE_PARENT);1048static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",1049 clk_parent_pll_audio,1050 1, 2, CLK_SET_RATE_PARENT);1051static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",1052 &pll_video0_clk.common.hw,1053 1, 2, CLK_SET_RATE_PARENT);1054static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",1055 &pll_video1_clk.common.hw,1056 1, 2, CLK_SET_RATE_PARENT);1057 1058 1059static struct clk_hw_onecell_data sun4i_a10_hw_clks = {1060 .hws = {1061 [CLK_HOSC] = &hosc_clk.common.hw,1062 [CLK_PLL_CORE] = &pll_core_clk.common.hw,1063 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,1064 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,1065 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,1066 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,1067 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,1068 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,1069 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,1070 [CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,1071 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,1072 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,1073 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,1074 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,1075 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,1076 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,1077 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,1078 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,1079 [CLK_CPU] = &cpu_clk.common.hw,1080 [CLK_AXI] = &axi_clk.common.hw,1081 [CLK_AXI_DRAM] = &axi_dram_clk.common.hw,1082 [CLK_AHB] = &ahb_sun4i_clk.common.hw,1083 [CLK_APB0] = &apb0_clk.common.hw,1084 [CLK_APB1] = &apb1_clk.common.hw,1085 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,1086 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,1087 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,1088 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,1089 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,1090 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,1091 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,1092 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,1093 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,1094 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,1095 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,1096 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,1097 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,1098 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,1099 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,1100 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,1101 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,1102 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,1103 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,1104 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,1105 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,1106 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,1107 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,1108 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,1109 [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,1110 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,1111 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,1112 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,1113 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,1114 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,1115 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,1116 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,1117 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,1118 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,1119 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,1120 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,1121 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,1122 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,1123 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,1124 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,1125 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,1126 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,1127 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,1128 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,1129 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,1130 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,1131 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,1132 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,1133 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,1134 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,1135 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,1136 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,1137 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,1138 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,1139 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,1140 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,1141 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,1142 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,1143 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,1144 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,1145 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,1146 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,1147 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,1148 [CLK_NAND] = &nand_clk.common.hw,1149 [CLK_MS] = &ms_clk.common.hw,1150 [CLK_MMC0] = &mmc0_clk.common.hw,1151 [CLK_MMC1] = &mmc1_clk.common.hw,1152 [CLK_MMC2] = &mmc2_clk.common.hw,1153 [CLK_MMC3] = &mmc3_clk.common.hw,1154 [CLK_TS] = &ts_clk.common.hw,1155 [CLK_SS] = &ss_clk.common.hw,1156 [CLK_SPI0] = &spi0_clk.common.hw,1157 [CLK_SPI1] = &spi1_clk.common.hw,1158 [CLK_SPI2] = &spi2_clk.common.hw,1159 [CLK_PATA] = &pata_clk.common.hw,1160 [CLK_IR0] = &ir0_sun4i_clk.common.hw,1161 [CLK_IR1] = &ir1_sun4i_clk.common.hw,1162 [CLK_I2S0] = &i2s0_clk.common.hw,1163 [CLK_AC97] = &ac97_clk.common.hw,1164 [CLK_SPDIF] = &spdif_clk.common.hw,1165 [CLK_KEYPAD] = &keypad_clk.common.hw,1166 [CLK_SATA] = &sata_clk.common.hw,1167 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,1168 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,1169 [CLK_USB_PHY] = &usb_phy_clk.common.hw,1170 /* CLK_GPS is unimplemented */1171 [CLK_SPI3] = &spi3_clk.common.hw,1172 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,1173 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,1174 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,1175 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,1176 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,1177 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,1178 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,1179 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,1180 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,1181 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,1182 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,1183 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,1184 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,1185 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,1186 [CLK_DE_BE0] = &de_be0_clk.common.hw,1187 [CLK_DE_BE1] = &de_be1_clk.common.hw,1188 [CLK_DE_FE0] = &de_fe0_clk.common.hw,1189 [CLK_DE_FE1] = &de_fe1_clk.common.hw,1190 [CLK_DE_MP] = &de_mp_clk.common.hw,1191 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,1192 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,1193 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,1194 [CLK_TVD] = &tvd_sun4i_clk.common.hw,1195 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,1196 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,1197 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,1198 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,1199 [CLK_CSI0] = &csi0_clk.common.hw,1200 [CLK_CSI1] = &csi1_clk.common.hw,1201 [CLK_VE] = &ve_clk.common.hw,1202 [CLK_CODEC] = &codec_clk.common.hw,1203 [CLK_AVS] = &avs_clk.common.hw,1204 [CLK_ACE] = &ace_clk.common.hw,1205 [CLK_HDMI] = &hdmi_clk.common.hw,1206 [CLK_GPU] = &gpu_sun7i_clk.common.hw,1207 [CLK_MBUS] = &mbus_sun4i_clk.common.hw,1208 },1209 .num = CLK_NUMBER_SUN4I,1210};1211static struct clk_hw_onecell_data sun7i_a20_hw_clks = {1212 .hws = {1213 [CLK_HOSC] = &hosc_clk.common.hw,1214 [CLK_PLL_CORE] = &pll_core_clk.common.hw,1215 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,1216 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,1217 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,1218 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,1219 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,1220 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,1221 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,1222 [CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,1223 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,1224 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,1225 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,1226 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,1227 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,1228 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,1229 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,1230 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,1231 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,1232 [CLK_CPU] = &cpu_clk.common.hw,1233 [CLK_AXI] = &axi_clk.common.hw,1234 [CLK_AHB] = &ahb_sun7i_clk.common.hw,1235 [CLK_APB0] = &apb0_clk.common.hw,1236 [CLK_APB1] = &apb1_clk.common.hw,1237 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,1238 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,1239 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,1240 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,1241 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,1242 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,1243 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,1244 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,1245 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,1246 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,1247 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,1248 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,1249 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,1250 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,1251 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,1252 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,1253 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,1254 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,1255 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,1256 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,1257 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,1258 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,1259 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,1260 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,1261 [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,1262 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,1263 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,1264 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,1265 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,1266 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,1267 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,1268 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,1269 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,1270 [CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,1271 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,1272 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,1273 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,1274 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,1275 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,1276 [CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,1277 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,1278 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,1279 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,1280 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,1281 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,1282 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,1283 [CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,1284 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,1285 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,1286 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,1287 [CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,1288 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,1289 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,1290 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,1291 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,1292 [CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,1293 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,1294 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,1295 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,1296 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,1297 [CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,1298 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,1299 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,1300 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,1301 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,1302 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,1303 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,1304 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,1305 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,1306 [CLK_NAND] = &nand_clk.common.hw,1307 [CLK_MS] = &ms_clk.common.hw,1308 [CLK_MMC0] = &mmc0_clk.common.hw,1309 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,1310 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,1311 [CLK_MMC1] = &mmc1_clk.common.hw,1312 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,1313 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,1314 [CLK_MMC2] = &mmc2_clk.common.hw,1315 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,1316 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,1317 [CLK_MMC3] = &mmc3_clk.common.hw,1318 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,1319 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,1320 [CLK_TS] = &ts_clk.common.hw,1321 [CLK_SS] = &ss_clk.common.hw,1322 [CLK_SPI0] = &spi0_clk.common.hw,1323 [CLK_SPI1] = &spi1_clk.common.hw,1324 [CLK_SPI2] = &spi2_clk.common.hw,1325 [CLK_PATA] = &pata_clk.common.hw,1326 [CLK_IR0] = &ir0_sun7i_clk.common.hw,1327 [CLK_IR1] = &ir1_sun7i_clk.common.hw,1328 [CLK_I2S0] = &i2s0_clk.common.hw,1329 [CLK_AC97] = &ac97_clk.common.hw,1330 [CLK_SPDIF] = &spdif_clk.common.hw,1331 [CLK_KEYPAD] = &keypad_clk.common.hw,1332 [CLK_SATA] = &sata_clk.common.hw,1333 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,1334 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,1335 [CLK_USB_PHY] = &usb_phy_clk.common.hw,1336 /* CLK_GPS is unimplemented */1337 [CLK_SPI3] = &spi3_clk.common.hw,1338 [CLK_I2S1] = &i2s1_clk.common.hw,1339 [CLK_I2S2] = &i2s2_clk.common.hw,1340 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,1341 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,1342 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,1343 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,1344 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,1345 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,1346 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,1347 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,1348 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,1349 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,1350 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,1351 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,1352 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,1353 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,1354 [CLK_DE_BE0] = &de_be0_clk.common.hw,1355 [CLK_DE_BE1] = &de_be1_clk.common.hw,1356 [CLK_DE_FE0] = &de_fe0_clk.common.hw,1357 [CLK_DE_FE1] = &de_fe1_clk.common.hw,1358 [CLK_DE_MP] = &de_mp_clk.common.hw,1359 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,1360 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,1361 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,1362 [CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,1363 [CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,1364 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,1365 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,1366 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,1367 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,1368 [CLK_CSI0] = &csi0_clk.common.hw,1369 [CLK_CSI1] = &csi1_clk.common.hw,1370 [CLK_VE] = &ve_clk.common.hw,1371 [CLK_CODEC] = &codec_clk.common.hw,1372 [CLK_AVS] = &avs_clk.common.hw,1373 [CLK_ACE] = &ace_clk.common.hw,1374 [CLK_HDMI] = &hdmi_clk.common.hw,1375 [CLK_GPU] = &gpu_sun7i_clk.common.hw,1376 [CLK_MBUS] = &mbus_sun7i_clk.common.hw,1377 [CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,1378 [CLK_HDMI1] = &hdmi1_clk.common.hw,1379 [CLK_OUT_A] = &out_a_clk.common.hw,1380 [CLK_OUT_B] = &out_b_clk.common.hw,1381 },1382 .num = CLK_NUMBER_SUN7I,1383};1384 1385static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {1386 [RST_USB_PHY0] = { 0x0cc, BIT(0) },1387 [RST_USB_PHY1] = { 0x0cc, BIT(1) },1388 [RST_USB_PHY2] = { 0x0cc, BIT(2) },1389 [RST_GPS] = { 0x0d0, BIT(0) },1390 [RST_DE_BE0] = { 0x104, BIT(30) },1391 [RST_DE_BE1] = { 0x108, BIT(30) },1392 [RST_DE_FE0] = { 0x10c, BIT(30) },1393 [RST_DE_FE1] = { 0x110, BIT(30) },1394 [RST_DE_MP] = { 0x114, BIT(30) },1395 [RST_TVE0] = { 0x118, BIT(29) },1396 [RST_TCON0] = { 0x118, BIT(30) },1397 [RST_TVE1] = { 0x11c, BIT(29) },1398 [RST_TCON1] = { 0x11c, BIT(30) },1399 [RST_CSI0] = { 0x134, BIT(30) },1400 [RST_CSI1] = { 0x138, BIT(30) },1401 [RST_VE] = { 0x13c, BIT(0) },1402 [RST_ACE] = { 0x148, BIT(16) },1403 [RST_LVDS] = { 0x14c, BIT(0) },1404 [RST_GPU] = { 0x154, BIT(30) },1405 [RST_HDMI_H] = { 0x170, BIT(0) },1406 [RST_HDMI_SYS] = { 0x170, BIT(1) },1407 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },1408};1409 1410static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {1411 .ccu_clks = sun4i_sun7i_ccu_clks,1412 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),1413 1414 .hw_clks = &sun4i_a10_hw_clks,1415 1416 .resets = sunxi_a10_a20_ccu_resets,1417 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),1418};1419 1420static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {1421 .ccu_clks = sun4i_sun7i_ccu_clks,1422 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),1423 1424 .hw_clks = &sun7i_a20_hw_clks,1425 1426 .resets = sunxi_a10_a20_ccu_resets,1427 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),1428};1429 1430static int sun4i_a10_ccu_probe(struct platform_device *pdev)1431{1432 const struct sunxi_ccu_desc *desc;1433 void __iomem *reg;1434 u32 val;1435 1436 desc = of_device_get_match_data(&pdev->dev);1437 if (!desc)1438 return -EINVAL;1439 1440 reg = devm_platform_ioremap_resource(pdev, 0);1441 if (IS_ERR(reg))1442 return PTR_ERR(reg);1443 1444 val = readl(reg + SUN4I_PLL_AUDIO_REG);1445 1446 /*1447 * Force VCO and PLL bias current to lowest setting. Higher1448 * settings interfere with sigma-delta modulation and result1449 * in audible noise and distortions when using SPDIF or I2S.1450 */1451 val &= ~GENMASK(25, 16);1452 1453 /* Force the PLL-Audio-1x divider to 1 */1454 val &= ~GENMASK(29, 26);1455 writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);1456 1457 /*1458 * Use the peripheral PLL6 as the AHB parent, instead of CPU /1459 * AXI which have rate changes due to cpufreq.1460 *1461 * This is especially a big deal for the HS timer whose parent1462 * clock is AHB.1463 *1464 * NB! These bits are undocumented in A10 manual.1465 */1466 val = readl(reg + SUN4I_AHB_REG);1467 val &= ~GENMASK(7, 6);1468 writel(val | (2 << 6), reg + SUN4I_AHB_REG);1469 1470 return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);1471}1472 1473static const struct of_device_id sun4i_a10_ccu_ids[] = {1474 {1475 .compatible = "allwinner,sun4i-a10-ccu",1476 .data = &sun4i_a10_ccu_desc,1477 },1478 {1479 .compatible = "allwinner,sun7i-a20-ccu",1480 .data = &sun7i_a20_ccu_desc,1481 },1482 { }1483};1484MODULE_DEVICE_TABLE(of, sun4i_a10_ccu_ids);1485 1486static struct platform_driver sun4i_a10_ccu_driver = {1487 .probe = sun4i_a10_ccu_probe,1488 .driver = {1489 .name = "sun4i-a10-ccu",1490 .suppress_bind_attrs = true,1491 .of_match_table = sun4i_a10_ccu_ids,1492 },1493};1494module_platform_driver(sun4i_a10_ccu_driver);1495 1496MODULE_IMPORT_NS(SUNXI_CCU);1497MODULE_DESCRIPTION("Support for the Allwinner A10/A20 CCU");1498MODULE_LICENSE("GPL");1499