53 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2017 Priit Laes4 *5 * Priit Laes <plaes@plaes.org>6 */7 8#ifndef _CCU_SUN4I_A10_H_9#define _CCU_SUN4I_A10_H_10 11#include <dt-bindings/clock/sun4i-a10-ccu.h>12#include <dt-bindings/clock/sun7i-a20-ccu.h>13#include <dt-bindings/reset/sun4i-a10-ccu.h>14 15/* The HOSC is exported */16#define CLK_PLL_CORE 217#define CLK_PLL_AUDIO_BASE 318#define CLK_PLL_AUDIO 419#define CLK_PLL_AUDIO_2X 520#define CLK_PLL_AUDIO_4X 621#define CLK_PLL_AUDIO_8X 722#define CLK_PLL_VIDEO0 823/* The PLL_VIDEO0_2X clock is exported */24#define CLK_PLL_VE 1025#define CLK_PLL_DDR_BASE 1126#define CLK_PLL_DDR 1227#define CLK_PLL_DDR_OTHER 1328#define CLK_PLL_PERIPH_BASE 1429#define CLK_PLL_PERIPH 1530#define CLK_PLL_PERIPH_SATA 1631#define CLK_PLL_VIDEO1 1732/* The PLL_VIDEO1_2X clock is exported */33#define CLK_PLL_GPU 1934 35/* The CPU clock is exported */36#define CLK_AXI 2137#define CLK_AXI_DRAM 2238#define CLK_AHB 2339#define CLK_APB0 2440#define CLK_APB1 2541 42/* AHB gates are exported (23..68) */43/* APB0 gates are exported (69..78) */44/* APB1 gates are exported (79..95) */45/* IP module clocks are exported (96..128) */46/* DRAM gates are exported (129..142)*/47/* Media (display engine clocks & etc) are exported (143..169) */48 49#define CLK_NUMBER_SUN4I (CLK_MBUS + 1)50#define CLK_NUMBER_SUN7I (CLK_OUT_B + 1)51 52#endif /* _CCU_SUN4I_A10_H_ */53