57 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>4 */5 6#ifndef _CCU_SUN50I_A100_H_7#define _CCU_SUN50I_A100_H_8 9#include <dt-bindings/clock/sun50i-a100-ccu.h>10#include <dt-bindings/reset/sun50i-a100-ccu.h>11 12#define CLK_OSC12M 013#define CLK_PLL_CPUX 114#define CLK_PLL_DDR0 215 16/* PLL_PERIPH0 exported for PRCM */17 18#define CLK_PLL_PERIPH0_2X 419#define CLK_PLL_PERIPH1 520#define CLK_PLL_PERIPH1_2X 621#define CLK_PLL_GPU 722#define CLK_PLL_VIDEO0 823#define CLK_PLL_VIDEO0_2X 924#define CLK_PLL_VIDEO0_4X 1025#define CLK_PLL_VIDEO1 1126#define CLK_PLL_VIDEO1_2X 1227#define CLK_PLL_VIDEO1_4X 1328#define CLK_PLL_VIDEO2 1429#define CLK_PLL_VIDEO2_2X 1530#define CLK_PLL_VIDEO2_4X 1631#define CLK_PLL_VIDEO3 1732#define CLK_PLL_VIDEO3_2X 1833#define CLK_PLL_VIDEO3_4X 1934#define CLK_PLL_VE 2035#define CLK_PLL_COM 2136#define CLK_PLL_COM_AUDIO 2237#define CLK_PLL_AUDIO 2338 39/* CPUX clock exported for DVFS */40 41#define CLK_AXI 2542#define CLK_CPUX_APB 2643#define CLK_PSI_AHB1_AHB2 2744#define CLK_AHB3 2845 46/* APB1 clock exported for PIO */47 48#define CLK_APB2 3049 50/* All module clocks and bus gates are exported except DRAM */51 52#define CLK_BUS_DRAM 5853 54#define CLK_NUMBER (CLK_CSI_ISP + 1)55 56#endif /* _CCU_SUN50I_A100_H_ */57