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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/io.h>8#include <linux/module.h>9#include <linux/platform_device.h>10 11#include "ccu_common.h"12#include "ccu_reset.h"13 14#include "ccu_div.h"15#include "ccu_gate.h"16#include "ccu_mp.h"17#include "ccu_mult.h"18#include "ccu_nk.h"19#include "ccu_nkm.h"20#include "ccu_nkmp.h"21#include "ccu_nm.h"22#include "ccu_phase.h"23 24#include "ccu-sun50i-a64.h"25 26static struct ccu_nkmp pll_cpux_clk = {27 .enable = BIT(31),28 .lock = BIT(28),29 .n = _SUNXI_CCU_MULT(8, 5),30 .k = _SUNXI_CCU_MULT(4, 2),31 .m = _SUNXI_CCU_DIV(0, 2),32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),33 .common = {34 .reg = 0x000,35 .hw.init = CLK_HW_INIT("pll-cpux",36 "osc24M",37 &ccu_nkmp_ops,38 CLK_SET_RATE_UNGATE),39 },40};41 42/*43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from44 * the base (2x, 4x and 8x), and one variable divider (the one true45 * pll audio).46 *47 * With sigma-delta modulation for fractional-N on the audio PLL,48 * we have to use specific dividers. This means the variable divider49 * can no longer be used, as the audio codec requests the exact clock50 * rates we support through this mechanism. So we now hard code the51 * variable divider to 1. This means the clock rates will no longer52 * match the clock names.53 */54#define SUN50I_A64_PLL_AUDIO_REG 0x00855 56static struct ccu_sdm_setting pll_audio_sdm_table[] = {57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },59};60 61static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",62 "osc24M", 0x008,63 8, 7, /* N */64 0, 5, /* M */65 pll_audio_sdm_table, BIT(24),66 0x284, BIT(31),67 BIT(31), /* gate */68 BIT(28), /* lock */69 CLK_SET_RATE_UNGATE);70 71static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",72 "osc24M", 0x010,73 192000000, /* Minimum rate */74 1008000000, /* Maximum rate */75 8, 7, /* N */76 0, 4, /* M */77 BIT(24), /* frac enable */78 BIT(25), /* frac select */79 270000000, /* frac rate 0 */80 297000000, /* frac rate 1 */81 BIT(31), /* gate */82 BIT(28), /* lock */83 CLK_SET_RATE_UNGATE);84 85static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",86 "osc24M", 0x018,87 8, 7, /* N */88 0, 4, /* M */89 BIT(24), /* frac enable */90 BIT(25), /* frac select */91 270000000, /* frac rate 0 */92 297000000, /* frac rate 1 */93 BIT(31), /* gate */94 BIT(28), /* lock */95 CLK_SET_RATE_UNGATE);96 97static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",98 "osc24M", 0x020,99 8, 5, /* N */100 4, 2, /* K */101 0, 2, /* M */102 BIT(31), /* gate */103 BIT(28), /* lock */104 CLK_SET_RATE_UNGATE);105 106static struct ccu_nk pll_periph0_clk = {107 .enable = BIT(31),108 .lock = BIT(28),109 .n = _SUNXI_CCU_MULT(8, 5),110 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),111 .fixed_post_div = 2,112 .common = {113 .reg = 0x028,114 .features = CCU_FEATURE_FIXED_POSTDIV,115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",116 &ccu_nk_ops, CLK_SET_RATE_UNGATE),117 },118};119 120static struct ccu_nk pll_periph1_clk = {121 .enable = BIT(31),122 .lock = BIT(28),123 .n = _SUNXI_CCU_MULT(8, 5),124 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),125 .fixed_post_div = 2,126 .common = {127 .reg = 0x02c,128 .features = CCU_FEATURE_FIXED_POSTDIV,129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",130 &ccu_nk_ops, CLK_SET_RATE_UNGATE),131 },132};133 134static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",135 "osc24M", 0x030,136 192000000, /* Minimum rate */137 1008000000, /* Maximum rate */138 8, 7, /* N */139 0, 4, /* M */140 BIT(24), /* frac enable */141 BIT(25), /* frac select */142 270000000, /* frac rate 0 */143 297000000, /* frac rate 1 */144 BIT(31), /* gate */145 BIT(28), /* lock */146 CLK_SET_RATE_UNGATE);147 148static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",149 "osc24M", 0x038,150 8, 7, /* N */151 0, 4, /* M */152 BIT(24), /* frac enable */153 BIT(25), /* frac select */154 270000000, /* frac rate 0 */155 297000000, /* frac rate 1 */156 BIT(31), /* gate */157 BIT(28), /* lock */158 CLK_SET_RATE_UNGATE);159 160/*161 * The output function can be changed to something more complex that162 * we do not handle yet.163 *164 * Hardcode the mode so that we don't fall in that case.165 */166#define SUN50I_A64_PLL_MIPI_REG 0x040167 168static struct ccu_nkm pll_mipi_clk = {169 /*170 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's171 * user manual, and by experiments the PLL doesn't work without172 * these bits toggled.173 */174 .enable = BIT(31) | BIT(23) | BIT(22),175 .lock = BIT(28),176 .n = _SUNXI_CCU_MULT(8, 4),177 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),178 .m = _SUNXI_CCU_DIV(0, 4),179 .max_m_n_ratio = 3,180 .min_parent_m_ratio = 24000000,181 .common = {182 .reg = 0x040,183 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",184 &ccu_nkm_ops,185 CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),186 .features = CCU_FEATURE_CLOSEST_RATE,187 .min_rate = 500000000,188 .max_rate = 1400000000,189 },190};191 192static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",193 "osc24M", 0x044,194 8, 7, /* N */195 0, 4, /* M */196 BIT(24), /* frac enable */197 BIT(25), /* frac select */198 270000000, /* frac rate 0 */199 297000000, /* frac rate 1 */200 BIT(31), /* gate */201 BIT(28), /* lock */202 CLK_SET_RATE_UNGATE);203 204static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",205 "osc24M", 0x048,206 8, 7, /* N */207 0, 4, /* M */208 BIT(24), /* frac enable */209 BIT(25), /* frac select */210 270000000, /* frac rate 0 */211 297000000, /* frac rate 1 */212 BIT(31), /* gate */213 BIT(28), /* lock */214 CLK_SET_RATE_UNGATE);215 216static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",217 "osc24M", 0x04c,218 8, 7, /* N */219 0, 2, /* M */220 BIT(31), /* gate */221 BIT(28), /* lock */222 CLK_SET_RATE_UNGATE);223 224static const char * const cpux_parents[] = { "osc32k", "osc24M",225 "pll-cpux", "pll-cpux" };226static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,227 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);228 229static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);230 231static const char * const ahb1_parents[] = { "osc32k", "osc24M",232 "axi", "pll-periph0" };233static const struct ccu_mux_var_prediv ahb1_predivs[] = {234 { .index = 3, .shift = 6, .width = 2 },235};236static struct ccu_div ahb1_clk = {237 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),238 239 .mux = {240 .shift = 12,241 .width = 2,242 243 .var_predivs = ahb1_predivs,244 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),245 },246 247 .common = {248 .reg = 0x054,249 .features = CCU_FEATURE_VARIABLE_PREDIV,250 .hw.init = CLK_HW_INIT_PARENTS("ahb1",251 ahb1_parents,252 &ccu_div_ops,253 0),254 },255};256 257static struct clk_div_table apb1_div_table[] = {258 { .val = 0, .div = 2 },259 { .val = 1, .div = 2 },260 { .val = 2, .div = 4 },261 { .val = 3, .div = 8 },262 { /* Sentinel */ },263};264static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",265 0x054, 8, 2, apb1_div_table, 0);266 267static const char * const apb2_parents[] = { "osc32k", "osc24M",268 "pll-periph0-2x",269 "pll-periph0-2x" };270static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,271 0, 5, /* M */272 16, 2, /* P */273 24, 2, /* mux */274 0);275 276static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };277static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {278 { .index = 1, .div = 2 },279};280static struct ccu_mux ahb2_clk = {281 .mux = {282 .shift = 0,283 .width = 1,284 .fixed_predivs = ahb2_fixed_predivs,285 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),286 },287 288 .common = {289 .reg = 0x05c,290 .features = CCU_FEATURE_FIXED_PREDIV,291 .hw.init = CLK_HW_INIT_PARENTS("ahb2",292 ahb2_parents,293 &ccu_mux_ops,294 0),295 },296};297 298static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",299 0x060, BIT(1), 0);300static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",301 0x060, BIT(5), 0);302static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",303 0x060, BIT(6), 0);304static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",305 0x060, BIT(8), 0);306static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",307 0x060, BIT(9), 0);308static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",309 0x060, BIT(10), 0);310static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",311 0x060, BIT(13), 0);312static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",313 0x060, BIT(14), 0);314static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",315 0x060, BIT(17), 0);316static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",317 0x060, BIT(18), 0);318static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",319 0x060, BIT(19), 0);320static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",321 0x060, BIT(20), 0);322static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",323 0x060, BIT(21), 0);324static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",325 0x060, BIT(23), 0);326static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",327 0x060, BIT(24), 0);328static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",329 0x060, BIT(25), 0);330static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",331 0x060, BIT(28), 0);332static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",333 0x060, BIT(29), 0);334 335static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",336 0x064, BIT(0), 0);337static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",338 0x064, BIT(3), 0);339static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",340 0x064, BIT(4), 0);341static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",342 0x064, BIT(5), 0);343static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",344 0x064, BIT(8), 0);345static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",346 0x064, BIT(11), 0);347static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",348 0x064, BIT(12), 0);349static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",350 0x064, BIT(20), 0);351static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",352 0x064, BIT(21), 0);353static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",354 0x064, BIT(22), 0);355 356static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",357 0x068, BIT(0), 0);358static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",359 0x068, BIT(1), 0);360static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",361 0x068, BIT(5), 0);362static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",363 0x068, BIT(8), 0);364static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",365 0x068, BIT(12), 0);366static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",367 0x068, BIT(13), 0);368static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",369 0x068, BIT(14), 0);370 371static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",372 0x06c, BIT(0), 0);373static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",374 0x06c, BIT(1), 0);375static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",376 0x06c, BIT(2), 0);377static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",378 0x06c, BIT(5), 0);379static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",380 0x06c, BIT(16), 0);381static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",382 0x06c, BIT(17), 0);383static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",384 0x06c, BIT(18), 0);385static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",386 0x06c, BIT(19), 0);387static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",388 0x06c, BIT(20), 0);389 390static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",391 0x070, BIT(7), 0);392 393static struct clk_div_table ths_div_table[] = {394 { .val = 0, .div = 1 },395 { .val = 1, .div = 2 },396 { .val = 2, .div = 4 },397 { .val = 3, .div = 6 },398 { /* Sentinel */ },399};400static const char * const ths_parents[] = { "osc24M" };401static struct ccu_div ths_clk = {402 .enable = BIT(31),403 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),404 .mux = _SUNXI_CCU_MUX(24, 2),405 .common = {406 .reg = 0x074,407 .hw.init = CLK_HW_INIT_PARENTS("ths",408 ths_parents,409 &ccu_div_ops,410 0),411 },412};413 414static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",415 "pll-periph1" };416static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,417 0, 4, /* M */418 16, 2, /* P */419 24, 2, /* mux */420 BIT(31), /* gate */421 0);422 423/*424 * MMC clocks are the new timing mode (see A83T & H3) variety, but without425 * the mode switch. This means they have a 2x post divider between the clock426 * and the MMC module. This is not documented in the manual, but is taken427 * into consideration when setting the mmc module clocks in the BSP kernel.428 * Without it, MMC performance is degraded.429 *430 * We model it here to be consistent with other SoCs supporting this mode.431 * The alternative would be to add the 2x multiplier when setting the MMC432 * module clock in the MMC driver, just for the A64.433 */434static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",435 "pll-periph1-2x" };436static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",437 mmc_default_parents, 0x088,438 0, 4, /* M */439 16, 2, /* P */440 24, 2, /* mux */441 BIT(31), /* gate */442 2, /* post-div */443 0);444 445static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",446 mmc_default_parents, 0x08c,447 0, 4, /* M */448 16, 2, /* P */449 24, 2, /* mux */450 BIT(31), /* gate */451 2, /* post-div */452 0);453 454static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",455 mmc_default_parents, 0x090,456 0, 4, /* M */457 16, 2, /* P */458 24, 2, /* mux */459 BIT(31), /* gate */460 2, /* post-div */461 0);462 463static const char * const ts_parents[] = { "osc24M", "pll-periph0", };464static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,465 0, 4, /* M */466 16, 2, /* P */467 24, 4, /* mux */468 BIT(31), /* gate */469 0);470 471static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,472 0, 4, /* M */473 16, 2, /* P */474 24, 2, /* mux */475 BIT(31), /* gate */476 0);477 478static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,479 0, 4, /* M */480 16, 2, /* P */481 24, 2, /* mux */482 BIT(31), /* gate */483 0);484 485static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,486 0, 4, /* M */487 16, 2, /* P */488 24, 2, /* mux */489 BIT(31), /* gate */490 0);491 492static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",493 "pll-audio-2x", "pll-audio" };494static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,495 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);496 497static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,498 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);499 500static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,501 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);502 503static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",504 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);505 506static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",507 0x0cc, BIT(8), 0);508static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",509 0x0cc, BIT(9), 0);510static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",511 0x0cc, BIT(10), 0);512static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",513 0x0cc, BIT(11), 0);514static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",515 0x0cc, BIT(16), 0);516static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",517 0x0cc, BIT(17), 0);518 519static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };520static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,521 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);522 523static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",524 0x100, BIT(0), 0);525static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",526 0x100, BIT(1), 0);527static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",528 0x100, BIT(2), 0);529static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",530 0x100, BIT(3), 0);531 532static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };533static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,534 0x104, 0, 4, 24, 3, BIT(31),535 CLK_SET_RATE_PARENT);536 537/*538 * DSI output seems to work only when PLL_MIPI selected. Set it and prevent539 * the mux from reparenting.540 */541#define SUN50I_A64_TCON0_CLK_REG 0x118542 543static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };544static const u8 tcon0_table[] = { 0, 2, };545static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,546 tcon0_table, 0x118, 24, 3, BIT(31),547 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);548 549static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };550static const u8 tcon1_table[] = { 0, 2, };551static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,552 tcon1_table, 0x11c,553 0, 4, /* M */554 24, 2, /* mux */555 BIT(31), /* gate */556 CLK_SET_RATE_PARENT);557 558static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };559static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,560 0x124, 0, 4, 24, 3, BIT(31), 0);561 562static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",563 0x130, BIT(31), 0);564 565static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };566static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,567 0x134, 16, 4, 24, 3, BIT(31), 0);568 569static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };570static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,571 0x134, 0, 5, 8, 3, BIT(15), 0);572 573static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",574 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);575 576static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",577 0x140, BIT(31), CLK_SET_RATE_PARENT);578 579static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",580 0x140, BIT(30), CLK_SET_RATE_PARENT);581 582static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",583 0x144, BIT(31), 0);584 585static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };586static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,587 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);588 589static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",590 0x154, BIT(31), 0);591 592static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",593 "pll-ddr0", "pll-ddr1" };594static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,595 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);596 597static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };598static const u8 dsi_dphy_table[] = { 0, 2, };599static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",600 dsi_dphy_parents, dsi_dphy_table,601 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);602 603static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",604 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);605 606/* Fixed Factor clocks */607static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);608 609static const struct clk_hw *clk_parent_pll_audio[] = {610 &pll_audio_base_clk.common.hw611};612 613/* We hardcode the divider to 1 for now */614static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",615 clk_parent_pll_audio,616 1, 1, CLK_SET_RATE_PARENT);617static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",618 clk_parent_pll_audio,619 2, 1, CLK_SET_RATE_PARENT);620static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",621 clk_parent_pll_audio,622 1, 1, CLK_SET_RATE_PARENT);623static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",624 clk_parent_pll_audio,625 1, 2, CLK_SET_RATE_PARENT);626static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",627 &pll_periph0_clk.common.hw,628 1, 2, 0);629static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",630 &pll_periph1_clk.common.hw,631 1, 2, 0);632static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",633 &pll_video0_clk.common.hw,634 1, 2, CLK_SET_RATE_PARENT);635 636static struct ccu_common *sun50i_a64_ccu_clks[] = {637 &pll_cpux_clk.common,638 &pll_audio_base_clk.common,639 &pll_video0_clk.common,640 &pll_ve_clk.common,641 &pll_ddr0_clk.common,642 &pll_periph0_clk.common,643 &pll_periph1_clk.common,644 &pll_video1_clk.common,645 &pll_gpu_clk.common,646 &pll_mipi_clk.common,647 &pll_hsic_clk.common,648 &pll_de_clk.common,649 &pll_ddr1_clk.common,650 &cpux_clk.common,651 &axi_clk.common,652 &ahb1_clk.common,653 &apb1_clk.common,654 &apb2_clk.common,655 &ahb2_clk.common,656 &bus_mipi_dsi_clk.common,657 &bus_ce_clk.common,658 &bus_dma_clk.common,659 &bus_mmc0_clk.common,660 &bus_mmc1_clk.common,661 &bus_mmc2_clk.common,662 &bus_nand_clk.common,663 &bus_dram_clk.common,664 &bus_emac_clk.common,665 &bus_ts_clk.common,666 &bus_hstimer_clk.common,667 &bus_spi0_clk.common,668 &bus_spi1_clk.common,669 &bus_otg_clk.common,670 &bus_ehci0_clk.common,671 &bus_ehci1_clk.common,672 &bus_ohci0_clk.common,673 &bus_ohci1_clk.common,674 &bus_ve_clk.common,675 &bus_tcon0_clk.common,676 &bus_tcon1_clk.common,677 &bus_deinterlace_clk.common,678 &bus_csi_clk.common,679 &bus_hdmi_clk.common,680 &bus_de_clk.common,681 &bus_gpu_clk.common,682 &bus_msgbox_clk.common,683 &bus_spinlock_clk.common,684 &bus_codec_clk.common,685 &bus_spdif_clk.common,686 &bus_pio_clk.common,687 &bus_ths_clk.common,688 &bus_i2s0_clk.common,689 &bus_i2s1_clk.common,690 &bus_i2s2_clk.common,691 &bus_i2c0_clk.common,692 &bus_i2c1_clk.common,693 &bus_i2c2_clk.common,694 &bus_scr_clk.common,695 &bus_uart0_clk.common,696 &bus_uart1_clk.common,697 &bus_uart2_clk.common,698 &bus_uart3_clk.common,699 &bus_uart4_clk.common,700 &bus_dbg_clk.common,701 &ths_clk.common,702 &nand_clk.common,703 &mmc0_clk.common,704 &mmc1_clk.common,705 &mmc2_clk.common,706 &ts_clk.common,707 &ce_clk.common,708 &spi0_clk.common,709 &spi1_clk.common,710 &i2s0_clk.common,711 &i2s1_clk.common,712 &i2s2_clk.common,713 &spdif_clk.common,714 &usb_phy0_clk.common,715 &usb_phy1_clk.common,716 &usb_hsic_clk.common,717 &usb_hsic_12m_clk.common,718 &usb_ohci0_clk.common,719 &usb_ohci1_clk.common,720 &dram_clk.common,721 &dram_ve_clk.common,722 &dram_csi_clk.common,723 &dram_deinterlace_clk.common,724 &dram_ts_clk.common,725 &de_clk.common,726 &tcon0_clk.common,727 &tcon1_clk.common,728 &deinterlace_clk.common,729 &csi_misc_clk.common,730 &csi_sclk_clk.common,731 &csi_mclk_clk.common,732 &ve_clk.common,733 &ac_dig_clk.common,734 &ac_dig_4x_clk.common,735 &avs_clk.common,736 &hdmi_clk.common,737 &hdmi_ddc_clk.common,738 &mbus_clk.common,739 &dsi_dphy_clk.common,740 &gpu_clk.common,741};742 743static struct clk_hw_onecell_data sun50i_a64_hw_clks = {744 .hws = {745 [CLK_OSC_12M] = &osc12M_clk.hw,746 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,747 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,748 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,749 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,750 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,751 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,752 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,753 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,754 [CLK_PLL_VE] = &pll_ve_clk.common.hw,755 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,756 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,757 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,758 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,759 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,760 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,761 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,762 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,763 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,764 [CLK_PLL_DE] = &pll_de_clk.common.hw,765 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,766 [CLK_CPUX] = &cpux_clk.common.hw,767 [CLK_AXI] = &axi_clk.common.hw,768 [CLK_AHB1] = &ahb1_clk.common.hw,769 [CLK_APB1] = &apb1_clk.common.hw,770 [CLK_APB2] = &apb2_clk.common.hw,771 [CLK_AHB2] = &ahb2_clk.common.hw,772 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,773 [CLK_BUS_CE] = &bus_ce_clk.common.hw,774 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,775 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,776 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,777 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,778 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,779 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,780 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,781 [CLK_BUS_TS] = &bus_ts_clk.common.hw,782 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,783 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,784 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,785 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,786 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,787 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,788 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,789 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,790 [CLK_BUS_VE] = &bus_ve_clk.common.hw,791 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,792 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,793 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,794 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,795 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,796 [CLK_BUS_DE] = &bus_de_clk.common.hw,797 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,798 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,799 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,800 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,801 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,802 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,803 [CLK_BUS_THS] = &bus_ths_clk.common.hw,804 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,805 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,806 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,807 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,808 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,809 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,810 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,811 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,812 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,813 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,814 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,815 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,816 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,817 [CLK_THS] = &ths_clk.common.hw,818 [CLK_NAND] = &nand_clk.common.hw,819 [CLK_MMC0] = &mmc0_clk.common.hw,820 [CLK_MMC1] = &mmc1_clk.common.hw,821 [CLK_MMC2] = &mmc2_clk.common.hw,822 [CLK_TS] = &ts_clk.common.hw,823 [CLK_CE] = &ce_clk.common.hw,824 [CLK_SPI0] = &spi0_clk.common.hw,825 [CLK_SPI1] = &spi1_clk.common.hw,826 [CLK_I2S0] = &i2s0_clk.common.hw,827 [CLK_I2S1] = &i2s1_clk.common.hw,828 [CLK_I2S2] = &i2s2_clk.common.hw,829 [CLK_SPDIF] = &spdif_clk.common.hw,830 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,831 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,832 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,833 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,834 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,835 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,836 [CLK_DRAM] = &dram_clk.common.hw,837 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,838 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,839 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,840 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,841 [CLK_DE] = &de_clk.common.hw,842 [CLK_TCON0] = &tcon0_clk.common.hw,843 [CLK_TCON1] = &tcon1_clk.common.hw,844 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,845 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,846 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,847 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,848 [CLK_VE] = &ve_clk.common.hw,849 [CLK_AC_DIG] = &ac_dig_clk.common.hw,850 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,851 [CLK_AVS] = &avs_clk.common.hw,852 [CLK_HDMI] = &hdmi_clk.common.hw,853 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,854 [CLK_MBUS] = &mbus_clk.common.hw,855 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,856 [CLK_GPU] = &gpu_clk.common.hw,857 },858 .num = CLK_NUMBER,859};860 861static struct ccu_reset_map sun50i_a64_ccu_resets[] = {862 [RST_USB_PHY0] = { 0x0cc, BIT(0) },863 [RST_USB_PHY1] = { 0x0cc, BIT(1) },864 [RST_USB_HSIC] = { 0x0cc, BIT(2) },865 866 [RST_DRAM] = { 0x0f4, BIT(31) },867 [RST_MBUS] = { 0x0fc, BIT(31) },868 869 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },870 [RST_BUS_CE] = { 0x2c0, BIT(5) },871 [RST_BUS_DMA] = { 0x2c0, BIT(6) },872 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },873 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },874 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },875 [RST_BUS_NAND] = { 0x2c0, BIT(13) },876 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },877 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },878 [RST_BUS_TS] = { 0x2c0, BIT(18) },879 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },880 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },881 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },882 [RST_BUS_OTG] = { 0x2c0, BIT(23) },883 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },884 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },885 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },886 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },887 888 [RST_BUS_VE] = { 0x2c4, BIT(0) },889 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },890 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },891 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },892 [RST_BUS_CSI] = { 0x2c4, BIT(8) },893 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },894 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },895 [RST_BUS_DE] = { 0x2c4, BIT(12) },896 [RST_BUS_GPU] = { 0x2c4, BIT(20) },897 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },898 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },899 [RST_BUS_DBG] = { 0x2c4, BIT(31) },900 901 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },902 903 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },904 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },905 [RST_BUS_THS] = { 0x2d0, BIT(8) },906 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },907 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },908 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },909 910 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },911 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },912 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },913 [RST_BUS_SCR] = { 0x2d8, BIT(5) },914 [RST_BUS_UART0] = { 0x2d8, BIT(16) },915 [RST_BUS_UART1] = { 0x2d8, BIT(17) },916 [RST_BUS_UART2] = { 0x2d8, BIT(18) },917 [RST_BUS_UART3] = { 0x2d8, BIT(19) },918 [RST_BUS_UART4] = { 0x2d8, BIT(20) },919};920 921static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {922 .ccu_clks = sun50i_a64_ccu_clks,923 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),924 925 .hw_clks = &sun50i_a64_hw_clks,926 927 .resets = sun50i_a64_ccu_resets,928 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),929};930 931static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {932 .common = &pll_cpux_clk.common,933 /* copy from pll_cpux_clk */934 .enable = BIT(31),935 .lock = BIT(28),936};937 938static struct ccu_mux_nb sun50i_a64_cpu_nb = {939 .common = &cpux_clk.common,940 .cm = &cpux_clk.mux,941 .delay_us = 1, /* > 8 clock cycles at 24 MHz */942 .bypass_index = 1, /* index of 24 MHz oscillator */943};944 945static int sun50i_a64_ccu_probe(struct platform_device *pdev)946{947 void __iomem *reg;948 u32 val;949 int ret;950 951 reg = devm_platform_ioremap_resource(pdev, 0);952 if (IS_ERR(reg))953 return PTR_ERR(reg);954 955 /* Force the PLL-Audio-1x divider to 1 */956 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);957 val &= ~GENMASK(19, 16);958 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);959 960 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);961 962 /* Set PLL MIPI as parent for TCON0 */963 val = readl(reg + SUN50I_A64_TCON0_CLK_REG);964 val &= ~GENMASK(26, 24);965 writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);966 967 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);968 if (ret)969 return ret;970 971 /* Gate then ungate PLL CPU after any rate changes */972 ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);973 974 /* Reparent CPU during PLL CPU rate changes */975 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,976 &sun50i_a64_cpu_nb);977 978 return 0;979}980 981static const struct of_device_id sun50i_a64_ccu_ids[] = {982 { .compatible = "allwinner,sun50i-a64-ccu" },983 { }984};985MODULE_DEVICE_TABLE(of, sun50i_a64_ccu_ids);986 987static struct platform_driver sun50i_a64_ccu_driver = {988 .probe = sun50i_a64_ccu_probe,989 .driver = {990 .name = "sun50i-a64-ccu",991 .suppress_bind_attrs = true,992 .of_match_table = sun50i_a64_ccu_ids,993 },994};995module_platform_driver(sun50i_a64_ccu_driver);996 997MODULE_IMPORT_NS(SUNXI_CCU);998MODULE_DESCRIPTION("Support for the Allwinner A64 CCU");999MODULE_LICENSE("GPL");1000