61 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Maxime Ripard4 *5 * Maxime Ripard <maxime.ripard@free-electrons.com>6 */7 8#ifndef _CCU_SUN50I_A64_H_9#define _CCU_SUN50I_A64_H_10 11#include <dt-bindings/clock/sun50i-a64-ccu.h>12#include <dt-bindings/reset/sun50i-a64-ccu.h>13 14#define CLK_OSC_12M 015#define CLK_PLL_CPUX 116#define CLK_PLL_AUDIO_BASE 217#define CLK_PLL_AUDIO 318#define CLK_PLL_AUDIO_2X 419#define CLK_PLL_AUDIO_4X 520#define CLK_PLL_AUDIO_8X 621 22/* PLL_VIDEO0 exported for HDMI PHY */23 24#define CLK_PLL_VIDEO0_2X 825#define CLK_PLL_VE 926#define CLK_PLL_DDR0 1027 28/* PLL_PERIPH0 exported for PRCM */29 30#define CLK_PLL_PERIPH0_2X 1231#define CLK_PLL_PERIPH1 1332#define CLK_PLL_PERIPH1_2X 1433#define CLK_PLL_VIDEO1 1534#define CLK_PLL_GPU 1635#define CLK_PLL_MIPI 1736#define CLK_PLL_HSIC 1837#define CLK_PLL_DE 1938#define CLK_PLL_DDR1 2039#define CLK_AXI 2240#define CLK_APB 2341#define CLK_AHB1 2442#define CLK_APB1 2543#define CLK_APB2 2644#define CLK_AHB2 2745 46/* All the bus gates are exported */47 48/* The first bunch of module clocks are exported */49 50#define CLK_USB_OHCI0_12M 9051 52#define CLK_USB_OHCI1_12M 9253 54/* All the DRAM gates are exported */55 56/* And the DSI and GPU module clock is exported */57 58#define CLK_NUMBER (CLK_GPU + 1)59 60#endif /* _CCU_SUN50I_A64_H_ */61