57 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright 2016 Icenowy Zheng <icenowy@aosc.io>4 */5 6#ifndef _CCU_SUN50I_H6_H_7#define _CCU_SUN50I_H6_H_8 9#include <dt-bindings/clock/sun50i-h6-ccu.h>10#include <dt-bindings/reset/sun50i-h6-ccu.h>11 12#define CLK_OSC12M 013#define CLK_PLL_CPUX 114#define CLK_PLL_DDR0 215 16/* PLL_PERIPH0 exported for PRCM */17 18#define CLK_PLL_PERIPH0_2X 419#define CLK_PLL_PERIPH0_4X 520#define CLK_PLL_PERIPH1 621#define CLK_PLL_PERIPH1_2X 722#define CLK_PLL_PERIPH1_4X 823#define CLK_PLL_GPU 924#define CLK_PLL_VIDEO0 1025#define CLK_PLL_VIDEO0_4X 1126#define CLK_PLL_VIDEO1 1227#define CLK_PLL_VIDEO1_4X 1328#define CLK_PLL_VE 1429#define CLK_PLL_DE 1530#define CLK_PLL_HSIC 1631#define CLK_PLL_AUDIO_BASE 1732#define CLK_PLL_AUDIO 1833#define CLK_PLL_AUDIO_2X 1934#define CLK_PLL_AUDIO_4X 2035 36/* CPUX clock exported for DVFS */37 38#define CLK_AXI 2239#define CLK_CPUX_APB 2340#define CLK_PSI_AHB1_AHB2 2441#define CLK_AHB3 2542 43/* APB1 clock exported for PIO */44 45#define CLK_APB2 2746#define CLK_MBUS 2847 48/* All module clocks and bus gates are exported except DRAM */49 50#define CLK_DRAM 5251 52#define CLK_BUS_DRAM 6053 54#define CLK_NUMBER (CLK_BUS_HDCP + 1)55 56#endif /* _CCU_SUN50I_H6_H_ */57