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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Maxime Ripard4 *5 * Maxime Ripard <maxime.ripard@free-electrons.com>6 */7 8#ifndef _CCU_SUN5I_H_9#define _CCU_SUN5I_H_10 11#include <dt-bindings/clock/sun5i-ccu.h>12#include <dt-bindings/reset/sun5i-ccu.h>13 14/* The HOSC is exported */15#define CLK_PLL_CORE 216#define CLK_PLL_AUDIO_BASE 317#define CLK_PLL_AUDIO 418#define CLK_PLL_AUDIO_2X 519#define CLK_PLL_AUDIO_4X 620#define CLK_PLL_AUDIO_8X 721#define CLK_PLL_VIDEO0 822 23/* The PLL_VIDEO0_2X is exported for HDMI */24 25#define CLK_PLL_VE 1026#define CLK_PLL_DDR_BASE 1127#define CLK_PLL_DDR 1228#define CLK_PLL_DDR_OTHER 1329#define CLK_PLL_PERIPH 1430#define CLK_PLL_VIDEO1 1531 32/* The PLL_VIDEO1_2X is exported for HDMI */33/* The CPU clock is exported */34 35#define CLK_AXI 1836#define CLK_AHB 1937#define CLK_APB0 2038#define CLK_APB1 2139#define CLK_DRAM_AXI 2240 41/* AHB gates are exported */42/* APB0 gates are exported */43/* APB1 gates are exported */44/* Modules clocks are exported */45/* USB clocks are exported */46/* GPS clock is exported */47/* DRAM gates are exported */48/* More display modules clocks are exported */49 50#define CLK_TCON_CH1_SCLK 9151 52/* The rest of the module clocks are exported */53 54#define CLK_NUMBER (CLK_IEP + 1)55 56#endif /* _CCU_SUN5I_H_ */57