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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Chen-Yu Tsai4 *5 * Chen-Yu Tsai <wens@csie.org>6 */7 8#ifndef _CCU_SUN6I_A31_H_9#define _CCU_SUN6I_A31_H_10 11#include <dt-bindings/clock/sun6i-a31-ccu.h>12#include <dt-bindings/reset/sun6i-a31-ccu.h>13 14#define CLK_PLL_CPU 015#define CLK_PLL_AUDIO_BASE 116#define CLK_PLL_AUDIO 217#define CLK_PLL_AUDIO_2X 318#define CLK_PLL_AUDIO_4X 419#define CLK_PLL_AUDIO_8X 520#define CLK_PLL_VIDEO0 621 22/* The PLL_VIDEO0_2X clock is exported */23 24#define CLK_PLL_VE 825#define CLK_PLL_DDR 926 27/* The PLL_PERIPH clock is exported */28 29#define CLK_PLL_PERIPH_2X 1130#define CLK_PLL_VIDEO1 1231 32/* The PLL_VIDEO1_2X clock is exported */33 34#define CLK_PLL_GPU 1435 36/* The PLL_VIDEO1_2X clock is exported */37 38#define CLK_PLL9 1639#define CLK_PLL10 1740 41/* The CPUX clock is exported */42 43#define CLK_AXI 1944#define CLK_AHB1 2045#define CLK_APB1 2146#define CLK_APB2 2247 48/* All the bus gates are exported */49 50/* The first bunch of module clocks are exported */51 52/* EMAC clock is not implemented */53 54#define CLK_MDFS 10755#define CLK_SDRAM0 10856#define CLK_SDRAM1 10957 58/* All the DRAM gates are exported */59 60/* Some more module clocks are exported */61 62#define CLK_MBUS0 14163#define CLK_MBUS1 14264 65/* Some more module clocks and external clock outputs are exported */66 67#define CLK_NUMBER (CLK_OUT_C + 1)68 69#endif /* _CCU_SUN6I_A31_H_ */70