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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Maxime Ripard4 *5 * Maxime Ripard <maxime.ripard@free-electrons.com>6 */7 8#ifndef _CCU_SUN8I_A23_A33_H_9#define _CCU_SUN8I_A23_A33_H_10 11#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>12#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>13 14#define CLK_PLL_CPUX 015#define CLK_PLL_AUDIO_BASE 116#define CLK_PLL_AUDIO 217#define CLK_PLL_AUDIO_2X 318#define CLK_PLL_AUDIO_4X 419#define CLK_PLL_AUDIO_8X 520#define CLK_PLL_VIDEO 621#define CLK_PLL_VIDEO_2X 722#define CLK_PLL_VE 823#define CLK_PLL_DDR0 924#define CLK_PLL_PERIPH 1025#define CLK_PLL_PERIPH_2X 1126#define CLK_PLL_GPU 1227 28/* The PLL MIPI clock is exported */29 30#define CLK_PLL_HSIC 1431#define CLK_PLL_DE 1532#define CLK_PLL_DDR1 1633#define CLK_PLL_DDR 1734 35/* The CPUX clock is exported */36 37#define CLK_AXI 1938#define CLK_AHB1 2039#define CLK_APB1 2140#define CLK_APB2 2241 42/* All the bus gates are exported */43 44/* The first part of the mod clocks is exported */45 46#define CLK_DRAM 7947 48/* Some more module clocks are exported */49 50#define CLK_MBUS 9551 52/* And the last module clocks are exported */53 54#define CLK_NUMBER (CLK_ATS + 1)55 56#endif /* _CCU_SUN8I_A23_A33_H_ */57