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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.4 */5 6#include <linux/clk-provider.h>7#include <linux/io.h>8#include <linux/module.h>9#include <linux/of.h>10#include <linux/platform_device.h>11 12#include "ccu_common.h"13#include "ccu_reset.h"14 15#include "ccu_div.h"16#include "ccu_gate.h"17#include "ccu_mp.h"18#include "ccu_mult.h"19#include "ccu_nk.h"20#include "ccu_nkm.h"21#include "ccu_nkmp.h"22#include "ccu_nm.h"23#include "ccu_phase.h"24#include "ccu_sdm.h"25 26#include "ccu-sun8i-h3.h"27 28static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",29 "osc24M", 0x000,30 8, 5, /* N */31 4, 2, /* K */32 0, 2, /* M */33 16, 2, /* P */34 BIT(31), /* gate */35 BIT(28), /* lock */36 CLK_SET_RATE_UNGATE);37 38/*39 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from40 * the base (2x, 4x and 8x), and one variable divider (the one true41 * pll audio).42 *43 * With sigma-delta modulation for fractional-N on the audio PLL,44 * we have to use specific dividers. This means the variable divider45 * can no longer be used, as the audio codec requests the exact clock46 * rates we support through this mechanism. So we now hard code the47 * variable divider to 1. This means the clock rates will no longer48 * match the clock names.49 */50#define SUN8I_H3_PLL_AUDIO_REG 0x00851 52static struct ccu_sdm_setting pll_audio_sdm_table[] = {53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },55};56 57static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",58 "osc24M", 0x008,59 8, 7, /* N */60 0, 5, /* M */61 pll_audio_sdm_table, BIT(24),62 0x284, BIT(31),63 BIT(31), /* gate */64 BIT(28), /* lock */65 CLK_SET_RATE_UNGATE);66 67static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",68 "osc24M", 0x0010,69 192000000, /* Minimum rate */70 912000000, /* Maximum rate */71 8, 7, /* N */72 0, 4, /* M */73 BIT(24), /* frac enable */74 BIT(25), /* frac select */75 270000000, /* frac rate 0 */76 297000000, /* frac rate 1 */77 BIT(31), /* gate */78 BIT(28), /* lock */79 CLK_SET_RATE_UNGATE);80 81static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",82 "osc24M", 0x0018,83 8, 7, /* N */84 0, 4, /* M */85 BIT(24), /* frac enable */86 BIT(25), /* frac select */87 270000000, /* frac rate 0 */88 297000000, /* frac rate 1 */89 BIT(31), /* gate */90 BIT(28), /* lock */91 CLK_SET_RATE_UNGATE);92 93static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",94 "osc24M", 0x020,95 8, 5, /* N */96 4, 2, /* K */97 0, 2, /* M */98 BIT(31), /* gate */99 BIT(28), /* lock */100 CLK_SET_RATE_UNGATE);101 102static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",103 "osc24M", 0x028,104 8, 5, /* N */105 4, 2, /* K */106 BIT(31), /* gate */107 BIT(28), /* lock */108 2, /* post-div */109 CLK_SET_RATE_UNGATE);110 111static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",112 "osc24M", 0x0038,113 8, 7, /* N */114 0, 4, /* M */115 BIT(24), /* frac enable */116 BIT(25), /* frac select */117 270000000, /* frac rate 0 */118 297000000, /* frac rate 1 */119 BIT(31), /* gate */120 BIT(28), /* lock */121 CLK_SET_RATE_UNGATE);122 123static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",124 "osc24M", 0x044,125 8, 5, /* N */126 4, 2, /* K */127 BIT(31), /* gate */128 BIT(28), /* lock */129 2, /* post-div */130 CLK_SET_RATE_UNGATE);131 132static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",133 "osc24M", 0x0048,134 8, 7, /* N */135 0, 4, /* M */136 BIT(24), /* frac enable */137 BIT(25), /* frac select */138 270000000, /* frac rate 0 */139 297000000, /* frac rate 1 */140 BIT(31), /* gate */141 BIT(28), /* lock */142 CLK_SET_RATE_UNGATE);143 144static const char * const cpux_parents[] = { "osc32k", "osc24M",145 "pll-cpux" , "pll-cpux" };146static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,147 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);148 149static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);150 151static const char * const ahb1_parents[] = { "osc32k", "osc24M",152 "axi" , "pll-periph0" };153static const struct ccu_mux_var_prediv ahb1_predivs[] = {154 { .index = 3, .shift = 6, .width = 2 },155};156static struct ccu_div ahb1_clk = {157 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),158 159 .mux = {160 .shift = 12,161 .width = 2,162 163 .var_predivs = ahb1_predivs,164 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),165 },166 167 .common = {168 .reg = 0x054,169 .features = CCU_FEATURE_VARIABLE_PREDIV,170 .hw.init = CLK_HW_INIT_PARENTS("ahb1",171 ahb1_parents,172 &ccu_div_ops,173 0),174 },175};176 177static struct clk_div_table apb1_div_table[] = {178 { .val = 0, .div = 2 },179 { .val = 1, .div = 2 },180 { .val = 2, .div = 4 },181 { .val = 3, .div = 8 },182 { /* Sentinel */ },183};184static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",185 0x054, 8, 2, apb1_div_table, 0);186 187static const char * const apb2_parents[] = { "osc32k", "osc24M",188 "pll-periph0" , "pll-periph0" };189static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,190 0, 5, /* M */191 16, 2, /* P */192 24, 2, /* mux */193 0);194 195static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };196static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {197 { .index = 1, .div = 2 },198};199static struct ccu_mux ahb2_clk = {200 .mux = {201 .shift = 0,202 .width = 1,203 .fixed_predivs = ahb2_fixed_predivs,204 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),205 },206 207 .common = {208 .reg = 0x05c,209 .features = CCU_FEATURE_FIXED_PREDIV,210 .hw.init = CLK_HW_INIT_PARENTS("ahb2",211 ahb2_parents,212 &ccu_mux_ops,213 0),214 },215};216 217static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",218 0x060, BIT(5), 0);219static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",220 0x060, BIT(6), 0);221static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",222 0x060, BIT(8), 0);223static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",224 0x060, BIT(9), 0);225static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",226 0x060, BIT(10), 0);227static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",228 0x060, BIT(13), 0);229static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",230 0x060, BIT(14), 0);231static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",232 0x060, BIT(17), 0);233static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",234 0x060, BIT(18), 0);235static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",236 0x060, BIT(19), 0);237static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",238 0x060, BIT(20), 0);239static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",240 0x060, BIT(21), 0);241static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",242 0x060, BIT(23), 0);243static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",244 0x060, BIT(24), 0);245static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",246 0x060, BIT(25), 0);247static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",248 0x060, BIT(26), 0);249static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",250 0x060, BIT(27), 0);251static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",252 0x060, BIT(28), 0);253static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",254 0x060, BIT(29), 0);255static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",256 0x060, BIT(30), 0);257static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",258 0x060, BIT(31), 0);259 260static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",261 0x064, BIT(0), 0);262static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",263 0x064, BIT(3), 0);264static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",265 0x064, BIT(4), 0);266static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",267 0x064, BIT(5), 0);268static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",269 0x064, BIT(8), 0);270static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",271 0x064, BIT(9), 0);272static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",273 0x064, BIT(11), 0);274static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",275 0x064, BIT(12), 0);276static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",277 0x064, BIT(20), 0);278static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",279 0x064, BIT(21), 0);280static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",281 0x064, BIT(22), 0);282 283static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",284 0x068, BIT(0), 0);285static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",286 0x068, BIT(1), 0);287static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",288 0x068, BIT(5), 0);289static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",290 0x068, BIT(8), 0);291static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",292 0x068, BIT(12), 0);293static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",294 0x068, BIT(13), 0);295static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",296 0x068, BIT(14), 0);297 298static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",299 0x06c, BIT(0), 0);300static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",301 0x06c, BIT(1), 0);302static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",303 0x06c, BIT(2), 0);304static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",305 0x06c, BIT(16), 0);306static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",307 0x06c, BIT(17), 0);308static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",309 0x06c, BIT(18), 0);310static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",311 0x06c, BIT(19), 0);312static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",313 0x06c, BIT(20), 0);314static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",315 0x06c, BIT(21), 0);316 317static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",318 0x070, BIT(0), 0);319static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",320 0x070, BIT(7), 0);321 322static struct clk_div_table ths_div_table[] = {323 { .val = 0, .div = 1 },324 { .val = 1, .div = 2 },325 { .val = 2, .div = 4 },326 { .val = 3, .div = 6 },327 { /* Sentinel */ },328};329static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",330 0x074, 0, 2, ths_div_table, BIT(31), 0);331 332static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",333 "pll-periph1" };334static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,335 0, 4, /* M */336 16, 2, /* P */337 24, 2, /* mux */338 BIT(31), /* gate */339 0);340 341static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,342 0, 4, /* M */343 16, 2, /* P */344 24, 2, /* mux */345 BIT(31), /* gate */346 0);347 348static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",349 0x088, 20, 3, 0);350static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",351 0x088, 8, 3, 0);352 353static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,354 0, 4, /* M */355 16, 2, /* P */356 24, 2, /* mux */357 BIT(31), /* gate */358 0);359 360static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",361 0x08c, 20, 3, 0);362static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",363 0x08c, 8, 3, 0);364 365static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,366 0, 4, /* M */367 16, 2, /* P */368 24, 2, /* mux */369 BIT(31), /* gate */370 0);371 372static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",373 0x090, 20, 3, 0);374static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",375 0x090, 8, 3, 0);376 377static const char * const ts_parents[] = { "osc24M", "pll-periph0", };378static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,379 0, 4, /* M */380 16, 2, /* P */381 24, 2, /* mux */382 BIT(31), /* gate */383 0);384 385static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,386 0, 4, /* M */387 16, 2, /* P */388 24, 2, /* mux */389 BIT(31), /* gate */390 0);391 392static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,393 0, 4, /* M */394 16, 2, /* P */395 24, 2, /* mux */396 BIT(31), /* gate */397 0);398 399static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,400 0, 4, /* M */401 16, 2, /* P */402 24, 2, /* mux */403 BIT(31), /* gate */404 0);405 406static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",407 "pll-audio-2x", "pll-audio" };408static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,409 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);410 411static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,412 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);413 414static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,415 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);416 417static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",418 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);419 420static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",421 0x0cc, BIT(8), 0);422static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",423 0x0cc, BIT(9), 0);424static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",425 0x0cc, BIT(10), 0);426static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",427 0x0cc, BIT(11), 0);428static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",429 0x0cc, BIT(16), 0);430static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",431 0x0cc, BIT(17), 0);432static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",433 0x0cc, BIT(18), 0);434static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",435 0x0cc, BIT(19), 0);436 437/* H3 has broken MDFS hardware, so the mux/divider cannot be changed. */438static CLK_FIXED_FACTOR_HW(h3_dram_clk, "dram",439 &pll_ddr_clk.common.hw,440 1, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);441 442static const char * const h5_dram_parents[] = { "pll-ddr", "pll-periph0-2x" };443static SUNXI_CCU_M_WITH_MUX(h5_dram_clk, "dram", h5_dram_parents,444 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);445 446static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",447 0x100, BIT(0), 0);448static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",449 0x100, BIT(1), 0);450static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",451 0x100, BIT(2), 0);452static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",453 0x100, BIT(3), 0);454 455static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };456static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,457 0x104, 0, 4, 24, 3, BIT(31),458 CLK_SET_RATE_PARENT);459 460static const char * const tcon_parents[] = { "pll-video" };461static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,462 0x118, 0, 4, 24, 3, BIT(31),463 CLK_SET_RATE_PARENT);464 465static const char * const tve_parents[] = { "pll-de", "pll-periph1" };466static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,467 0x120, 0, 4, 24, 3, BIT(31), 0);468 469static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };470static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,471 0x124, 0, 4, 24, 3, BIT(31), 0);472 473static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",474 0x130, BIT(31), 0);475 476static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };477static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,478 0x134, 16, 4, 24, 3, BIT(31), 0);479 480static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };481static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,482 0x134, 0, 5, 8, 3, BIT(15), 0);483 484static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",485 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);486 487static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",488 0x140, BIT(31), CLK_SET_RATE_PARENT);489static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",490 0x144, BIT(31), 0);491 492static const char * const hdmi_parents[] = { "pll-video" };493static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,494 0x150, 0, 4, 24, 2, BIT(31),495 CLK_SET_RATE_PARENT);496 497static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",498 0x154, BIT(31), 0);499 500static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };501static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,502 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);503 504static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",505 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);506 507static struct ccu_common *sun8i_h3_ccu_clks[] = {508 &pll_cpux_clk.common,509 &pll_audio_base_clk.common,510 &pll_video_clk.common,511 &pll_ve_clk.common,512 &pll_ddr_clk.common,513 &pll_periph0_clk.common,514 &pll_gpu_clk.common,515 &pll_periph1_clk.common,516 &pll_de_clk.common,517 &cpux_clk.common,518 &axi_clk.common,519 &ahb1_clk.common,520 &apb1_clk.common,521 &apb2_clk.common,522 &ahb2_clk.common,523 &bus_ce_clk.common,524 &bus_dma_clk.common,525 &bus_mmc0_clk.common,526 &bus_mmc1_clk.common,527 &bus_mmc2_clk.common,528 &bus_nand_clk.common,529 &bus_dram_clk.common,530 &bus_emac_clk.common,531 &bus_ts_clk.common,532 &bus_hstimer_clk.common,533 &bus_spi0_clk.common,534 &bus_spi1_clk.common,535 &bus_otg_clk.common,536 &bus_ehci0_clk.common,537 &bus_ehci1_clk.common,538 &bus_ehci2_clk.common,539 &bus_ehci3_clk.common,540 &bus_ohci0_clk.common,541 &bus_ohci1_clk.common,542 &bus_ohci2_clk.common,543 &bus_ohci3_clk.common,544 &bus_ve_clk.common,545 &bus_tcon0_clk.common,546 &bus_tcon1_clk.common,547 &bus_deinterlace_clk.common,548 &bus_csi_clk.common,549 &bus_tve_clk.common,550 &bus_hdmi_clk.common,551 &bus_de_clk.common,552 &bus_gpu_clk.common,553 &bus_msgbox_clk.common,554 &bus_spinlock_clk.common,555 &bus_codec_clk.common,556 &bus_spdif_clk.common,557 &bus_pio_clk.common,558 &bus_ths_clk.common,559 &bus_i2s0_clk.common,560 &bus_i2s1_clk.common,561 &bus_i2s2_clk.common,562 &bus_i2c0_clk.common,563 &bus_i2c1_clk.common,564 &bus_i2c2_clk.common,565 &bus_uart0_clk.common,566 &bus_uart1_clk.common,567 &bus_uart2_clk.common,568 &bus_uart3_clk.common,569 &bus_scr0_clk.common,570 &bus_scr1_clk.common,571 &bus_ephy_clk.common,572 &bus_dbg_clk.common,573 &ths_clk.common,574 &nand_clk.common,575 &mmc0_clk.common,576 &mmc0_sample_clk.common,577 &mmc0_output_clk.common,578 &mmc1_clk.common,579 &mmc1_sample_clk.common,580 &mmc1_output_clk.common,581 &mmc2_clk.common,582 &mmc2_sample_clk.common,583 &mmc2_output_clk.common,584 &ts_clk.common,585 &ce_clk.common,586 &spi0_clk.common,587 &spi1_clk.common,588 &i2s0_clk.common,589 &i2s1_clk.common,590 &i2s2_clk.common,591 &spdif_clk.common,592 &usb_phy0_clk.common,593 &usb_phy1_clk.common,594 &usb_phy2_clk.common,595 &usb_phy3_clk.common,596 &usb_ohci0_clk.common,597 &usb_ohci1_clk.common,598 &usb_ohci2_clk.common,599 &usb_ohci3_clk.common,600 &h5_dram_clk.common,601 &dram_ve_clk.common,602 &dram_csi_clk.common,603 &dram_deinterlace_clk.common,604 &dram_ts_clk.common,605 &de_clk.common,606 &tcon_clk.common,607 &tve_clk.common,608 &deinterlace_clk.common,609 &csi_misc_clk.common,610 &csi_sclk_clk.common,611 &csi_mclk_clk.common,612 &ve_clk.common,613 &ac_dig_clk.common,614 &avs_clk.common,615 &hdmi_clk.common,616 &hdmi_ddc_clk.common,617 &mbus_clk.common,618 &gpu_clk.common,619};620 621static const struct clk_hw *clk_parent_pll_audio[] = {622 &pll_audio_base_clk.common.hw623};624 625/* We hardcode the divider to 1 for now */626static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",627 clk_parent_pll_audio,628 1, 1, CLK_SET_RATE_PARENT);629static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",630 clk_parent_pll_audio,631 2, 1, CLK_SET_RATE_PARENT);632static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",633 clk_parent_pll_audio,634 1, 1, CLK_SET_RATE_PARENT);635static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",636 clk_parent_pll_audio,637 1, 2, CLK_SET_RATE_PARENT);638static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",639 &pll_periph0_clk.common.hw,640 1, 2, 0);641 642static struct clk_hw_onecell_data sun8i_h3_hw_clks = {643 .hws = {644 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,645 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,646 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,647 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,648 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,649 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,650 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,651 [CLK_PLL_VE] = &pll_ve_clk.common.hw,652 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,653 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,654 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,655 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,656 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,657 [CLK_PLL_DE] = &pll_de_clk.common.hw,658 [CLK_CPUX] = &cpux_clk.common.hw,659 [CLK_AXI] = &axi_clk.common.hw,660 [CLK_AHB1] = &ahb1_clk.common.hw,661 [CLK_APB1] = &apb1_clk.common.hw,662 [CLK_APB2] = &apb2_clk.common.hw,663 [CLK_AHB2] = &ahb2_clk.common.hw,664 [CLK_BUS_CE] = &bus_ce_clk.common.hw,665 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,666 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,667 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,668 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,669 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,670 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,671 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,672 [CLK_BUS_TS] = &bus_ts_clk.common.hw,673 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,674 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,675 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,676 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,677 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,678 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,679 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,680 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,681 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,682 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,683 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,684 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,685 [CLK_BUS_VE] = &bus_ve_clk.common.hw,686 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,687 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,688 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,689 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,690 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,691 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,692 [CLK_BUS_DE] = &bus_de_clk.common.hw,693 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,694 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,695 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,696 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,697 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,698 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,699 [CLK_BUS_THS] = &bus_ths_clk.common.hw,700 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,701 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,702 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,703 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,704 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,705 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,706 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,707 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,708 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,709 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,710 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,711 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,712 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,713 [CLK_THS] = &ths_clk.common.hw,714 [CLK_NAND] = &nand_clk.common.hw,715 [CLK_MMC0] = &mmc0_clk.common.hw,716 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,717 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,718 [CLK_MMC1] = &mmc1_clk.common.hw,719 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,720 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,721 [CLK_MMC2] = &mmc2_clk.common.hw,722 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,723 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,724 [CLK_TS] = &ts_clk.common.hw,725 [CLK_CE] = &ce_clk.common.hw,726 [CLK_SPI0] = &spi0_clk.common.hw,727 [CLK_SPI1] = &spi1_clk.common.hw,728 [CLK_I2S0] = &i2s0_clk.common.hw,729 [CLK_I2S1] = &i2s1_clk.common.hw,730 [CLK_I2S2] = &i2s2_clk.common.hw,731 [CLK_SPDIF] = &spdif_clk.common.hw,732 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,733 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,734 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,735 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,736 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,737 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,738 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,739 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,740 [CLK_DRAM] = &h3_dram_clk.hw,741 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,742 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,743 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,744 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,745 [CLK_DE] = &de_clk.common.hw,746 [CLK_TCON0] = &tcon_clk.common.hw,747 [CLK_TVE] = &tve_clk.common.hw,748 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,749 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,750 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,751 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,752 [CLK_VE] = &ve_clk.common.hw,753 [CLK_AC_DIG] = &ac_dig_clk.common.hw,754 [CLK_AVS] = &avs_clk.common.hw,755 [CLK_HDMI] = &hdmi_clk.common.hw,756 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,757 [CLK_MBUS] = &mbus_clk.common.hw,758 [CLK_GPU] = &gpu_clk.common.hw,759 },760 .num = CLK_NUMBER_H3,761};762 763static struct clk_hw_onecell_data sun50i_h5_hw_clks = {764 .hws = {765 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,766 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,767 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,768 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,769 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,770 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,771 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,772 [CLK_PLL_VE] = &pll_ve_clk.common.hw,773 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,774 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,775 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,776 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,777 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,778 [CLK_PLL_DE] = &pll_de_clk.common.hw,779 [CLK_CPUX] = &cpux_clk.common.hw,780 [CLK_AXI] = &axi_clk.common.hw,781 [CLK_AHB1] = &ahb1_clk.common.hw,782 [CLK_APB1] = &apb1_clk.common.hw,783 [CLK_APB2] = &apb2_clk.common.hw,784 [CLK_AHB2] = &ahb2_clk.common.hw,785 [CLK_BUS_CE] = &bus_ce_clk.common.hw,786 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,787 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,788 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,789 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,790 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,791 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,792 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,793 [CLK_BUS_TS] = &bus_ts_clk.common.hw,794 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,795 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,796 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,797 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,798 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,799 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,800 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,801 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,802 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,803 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,804 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,805 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,806 [CLK_BUS_VE] = &bus_ve_clk.common.hw,807 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,808 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,809 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,810 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,811 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,812 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,813 [CLK_BUS_DE] = &bus_de_clk.common.hw,814 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,815 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,816 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,817 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,818 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,819 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,820 [CLK_BUS_THS] = &bus_ths_clk.common.hw,821 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,822 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,823 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,824 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,825 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,826 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,827 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,828 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,829 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,830 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,831 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,832 [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,833 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,834 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,835 [CLK_THS] = &ths_clk.common.hw,836 [CLK_NAND] = &nand_clk.common.hw,837 [CLK_MMC0] = &mmc0_clk.common.hw,838 [CLK_MMC1] = &mmc1_clk.common.hw,839 [CLK_MMC2] = &mmc2_clk.common.hw,840 [CLK_TS] = &ts_clk.common.hw,841 [CLK_CE] = &ce_clk.common.hw,842 [CLK_SPI0] = &spi0_clk.common.hw,843 [CLK_SPI1] = &spi1_clk.common.hw,844 [CLK_I2S0] = &i2s0_clk.common.hw,845 [CLK_I2S1] = &i2s1_clk.common.hw,846 [CLK_I2S2] = &i2s2_clk.common.hw,847 [CLK_SPDIF] = &spdif_clk.common.hw,848 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,849 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,850 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,851 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,852 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,853 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,854 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,855 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,856 [CLK_DRAM] = &h5_dram_clk.common.hw,857 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,858 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,859 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,860 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,861 [CLK_DE] = &de_clk.common.hw,862 [CLK_TCON0] = &tcon_clk.common.hw,863 [CLK_TVE] = &tve_clk.common.hw,864 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,865 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,866 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,867 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,868 [CLK_VE] = &ve_clk.common.hw,869 [CLK_AC_DIG] = &ac_dig_clk.common.hw,870 [CLK_AVS] = &avs_clk.common.hw,871 [CLK_HDMI] = &hdmi_clk.common.hw,872 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,873 [CLK_MBUS] = &mbus_clk.common.hw,874 [CLK_GPU] = &gpu_clk.common.hw,875 },876 .num = CLK_NUMBER_H5,877};878 879static struct ccu_reset_map sun8i_h3_ccu_resets[] = {880 [RST_USB_PHY0] = { 0x0cc, BIT(0) },881 [RST_USB_PHY1] = { 0x0cc, BIT(1) },882 [RST_USB_PHY2] = { 0x0cc, BIT(2) },883 [RST_USB_PHY3] = { 0x0cc, BIT(3) },884 885 [RST_MBUS] = { 0x0fc, BIT(31) },886 887 [RST_BUS_CE] = { 0x2c0, BIT(5) },888 [RST_BUS_DMA] = { 0x2c0, BIT(6) },889 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },890 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },891 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },892 [RST_BUS_NAND] = { 0x2c0, BIT(13) },893 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },894 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },895 [RST_BUS_TS] = { 0x2c0, BIT(18) },896 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },897 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },898 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },899 [RST_BUS_OTG] = { 0x2c0, BIT(23) },900 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },901 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },902 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },903 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },904 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },905 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },906 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },907 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },908 909 [RST_BUS_VE] = { 0x2c4, BIT(0) },910 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },911 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },912 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },913 [RST_BUS_CSI] = { 0x2c4, BIT(8) },914 [RST_BUS_TVE] = { 0x2c4, BIT(9) },915 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },916 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },917 [RST_BUS_DE] = { 0x2c4, BIT(12) },918 [RST_BUS_GPU] = { 0x2c4, BIT(20) },919 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },920 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },921 [RST_BUS_DBG] = { 0x2c4, BIT(31) },922 923 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },924 925 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },926 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },927 [RST_BUS_THS] = { 0x2d0, BIT(8) },928 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },929 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },930 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },931 932 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },933 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },934 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },935 [RST_BUS_UART0] = { 0x2d8, BIT(16) },936 [RST_BUS_UART1] = { 0x2d8, BIT(17) },937 [RST_BUS_UART2] = { 0x2d8, BIT(18) },938 [RST_BUS_UART3] = { 0x2d8, BIT(19) },939 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },940};941 942static struct ccu_reset_map sun50i_h5_ccu_resets[] = {943 [RST_USB_PHY0] = { 0x0cc, BIT(0) },944 [RST_USB_PHY1] = { 0x0cc, BIT(1) },945 [RST_USB_PHY2] = { 0x0cc, BIT(2) },946 [RST_USB_PHY3] = { 0x0cc, BIT(3) },947 948 [RST_MBUS] = { 0x0fc, BIT(31) },949 950 [RST_BUS_CE] = { 0x2c0, BIT(5) },951 [RST_BUS_DMA] = { 0x2c0, BIT(6) },952 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },953 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },954 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },955 [RST_BUS_NAND] = { 0x2c0, BIT(13) },956 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },957 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },958 [RST_BUS_TS] = { 0x2c0, BIT(18) },959 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },960 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },961 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },962 [RST_BUS_OTG] = { 0x2c0, BIT(23) },963 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },964 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },965 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },966 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },967 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },968 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },969 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },970 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },971 972 [RST_BUS_VE] = { 0x2c4, BIT(0) },973 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },974 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },975 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },976 [RST_BUS_CSI] = { 0x2c4, BIT(8) },977 [RST_BUS_TVE] = { 0x2c4, BIT(9) },978 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },979 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },980 [RST_BUS_DE] = { 0x2c4, BIT(12) },981 [RST_BUS_GPU] = { 0x2c4, BIT(20) },982 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },983 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },984 [RST_BUS_DBG] = { 0x2c4, BIT(31) },985 986 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },987 988 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },989 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },990 [RST_BUS_THS] = { 0x2d0, BIT(8) },991 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },992 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },993 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },994 995 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },996 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },997 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },998 [RST_BUS_UART0] = { 0x2d8, BIT(16) },999 [RST_BUS_UART1] = { 0x2d8, BIT(17) },1000 [RST_BUS_UART2] = { 0x2d8, BIT(18) },1001 [RST_BUS_UART3] = { 0x2d8, BIT(19) },1002 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },1003 [RST_BUS_SCR1] = { 0x2d8, BIT(20) },1004};1005 1006static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {1007 .ccu_clks = sun8i_h3_ccu_clks,1008 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),1009 1010 .hw_clks = &sun8i_h3_hw_clks,1011 1012 .resets = sun8i_h3_ccu_resets,1013 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),1014};1015 1016static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {1017 .ccu_clks = sun8i_h3_ccu_clks,1018 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),1019 1020 .hw_clks = &sun50i_h5_hw_clks,1021 1022 .resets = sun50i_h5_ccu_resets,1023 .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),1024};1025 1026static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {1027 .common = &pll_cpux_clk.common,1028 /* copy from pll_cpux_clk */1029 .enable = BIT(31),1030 .lock = BIT(28),1031};1032 1033static struct ccu_mux_nb sun8i_h3_cpu_nb = {1034 .common = &cpux_clk.common,1035 .cm = &cpux_clk.mux,1036 .delay_us = 1, /* > 8 clock cycles at 24 MHz */1037 .bypass_index = 1, /* index of 24 MHz oscillator */1038};1039 1040static int sun8i_h3_ccu_probe(struct platform_device *pdev)1041{1042 const struct sunxi_ccu_desc *desc;1043 void __iomem *reg;1044 int ret;1045 u32 val;1046 1047 desc = of_device_get_match_data(&pdev->dev);1048 if (!desc)1049 return -EINVAL;1050 1051 reg = devm_platform_ioremap_resource(pdev, 0);1052 if (IS_ERR(reg))1053 return PTR_ERR(reg);1054 1055 /* Force the PLL-Audio-1x divider to 1 */1056 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);1057 val &= ~GENMASK(19, 16);1058 writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);1059 1060 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, desc);1061 if (ret)1062 return ret;1063 1064 /* Gate then ungate PLL CPU after any rate changes */1065 ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);1066 1067 /* Reparent CPU during PLL CPU rate changes */1068 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,1069 &sun8i_h3_cpu_nb);1070 1071 return 0;1072}1073 1074static const struct of_device_id sun8i_h3_ccu_ids[] = {1075 {1076 .compatible = "allwinner,sun8i-h3-ccu",1077 .data = &sun8i_h3_ccu_desc,1078 },1079 {1080 .compatible = "allwinner,sun50i-h5-ccu",1081 .data = &sun50i_h5_ccu_desc,1082 },1083 { }1084};1085MODULE_DEVICE_TABLE(of, sun8i_h3_ccu_ids);1086 1087static struct platform_driver sun8i_h3_ccu_driver = {1088 .probe = sun8i_h3_ccu_probe,1089 .driver = {1090 .name = "sun8i-h3-ccu",1091 .suppress_bind_attrs = true,1092 .of_match_table = sun8i_h3_ccu_ids,1093 },1094};1095module_platform_driver(sun8i_h3_ccu_driver);1096 1097MODULE_IMPORT_NS(SUNXI_CCU);1098MODULE_DESCRIPTION("Support for the Allwinner H3 CCU");1099MODULE_LICENSE("GPL");1100