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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Maxime Ripard4 *5 * Maxime Ripard <maxime.ripard@free-electrons.com>6 */7 8#ifndef _CCU_SUN8I_H3_H_9#define _CCU_SUN8I_H3_H_10 11#include <dt-bindings/clock/sun8i-h3-ccu.h>12#include <dt-bindings/reset/sun8i-h3-ccu.h>13 14#define CLK_PLL_CPUX 015#define CLK_PLL_AUDIO_BASE 116#define CLK_PLL_AUDIO 217#define CLK_PLL_AUDIO_2X 318#define CLK_PLL_AUDIO_4X 419#define CLK_PLL_AUDIO_8X 520 21/* PLL_VIDEO is exported */22 23#define CLK_PLL_VE 724#define CLK_PLL_DDR 825 26/* PLL_PERIPH0 exported for PRCM */27 28#define CLK_PLL_PERIPH0_2X 1029#define CLK_PLL_GPU 1130#define CLK_PLL_PERIPH1 1231#define CLK_PLL_DE 1332 33/* The CPUX clock is exported */34 35#define CLK_AXI 1536#define CLK_AHB1 1637#define CLK_APB1 1738#define CLK_APB2 1839#define CLK_AHB2 1940 41/* All the bus gates are exported */42 43/* The first bunch of module clocks are exported */44 45/* All the DRAM gates are exported */46 47/* Some more module clocks are exported */48 49#define CLK_NUMBER_H3 (CLK_GPU + 1)50#define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1)51 52#endif /* _CCU_SUN8I_H3_H_ */53