61 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>4 */5 6#ifndef _CCU_SUN8I_R40_H_7#define _CCU_SUN8I_R40_H_8 9#include <dt-bindings/clock/sun8i-r40-ccu.h>10#include <dt-bindings/reset/sun8i-r40-ccu.h>11 12#define CLK_OSC_12M 013#define CLK_PLL_CPU 114#define CLK_PLL_AUDIO_BASE 215#define CLK_PLL_AUDIO 316#define CLK_PLL_AUDIO_2X 417#define CLK_PLL_AUDIO_4X 518#define CLK_PLL_AUDIO_8X 619 20/* PLL_VIDEO0 is exported */21 22#define CLK_PLL_VIDEO0_2X 823#define CLK_PLL_VE 924#define CLK_PLL_DDR0 1025#define CLK_PLL_PERIPH0 1126#define CLK_PLL_PERIPH0_SATA 1227#define CLK_PLL_PERIPH0_2X 1328#define CLK_PLL_PERIPH1 1429#define CLK_PLL_PERIPH1_2X 1530 31/* PLL_VIDEO1 is exported */32 33#define CLK_PLL_VIDEO1_2X 1734#define CLK_PLL_SATA 1835#define CLK_PLL_SATA_OUT 1936#define CLK_PLL_GPU 2037#define CLK_PLL_MIPI 2138#define CLK_PLL_DE 2239#define CLK_PLL_DDR1 2340 41/* The CPU clock is exported */42 43#define CLK_AXI 2544#define CLK_AHB1 2645#define CLK_APB1 2746#define CLK_APB2 2847 48/* All the bus gates are exported */49 50/* The first bunch of module clocks are exported */51 52#define CLK_DRAM 13253 54/* All the DRAM gates are exported */55 56/* Some more module clocks are exported */57 58#define CLK_NUMBER (CLK_OUTB + 1)59 60#endif /* _CCU_SUN8I_R40_H_ */61