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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>4 *5 * Based on ccu-sun8i-h3.h, which is:6 * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>7 */8 9#ifndef _CCU_SUN8I_V3S_H_10#define _CCU_SUN8I_V3S_H_11 12#include <dt-bindings/clock/sun8i-v3s-ccu.h>13#include <dt-bindings/reset/sun8i-v3s-ccu.h>14 15#define CLK_PLL_CPU 016#define CLK_PLL_AUDIO_BASE 117#define CLK_PLL_AUDIO 218#define CLK_PLL_AUDIO_2X 319#define CLK_PLL_AUDIO_4X 420#define CLK_PLL_AUDIO_8X 521#define CLK_PLL_VIDEO 622#define CLK_PLL_VE 723#define CLK_PLL_DDR0 824#define CLK_PLL_PERIPH0 925#define CLK_PLL_PERIPH0_2X 1026#define CLK_PLL_ISP 1127#define CLK_PLL_PERIPH1 1228/* Reserve one number for not implemented and not used PLL_DDR1 */29 30/* The CPU clock is exported */31 32#define CLK_AXI 1533#define CLK_AHB1 1634#define CLK_APB1 1735#define CLK_APB2 1836#define CLK_AHB2 1937 38/* All the bus gates are exported */39 40/* The first bunch of module clocks are exported */41 42#define CLK_DRAM 5843 44/* All the DRAM gates are exported */45 46/* Some more module clocks are exported */47 48#define CLK_MBUS 7249 50/* And the GPU module clock is exported */51 52#define CLK_PLL_DDR1 7453 54#endif /* _CCU_SUN8I_V3S_H_ */55