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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright 2016 Chen-Yu Tsai4 *5 * Chen-Yu Tsai <wens@csie.org>6 */7 8#ifndef _CCU_SUN9I_A80_H_9#define _CCU_SUN9I_A80_H_10 11#include <dt-bindings/clock/sun9i-a80-ccu.h>12#include <dt-bindings/reset/sun9i-a80-ccu.h>13 14#define CLK_PLL_C0CPUX 015#define CLK_PLL_C1CPUX 116 17/* pll-audio and pll-periph0 are exported to the PRCM block */18 19#define CLK_PLL_VE 420#define CLK_PLL_DDR 521#define CLK_PLL_VIDEO0 622#define CLK_PLL_VIDEO1 723#define CLK_PLL_GPU 824#define CLK_PLL_DE 925#define CLK_PLL_ISP 1026#define CLK_PLL_PERIPH1 1127 28/* The CPUX clocks are exported */29 30#define CLK_ATB0 1431#define CLK_AXI0 1532#define CLK_ATB1 1633#define CLK_AXI1 1734#define CLK_GTBUS 1835#define CLK_AHB0 1936#define CLK_AHB1 2037#define CLK_AHB2 2138#define CLK_APB0 2239#define CLK_APB1 2340#define CLK_CCI400 2441#define CLK_ATS 2542#define CLK_TRACE 2643 44/* module clocks and bus gates exported */45 46#define CLK_NUMBER (CLK_BUS_UART5 + 1)47 48#endif /* _CCU_SUN9I_A80_H_ */49