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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>4 *5 */6 7#ifndef _CCU_SUNIV_F1C100S_H_8#define _CCU_SUNIV_F1C100S_H_9 10#include <dt-bindings/clock/suniv-ccu-f1c100s.h>11#include <dt-bindings/reset/suniv-ccu-f1c100s.h>12 13#define CLK_PLL_CPU 014#define CLK_PLL_AUDIO_BASE 115#define CLK_PLL_AUDIO 216#define CLK_PLL_AUDIO_2X 317#define CLK_PLL_AUDIO_4X 418#define CLK_PLL_AUDIO_8X 519#define CLK_PLL_VIDEO 620#define CLK_PLL_VIDEO_2X 721#define CLK_PLL_VE 822#define CLK_PLL_DDR0 923#define CLK_PLL_PERIPH 1024 25/* CPU clock is exported */26 27#define CLK_AHB 1228#define CLK_APB 1329 30/* All bus gates, DRAM gates and mod clocks are exported */31 32#define CLK_NUMBER (CLK_IR + 1)33 34#endif /* _CCU_SUNIV_F1C100S_H_ */35