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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright 2015 Maxime Ripard4 *5 * Maxime Ripard <maxime.ripard@free-electrons.com>6 */7 8#include <linux/clk.h>9#include <linux/clk-provider.h>10#include <linux/io.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/slab.h>14#include <linux/spinlock.h>15 16static DEFINE_SPINLOCK(gates_lock);17 18static void __init sunxi_simple_gates_setup(struct device_node *node,19 const int protected[],20 int nprotected)21{22 struct clk_onecell_data *clk_data;23 const char *clk_parent, *clk_name;24 struct resource res;25 void __iomem *clk_reg;26 void __iomem *reg;27 int number, i = 0, j;28 u8 clk_bit;29 u32 index;30 31 reg = of_io_request_and_map(node, 0, of_node_full_name(node));32 if (IS_ERR(reg))33 return;34 35 clk_parent = of_clk_get_parent_name(node, 0);36 37 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);38 if (!clk_data)39 goto err_unmap;40 41 number = of_property_count_u32_elems(node, "clock-indices");42 of_property_read_u32_index(node, "clock-indices", number - 1, &number);43 44 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);45 if (!clk_data->clks)46 goto err_free_data;47 48 of_property_for_each_u32(node, "clock-indices", index) {49 of_property_read_string_index(node, "clock-output-names",50 i, &clk_name);51 52 clk_reg = reg + 4 * (index / 32);53 clk_bit = index % 32;54 55 clk_data->clks[index] = clk_register_gate(NULL, clk_name,56 clk_parent, 0,57 clk_reg,58 clk_bit,59 0, &gates_lock);60 i++;61 62 if (IS_ERR(clk_data->clks[index])) {63 WARN_ON(true);64 continue;65 }66 67 for (j = 0; j < nprotected; j++)68 if (protected[j] == index)69 clk_prepare_enable(clk_data->clks[index]);70 71 }72 73 clk_data->clk_num = number + 1;74 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);75 76 return;77 78err_free_data:79 kfree(clk_data);80err_unmap:81 iounmap(reg);82 of_address_to_resource(node, 0, &res);83 release_mem_region(res.start, resource_size(&res));84}85 86static void __init sunxi_simple_gates_init(struct device_node *node)87{88 sunxi_simple_gates_setup(node, NULL, 0);89}90 91CLK_OF_DECLARE(sun4i_a10_gates, "allwinner,sun4i-a10-gates-clk",92 sunxi_simple_gates_init);93CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",94 sunxi_simple_gates_init);95CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",96 sunxi_simple_gates_init);97CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",98 sunxi_simple_gates_init);99CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",100 sunxi_simple_gates_init);101CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",102 sunxi_simple_gates_init);103CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",104 sunxi_simple_gates_init);105CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",106 sunxi_simple_gates_init);107CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",108 sunxi_simple_gates_init);109CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",110 sunxi_simple_gates_init);111CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",112 sunxi_simple_gates_init);113CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",114 sunxi_simple_gates_init);115CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",116 sunxi_simple_gates_init);117CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",118 sunxi_simple_gates_init);119CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",120 sunxi_simple_gates_init);121CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",122 sunxi_simple_gates_init);123CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",124 sunxi_simple_gates_init);125CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk",126 sunxi_simple_gates_init);127CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",128 sunxi_simple_gates_init);129CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",130 sunxi_simple_gates_init);131CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",132 sunxi_simple_gates_init);133CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",134 sunxi_simple_gates_init);135CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",136 sunxi_simple_gates_init);137CLK_OF_DECLARE(sun9i_a80_apbs, "allwinner,sun9i-a80-apbs-gates-clk",138 sunxi_simple_gates_init);139 140static const int sun4i_a10_ahb_critical_clocks[] __initconst = {141 14, /* ahb_sdram */142};143 144static void __init sun4i_a10_ahb_init(struct device_node *node)145{146 sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,147 ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));148}149CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",150 sun4i_a10_ahb_init);151CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",152 sun4i_a10_ahb_init);153CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",154 sun4i_a10_ahb_init);155CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",156 sun4i_a10_ahb_init);157 158static const int sun4i_a10_dram_critical_clocks[] __initconst = {159 15, /* dram_output */160};161 162static void __init sun4i_a10_dram_init(struct device_node *node)163{164 sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,165 ARRAY_SIZE(sun4i_a10_dram_critical_clocks));166}167CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",168 sun4i_a10_dram_init);169