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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * clk-dfll.c - Tegra DFLL clock source common code4 *5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.6 *7 * Aleksandr Frid <afrid@nvidia.com>8 * Paul Walmsley <pwalmsley@nvidia.com>9 *10 * This library is for the DVCO and DFLL IP blocks on the Tegra12411 * SoC. These IP blocks together are also known at NVIDIA as12 * "CL-DVFS". To try to avoid confusion, this code refers to them13 * collectively as the "DFLL."14 *15 * The DFLL is a root clocksource which tolerates some amount of16 * supply voltage noise. Tegra124 uses it to clock the fast CPU17 * complex when the target CPU speed is above a particular rate. The18 * DFLL can be operated in either open-loop mode or closed-loop mode.19 * In open-loop mode, the DFLL generates an output clock appropriate20 * to the supply voltage. In closed-loop mode, when configured with a21 * target frequency, the DFLL minimizes supply voltage while22 * delivering an average frequency equal to the target.23 *24 * Devices clocked by the DFLL must be able to tolerate frequency25 * variation. In the case of the CPU, it's important to note that the26 * CPU cycle time will vary. This has implications for27 * performance-measurement code and any code that relies on the CPU28 * cycle time to delay for a certain length of time.29 */30 31#include <linux/clk.h>32#include <linux/clk-provider.h>33#include <linux/debugfs.h>34#include <linux/device.h>35#include <linux/err.h>36#include <linux/i2c.h>37#include <linux/io.h>38#include <linux/kernel.h>39#include <linux/module.h>40#include <linux/of.h>41#include <linux/pinctrl/consumer.h>42#include <linux/pm_opp.h>43#include <linux/pm_runtime.h>44#include <linux/regmap.h>45#include <linux/regulator/consumer.h>46#include <linux/reset.h>47#include <linux/seq_file.h>48 49#include "clk-dfll.h"50#include "cvb.h"51 52/*53 * DFLL control registers - access via dfll_{readl,writel}54 */55 56/* DFLL_CTRL: DFLL control register */57#define DFLL_CTRL 0x0058#define DFLL_CTRL_MODE_MASK 0x0359 60/* DFLL_CONFIG: DFLL sample rate control */61#define DFLL_CONFIG 0x0462#define DFLL_CONFIG_DIV_MASK 0xff63#define DFLL_CONFIG_DIV_PRESCALE 3264 65/* DFLL_PARAMS: tuning coefficients for closed loop integrator */66#define DFLL_PARAMS 0x0867#define DFLL_PARAMS_CG_SCALE (0x1 << 24)68#define DFLL_PARAMS_FORCE_MODE_SHIFT 2269#define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)70#define DFLL_PARAMS_CF_PARAM_SHIFT 1671#define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)72#define DFLL_PARAMS_CI_PARAM_SHIFT 873#define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)74#define DFLL_PARAMS_CG_PARAM_SHIFT 075#define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)76 77/* DFLL_TUNE0: delay line configuration register 0 */78#define DFLL_TUNE0 0x0c79 80/* DFLL_TUNE1: delay line configuration register 1 */81#define DFLL_TUNE1 0x1082 83/* DFLL_FREQ_REQ: target DFLL frequency control */84#define DFLL_FREQ_REQ 0x1485#define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28)86#define DFLL_FREQ_REQ_FORCE_SHIFT 1687#define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)88#define FORCE_MAX 204789#define FORCE_MIN -204890#define DFLL_FREQ_REQ_SCALE_SHIFT 891#define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)92#define DFLL_FREQ_REQ_SCALE_MAX 25693#define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7)94#define DFLL_FREQ_REQ_MULT_SHIFT 095#define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)96#define FREQ_MAX 12797 98/* DFLL_DROOP_CTRL: droop prevention control */99#define DFLL_DROOP_CTRL 0x1c100 101/* DFLL_OUTPUT_CFG: closed loop mode control registers */102/* NOTE: access via dfll_i2c_{readl,writel} */103#define DFLL_OUTPUT_CFG 0x20104#define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30)105#define OUT_MASK 0x3f106#define DFLL_OUTPUT_CFG_SAFE_SHIFT 24107#define DFLL_OUTPUT_CFG_SAFE_MASK \108 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)109#define DFLL_OUTPUT_CFG_MAX_SHIFT 16110#define DFLL_OUTPUT_CFG_MAX_MASK \111 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)112#define DFLL_OUTPUT_CFG_MIN_SHIFT 8113#define DFLL_OUTPUT_CFG_MIN_MASK \114 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)115#define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7)116#define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6)117#define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0118#define DFLL_OUTPUT_CFG_PWM_DIV_MASK \119 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)120 121/* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */122#define DFLL_OUTPUT_FORCE 0x24123#define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6)124#define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0125#define DFLL_OUTPUT_FORCE_VALUE_MASK \126 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)127 128/* DFLL_MONITOR_CTRL: internal monitor data source control */129#define DFLL_MONITOR_CTRL 0x28130#define DFLL_MONITOR_CTRL_FREQ 6131 132/* DFLL_MONITOR_DATA: internal monitor data output */133#define DFLL_MONITOR_DATA 0x2c134#define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16)135#define DFLL_MONITOR_DATA_VAL_SHIFT 0136#define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)137 138/*139 * I2C output control registers - access via dfll_i2c_{readl,writel}140 */141 142/* DFLL_I2C_CFG: I2C controller configuration register */143#define DFLL_I2C_CFG 0x40144#define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20)145#define DFLL_I2C_CFG_HS_CODE_SHIFT 16146#define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)147#define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15)148#define DFLL_I2C_CFG_SIZE_SHIFT 12149#define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)150#define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10)151#define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1152#define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0153 154/* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */155#define DFLL_I2C_VDD_REG_ADDR 0x44156 157/* DFLL_I2C_STS: I2C controller status */158#define DFLL_I2C_STS 0x48159#define DFLL_I2C_STS_I2C_LAST_SHIFT 1160#define DFLL_I2C_STS_I2C_REQ_PENDING 0x1161 162/* DFLL_INTR_STS: DFLL interrupt status register */163#define DFLL_INTR_STS 0x5c164 165/* DFLL_INTR_EN: DFLL interrupt enable register */166#define DFLL_INTR_EN 0x60167#define DFLL_INTR_MIN_MASK 0x1168#define DFLL_INTR_MAX_MASK 0x2169 170/*171 * Integrated I2C controller registers - relative to td->i2c_controller_base172 */173 174/* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */175#define DFLL_I2C_CLK_DIVISOR 0x6c176#define DFLL_I2C_CLK_DIVISOR_MASK 0xffff177#define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16178#define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0179#define DFLL_I2C_CLK_DIVISOR_PREDIV 8180#define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12181 182/*183 * Other constants184 */185 186/* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */187#define MAX_DFLL_VOLTAGES 33188 189/*190 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware191 * integrates the DVCO counter over - used for debug rate monitoring and192 * droop control193 */194#define REF_CLK_CYC_PER_DVCO_SAMPLE 4195 196/*197 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this198 * driver, in Hz199 */200#define REF_CLOCK_RATE 51000000UL201 202#define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))203#define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2))204 205/**206 * enum dfll_ctrl_mode - DFLL hardware operating mode207 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)208 * @DFLL_DISABLED: DFLL not generating an output clock209 * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage210 * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match211 * the requested rate212 *213 * The integer corresponding to the last two states, minus one, is214 * written to the DFLL hardware to change operating modes.215 */216enum dfll_ctrl_mode {217 DFLL_UNINITIALIZED = 0,218 DFLL_DISABLED = 1,219 DFLL_OPEN_LOOP = 2,220 DFLL_CLOSED_LOOP = 3,221};222 223/**224 * enum dfll_tune_range - voltage range that the driver believes it's in225 * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed226 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)227 *228 * Some DFLL tuning parameters may need to change depending on the229 * DVCO's voltage; these states represent the ranges that the driver230 * supports. These are software states; these values are never231 * written into registers.232 */233enum dfll_tune_range {234 DFLL_TUNE_UNINITIALIZED = 0,235 DFLL_TUNE_LOW = 1,236};237 238 239enum tegra_dfll_pmu_if {240 TEGRA_DFLL_PMU_I2C = 0,241 TEGRA_DFLL_PMU_PWM = 1,242};243 244/**245 * struct dfll_rate_req - target DFLL rate request data246 * @rate: target frequency, after the postscaling247 * @dvco_target_rate: target frequency, after the postscaling248 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached249 * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register250 * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register251 */252struct dfll_rate_req {253 unsigned long rate;254 unsigned long dvco_target_rate;255 int lut_index;256 u8 mult_bits;257 u8 scale_bits;258};259 260struct tegra_dfll {261 struct device *dev;262 struct tegra_dfll_soc_data *soc;263 264 void __iomem *base;265 void __iomem *i2c_base;266 void __iomem *i2c_controller_base;267 void __iomem *lut_base;268 269 struct regulator *vdd_reg;270 struct clk *soc_clk;271 struct clk *ref_clk;272 struct clk *i2c_clk;273 struct clk *dfll_clk;274 struct reset_control *dfll_rst;275 struct reset_control *dvco_rst;276 unsigned long ref_rate;277 unsigned long i2c_clk_rate;278 unsigned long dvco_rate_min;279 280 enum dfll_ctrl_mode mode;281 enum dfll_tune_range tune_range;282 struct dentry *debugfs_dir;283 struct clk_hw dfll_clk_hw;284 const char *output_clock_name;285 struct dfll_rate_req last_req;286 unsigned long last_unrounded_rate;287 288 /* Parameters from DT */289 u32 droop_ctrl;290 u32 sample_rate;291 u32 force_mode;292 u32 cf;293 u32 ci;294 u32 cg;295 bool cg_scale;296 297 /* I2C interface parameters */298 u32 i2c_fs_rate;299 u32 i2c_reg;300 u32 i2c_slave_addr;301 302 /* lut array entries are regulator framework selectors or PWM values*/303 unsigned lut[MAX_DFLL_VOLTAGES];304 unsigned long lut_uv[MAX_DFLL_VOLTAGES];305 int lut_size;306 u8 lut_bottom, lut_min, lut_max, lut_safe;307 308 /* PWM interface */309 enum tegra_dfll_pmu_if pmu_if;310 unsigned long pwm_rate;311 struct pinctrl *pwm_pin;312 struct pinctrl_state *pwm_enable_state;313 struct pinctrl_state *pwm_disable_state;314 u32 reg_init_uV;315};316 317#define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)318 319/* mode_name: map numeric DFLL modes to names for friendly console messages */320static const char * const mode_name[] = {321 [DFLL_UNINITIALIZED] = "uninitialized",322 [DFLL_DISABLED] = "disabled",323 [DFLL_OPEN_LOOP] = "open_loop",324 [DFLL_CLOSED_LOOP] = "closed_loop",325};326 327/*328 * Register accessors329 */330 331static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)332{333 return __raw_readl(td->base + offs);334}335 336static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)337{338 WARN_ON(offs >= DFLL_I2C_CFG);339 __raw_writel(val, td->base + offs);340}341 342static inline void dfll_wmb(struct tegra_dfll *td)343{344 dfll_readl(td, DFLL_CTRL);345}346 347/* I2C output control registers - for addresses above DFLL_I2C_CFG */348 349static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)350{351 return __raw_readl(td->i2c_base + offs);352}353 354static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)355{356 __raw_writel(val, td->i2c_base + offs);357}358 359static inline void dfll_i2c_wmb(struct tegra_dfll *td)360{361 dfll_i2c_readl(td, DFLL_I2C_CFG);362}363 364/**365 * dfll_is_running - is the DFLL currently generating a clock?366 * @td: DFLL instance367 *368 * If the DFLL is currently generating an output clock signal, return369 * true; otherwise return false.370 */371static bool dfll_is_running(struct tegra_dfll *td)372{373 return td->mode >= DFLL_OPEN_LOOP;374}375 376/*377 * Runtime PM suspend/resume callbacks378 */379 380/**381 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL382 * @dev: DFLL device *383 *384 * Enable all clocks needed by the DFLL. Assumes that clk_prepare()385 * has already been called on all the clocks.386 *387 * XXX Should also handle context restore when returning from off.388 */389int tegra_dfll_runtime_resume(struct device *dev)390{391 struct tegra_dfll *td = dev_get_drvdata(dev);392 int ret;393 394 ret = clk_enable(td->ref_clk);395 if (ret) {396 dev_err(dev, "could not enable ref clock: %d\n", ret);397 return ret;398 }399 400 ret = clk_enable(td->soc_clk);401 if (ret) {402 dev_err(dev, "could not enable register clock: %d\n", ret);403 clk_disable(td->ref_clk);404 return ret;405 }406 407 ret = clk_enable(td->i2c_clk);408 if (ret) {409 dev_err(dev, "could not enable i2c clock: %d\n", ret);410 clk_disable(td->soc_clk);411 clk_disable(td->ref_clk);412 return ret;413 }414 415 return 0;416}417EXPORT_SYMBOL(tegra_dfll_runtime_resume);418 419/**420 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL421 * @dev: DFLL device *422 *423 * Disable all clocks needed by the DFLL. Assumes that other code424 * will later call clk_unprepare().425 */426int tegra_dfll_runtime_suspend(struct device *dev)427{428 struct tegra_dfll *td = dev_get_drvdata(dev);429 430 clk_disable(td->ref_clk);431 clk_disable(td->soc_clk);432 clk_disable(td->i2c_clk);433 434 return 0;435}436EXPORT_SYMBOL(tegra_dfll_runtime_suspend);437 438/*439 * DFLL tuning operations (per-voltage-range tuning settings)440 */441 442/**443 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage444 * @td: DFLL instance445 *446 * Tune the DFLL oscillator parameters and the CPU clock shaper for447 * the low-voltage range. These settings are valid for any voltage,448 * but may not be optimal.449 */450static void dfll_tune_low(struct tegra_dfll *td)451{452 td->tune_range = DFLL_TUNE_LOW;453 454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);455 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);456 dfll_wmb(td);457 458 if (td->soc->set_clock_trimmers_low)459 td->soc->set_clock_trimmers_low();460}461 462/*463 * Output clock scaler helpers464 */465 466/**467 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate468 * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)469 * @dvco_rate: the DVCO rate470 *471 * Apply the same scaling formula that the DFLL hardware uses to scale472 * the DVCO rate.473 */474static unsigned long dfll_scale_dvco_rate(int scale_bits,475 unsigned long dvco_rate)476{477 return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;478}479 480/*481 * DFLL mode switching482 */483 484/**485 * dfll_set_mode - change the DFLL control mode486 * @td: DFLL instance487 * @mode: DFLL control mode (see enum dfll_ctrl_mode)488 *489 * Change the DFLL's operating mode between disabled, open-loop mode,490 * and closed-loop mode, or vice versa.491 */492static void dfll_set_mode(struct tegra_dfll *td,493 enum dfll_ctrl_mode mode)494{495 td->mode = mode;496 dfll_writel(td, mode - 1, DFLL_CTRL);497 dfll_wmb(td);498}499 500/*501 * DVCO rate control502 */503 504static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)505{506 struct dev_pm_opp *opp;507 unsigned long rate, prev_rate;508 unsigned long uv, min_uv;509 510 min_uv = td->lut_uv[out_min];511 for (rate = 0, prev_rate = 0; ; rate++) {512 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);513 if (IS_ERR(opp))514 break;515 516 uv = dev_pm_opp_get_voltage(opp);517 dev_pm_opp_put(opp);518 519 if (uv && uv > min_uv)520 return prev_rate;521 522 prev_rate = rate;523 }524 525 return prev_rate;526}527 528/*529 * DFLL-to-I2C controller interface530 */531 532/**533 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests534 * @td: DFLL instance535 * @enable: whether to enable or disable the I2C voltage requests536 *537 * Set the master enable control for I2C control value updates. If disabled,538 * then I2C control messages are inhibited, regardless of the DFLL mode.539 */540static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)541{542 u32 val;543 544 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);545 546 if (enable)547 val |= DFLL_OUTPUT_CFG_I2C_ENABLE;548 else549 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE;550 551 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);552 dfll_i2c_wmb(td);553 554 return 0;555}556 557 558/*559 * DFLL-to-PWM controller interface560 */561 562/**563 * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests564 * @td: DFLL instance565 * @enable: whether to enable or disable the PWM voltage requests566 *567 * Set the master enable control for PWM control value updates. If disabled,568 * then the PWM signal is not driven. Also configure the PWM output pad569 * to the appropriate state.570 */571static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)572{573 int ret;574 u32 val, div;575 576 if (enable) {577 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);578 if (ret < 0) {579 dev_err(td->dev, "setting enable state failed\n");580 return -EINVAL;581 }582 val = dfll_readl(td, DFLL_OUTPUT_CFG);583 val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK;584 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);585 val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)586 & DFLL_OUTPUT_CFG_PWM_DIV_MASK;587 dfll_writel(td, val, DFLL_OUTPUT_CFG);588 dfll_wmb(td);589 590 val |= DFLL_OUTPUT_CFG_PWM_ENABLE;591 dfll_writel(td, val, DFLL_OUTPUT_CFG);592 dfll_wmb(td);593 } else {594 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);595 if (ret < 0)596 dev_warn(td->dev, "setting disable state failed\n");597 598 val = dfll_readl(td, DFLL_OUTPUT_CFG);599 val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE;600 dfll_writel(td, val, DFLL_OUTPUT_CFG);601 dfll_wmb(td);602 }603 604 return 0;605}606 607/**608 * dfll_set_force_output_value - set fixed value for force output609 * @td: DFLL instance610 * @out_val: value to force output611 *612 * Set the fixed value for force output, DFLL will output this value when613 * force output is enabled.614 */615static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)616{617 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);618 619 val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK);620 dfll_writel(td, val, DFLL_OUTPUT_FORCE);621 dfll_wmb(td);622 623 return dfll_readl(td, DFLL_OUTPUT_FORCE);624}625 626/**627 * dfll_set_force_output_enabled - enable/disable force output628 * @td: DFLL instance629 * @enable: whether to enable or disable the force output630 *631 * Set the enable control for fouce output with fixed value.632 */633static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)634{635 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);636 637 if (enable)638 val |= DFLL_OUTPUT_FORCE_ENABLE;639 else640 val &= ~DFLL_OUTPUT_FORCE_ENABLE;641 642 dfll_writel(td, val, DFLL_OUTPUT_FORCE);643 dfll_wmb(td);644}645 646/**647 * dfll_force_output - force output a fixed value648 * @td: DFLL instance649 * @out_sel: value to force output650 *651 * Set the fixed value for force output, DFLL will output this value.652 */653static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)654{655 u32 val;656 657 if (out_sel > OUT_MASK)658 return -EINVAL;659 660 val = dfll_set_force_output_value(td, out_sel);661 if ((td->mode < DFLL_CLOSED_LOOP) &&662 !(val & DFLL_OUTPUT_FORCE_ENABLE)) {663 dfll_set_force_output_enabled(td, true);664 }665 666 return 0;667}668 669/**670 * dfll_load_i2c_lut - load the voltage lookup table671 * @td: struct tegra_dfll *672 *673 * Load the voltage-to-PMIC register value lookup table into the DFLL674 * IP block memory. Look-up tables can be loaded at any time.675 */676static void dfll_load_i2c_lut(struct tegra_dfll *td)677{678 int i, lut_index;679 u32 val;680 681 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {682 if (i < td->lut_min)683 lut_index = td->lut_min;684 else if (i > td->lut_max)685 lut_index = td->lut_max;686 else687 lut_index = i;688 689 val = regulator_list_hardware_vsel(td->vdd_reg,690 td->lut[lut_index]);691 __raw_writel(val, td->lut_base + i * 4);692 }693 694 dfll_i2c_wmb(td);695}696 697/**698 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface699 * @td: DFLL instance700 *701 * During DFLL driver initialization, program the DFLL-I2C interface702 * with the PMU slave address, vdd register offset, and transfer mode.703 * This data is used by the DFLL to automatically construct I2C704 * voltage-set commands, which are then passed to the DFLL's internal705 * I2C controller.706 */707static void dfll_init_i2c_if(struct tegra_dfll *td)708{709 u32 val;710 711 if (td->i2c_slave_addr > 0x7f) {712 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;713 val |= DFLL_I2C_CFG_SLAVE_ADDR_10;714 } else {715 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;716 }717 val |= DFLL_I2C_CFG_SIZE_MASK;718 val |= DFLL_I2C_CFG_ARB_ENABLE;719 dfll_i2c_writel(td, val, DFLL_I2C_CFG);720 721 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);722 723 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);724 BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK));725 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT;726 727 /* default hs divisor just in case */728 val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT;729 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);730 dfll_i2c_wmb(td);731}732 733/**734 * dfll_init_out_if - prepare DFLL-to-PMIC interface735 * @td: DFLL instance736 *737 * During DFLL driver initialization or resume from context loss,738 * disable the I2C command output to the PMIC, set safe voltage and739 * output limits, and disable and clear limit interrupts.740 */741static void dfll_init_out_if(struct tegra_dfll *td)742{743 u32 val;744 745 td->lut_min = td->lut_bottom;746 td->lut_max = td->lut_size - 1;747 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);748 749 /* clear DFLL_OUTPUT_CFG before setting new value */750 dfll_writel(td, 0, DFLL_OUTPUT_CFG);751 dfll_wmb(td);752 753 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |754 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |755 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);756 dfll_writel(td, val, DFLL_OUTPUT_CFG);757 dfll_wmb(td);758 759 dfll_writel(td, 0, DFLL_OUTPUT_FORCE);760 dfll_i2c_writel(td, 0, DFLL_INTR_EN);761 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,762 DFLL_INTR_STS);763 764 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {765 u32 vinit = td->reg_init_uV;766 int vstep = td->soc->alignment.step_uv;767 unsigned long vmin = td->lut_uv[0];768 769 /* set initial voltage */770 if ((vinit >= vmin) && vstep) {771 unsigned int vsel;772 773 vsel = DIV_ROUND_UP((vinit - vmin), vstep);774 dfll_force_output(td, vsel);775 }776 } else {777 dfll_load_i2c_lut(td);778 dfll_init_i2c_if(td);779 }780}781 782/*783 * Set/get the DFLL's targeted output clock rate784 */785 786/**787 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate788 * @td: DFLL instance789 * @rate: clock rate790 *791 * Determines the index of a I2C LUT entry for a voltage that approximately792 * produces the given DFLL clock rate. This is used when forcing a value793 * to the integrator during rate changes. Returns -ENOENT if a suitable794 * LUT index is not found.795 */796static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)797{798 struct dev_pm_opp *opp;799 int i, align_step;800 801 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);802 if (IS_ERR(opp))803 return PTR_ERR(opp);804 805 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;806 dev_pm_opp_put(opp);807 808 for (i = td->lut_bottom; i < td->lut_size; i++) {809 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)810 return i;811 }812 813 return -ENOENT;814}815 816/**817 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate818 * @td: DFLL instance819 * @req: DFLL-rate-request structure820 * @rate: the desired DFLL rate821 *822 * Populate the DFLL-rate-request record @req fields with the scale_bits823 * and mult_bits fields, based on the target input rate. Returns 0 upon824 * success, or -EINVAL if the requested rate in req->rate is too high825 * or low for the DFLL to generate.826 */827static int dfll_calculate_rate_request(struct tegra_dfll *td,828 struct dfll_rate_req *req,829 unsigned long rate)830{831 u32 val;832 833 /*834 * If requested rate is below the minimum DVCO rate, active the scaler.835 * In the future the DVCO minimum voltage should be selected based on836 * chip temperature and the actual minimum rate should be calibrated837 * at runtime.838 */839 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1;840 if (rate < td->dvco_rate_min) {841 int scale;842 843 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,844 td->dvco_rate_min / 1000);845 if (!scale) {846 dev_err(td->dev, "%s: Rate %lu is too low\n",847 __func__, rate);848 return -EINVAL;849 }850 req->scale_bits = scale - 1;851 rate = td->dvco_rate_min;852 }853 854 /* Convert requested rate into frequency request and scale settings */855 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);856 if (val > FREQ_MAX) {857 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",858 __func__, rate);859 return -EINVAL;860 }861 req->mult_bits = val;862 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);863 req->rate = dfll_scale_dvco_rate(req->scale_bits,864 req->dvco_target_rate);865 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);866 if (req->lut_index < 0)867 return req->lut_index;868 869 return 0;870}871 872/**873 * dfll_set_frequency_request - start the frequency change operation874 * @td: DFLL instance875 * @req: rate request structure876 *877 * Tell the DFLL to try to change its output frequency to the878 * frequency represented by @req. DFLL must be in closed-loop mode.879 */880static void dfll_set_frequency_request(struct tegra_dfll *td,881 struct dfll_rate_req *req)882{883 u32 val = 0;884 int force_val;885 int coef = 128; /* FIXME: td->cg_scale? */;886 887 force_val = (req->lut_index - td->lut_safe) * coef / td->cg;888 force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);889 890 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT;891 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT;892 val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) &893 DFLL_FREQ_REQ_FORCE_MASK;894 val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE;895 896 dfll_writel(td, val, DFLL_FREQ_REQ);897 dfll_wmb(td);898}899 900/**901 * dfll_request_rate - set the next rate for the DFLL to tune to902 * @td: DFLL instance903 * @rate: clock rate to target904 *905 * Convert the requested clock rate @rate into the DFLL control logic906 * settings. In closed-loop mode, update new settings immediately to907 * adjust DFLL output rate accordingly. Otherwise, just save them908 * until the next switch to closed loop. Returns 0 upon success,909 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL910 * if @rate is outside the DFLL's tunable range.911 */912static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)913{914 int ret;915 struct dfll_rate_req req;916 917 if (td->mode == DFLL_UNINITIALIZED) {918 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",919 __func__, mode_name[td->mode]);920 return -EPERM;921 }922 923 ret = dfll_calculate_rate_request(td, &req, rate);924 if (ret)925 return ret;926 927 td->last_unrounded_rate = rate;928 td->last_req = req;929 930 if (td->mode == DFLL_CLOSED_LOOP)931 dfll_set_frequency_request(td, &td->last_req);932 933 return 0;934}935 936/*937 * DFLL enable/disable & open-loop <-> closed-loop transitions938 */939 940/**941 * dfll_disable - switch from open-loop mode to disabled mode942 * @td: DFLL instance943 *944 * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success945 * or -EPERM if the DFLL is not currently in open-loop mode.946 */947static int dfll_disable(struct tegra_dfll *td)948{949 if (td->mode != DFLL_OPEN_LOOP) {950 dev_err(td->dev, "cannot disable DFLL in %s mode\n",951 mode_name[td->mode]);952 return -EINVAL;953 }954 955 dfll_set_mode(td, DFLL_DISABLED);956 pm_runtime_put_sync(td->dev);957 958 return 0;959}960 961/**962 * dfll_enable - switch a disabled DFLL to open-loop mode963 * @td: DFLL instance964 *965 * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success966 * or -EPERM if the DFLL is not currently disabled.967 */968static int dfll_enable(struct tegra_dfll *td)969{970 if (td->mode != DFLL_DISABLED) {971 dev_err(td->dev, "cannot enable DFLL in %s mode\n",972 mode_name[td->mode]);973 return -EPERM;974 }975 976 pm_runtime_get_sync(td->dev);977 dfll_set_mode(td, DFLL_OPEN_LOOP);978 979 return 0;980}981 982/**983 * dfll_set_open_loop_config - prepare to switch to open-loop mode984 * @td: DFLL instance985 *986 * Prepare to switch the DFLL to open-loop mode. This switches the987 * DFLL to the low-voltage tuning range, ensures that I2C output988 * forcing is disabled, and disables the output clock rate scaler.989 * The DFLL's low-voltage tuning range parameters must be990 * characterized to keep the downstream device stable at any DVCO991 * input voltage. No return value.992 */993static void dfll_set_open_loop_config(struct tegra_dfll *td)994{995 u32 val;996 997 /* always tune low (safe) in open loop */998 if (td->tune_range != DFLL_TUNE_LOW)999 dfll_tune_low(td);1000 1001 val = dfll_readl(td, DFLL_FREQ_REQ);1002 val |= DFLL_FREQ_REQ_SCALE_MASK;1003 val &= ~DFLL_FREQ_REQ_FORCE_ENABLE;1004 dfll_writel(td, val, DFLL_FREQ_REQ);1005 dfll_wmb(td);1006}1007 1008/**1009 * dfll_lock - switch from open-loop to closed-loop mode1010 * @td: DFLL instance1011 *1012 * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,1013 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the1014 * DFLL is not currently in open-loop mode.1015 */1016static int dfll_lock(struct tegra_dfll *td)1017{1018 struct dfll_rate_req *req = &td->last_req;1019 1020 switch (td->mode) {1021 case DFLL_CLOSED_LOOP:1022 return 0;1023 1024 case DFLL_OPEN_LOOP:1025 if (req->rate == 0) {1026 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",1027 __func__);1028 return -EINVAL;1029 }1030 1031 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)1032 dfll_pwm_set_output_enabled(td, true);1033 else1034 dfll_i2c_set_output_enabled(td, true);1035 1036 dfll_set_mode(td, DFLL_CLOSED_LOOP);1037 dfll_set_frequency_request(td, req);1038 dfll_set_force_output_enabled(td, false);1039 return 0;1040 1041 default:1042 BUG_ON(td->mode > DFLL_CLOSED_LOOP);1043 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",1044 __func__, mode_name[td->mode]);1045 return -EPERM;1046 }1047}1048 1049/**1050 * dfll_unlock - switch from closed-loop to open-loop mode1051 * @td: DFLL instance1052 *1053 * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,1054 * or -EPERM if the DFLL is not currently in open-loop mode.1055 */1056static int dfll_unlock(struct tegra_dfll *td)1057{1058 switch (td->mode) {1059 case DFLL_CLOSED_LOOP:1060 dfll_set_open_loop_config(td);1061 dfll_set_mode(td, DFLL_OPEN_LOOP);1062 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)1063 dfll_pwm_set_output_enabled(td, false);1064 else1065 dfll_i2c_set_output_enabled(td, false);1066 return 0;1067 1068 case DFLL_OPEN_LOOP:1069 return 0;1070 1071 default:1072 BUG_ON(td->mode > DFLL_CLOSED_LOOP);1073 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",1074 __func__, mode_name[td->mode]);1075 return -EPERM;1076 }1077}1078 1079/*1080 * Clock framework integration1081 *1082 * When the DFLL is being controlled by the CCF, always enter closed loop1083 * mode when the clk is enabled. This requires that a DFLL rate request1084 * has been set beforehand, which implies that a clk_set_rate() call is1085 * always required before a clk_enable().1086 */1087 1088static int dfll_clk_is_enabled(struct clk_hw *hw)1089{1090 struct tegra_dfll *td = clk_hw_to_dfll(hw);1091 1092 return dfll_is_running(td);1093}1094 1095static int dfll_clk_enable(struct clk_hw *hw)1096{1097 struct tegra_dfll *td = clk_hw_to_dfll(hw);1098 int ret;1099 1100 ret = dfll_enable(td);1101 if (ret)1102 return ret;1103 1104 ret = dfll_lock(td);1105 if (ret)1106 dfll_disable(td);1107 1108 return ret;1109}1110 1111static void dfll_clk_disable(struct clk_hw *hw)1112{1113 struct tegra_dfll *td = clk_hw_to_dfll(hw);1114 int ret;1115 1116 ret = dfll_unlock(td);1117 if (!ret)1118 dfll_disable(td);1119}1120 1121static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,1122 unsigned long parent_rate)1123{1124 struct tegra_dfll *td = clk_hw_to_dfll(hw);1125 1126 return td->last_unrounded_rate;1127}1128 1129/* Must use determine_rate since it allows for rates exceeding 2^31-1 */1130static int dfll_clk_determine_rate(struct clk_hw *hw,1131 struct clk_rate_request *clk_req)1132{1133 struct tegra_dfll *td = clk_hw_to_dfll(hw);1134 struct dfll_rate_req req;1135 int ret;1136 1137 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);1138 if (ret)1139 return ret;1140 1141 /*1142 * Don't set the rounded rate, since it doesn't really matter as1143 * the output rate will be voltage controlled anyway, and cpufreq1144 * freaks out if any rounding happens.1145 */1146 1147 return 0;1148}1149 1150static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,1151 unsigned long parent_rate)1152{1153 struct tegra_dfll *td = clk_hw_to_dfll(hw);1154 1155 return dfll_request_rate(td, rate);1156}1157 1158static const struct clk_ops dfll_clk_ops = {1159 .is_enabled = dfll_clk_is_enabled,1160 .enable = dfll_clk_enable,1161 .disable = dfll_clk_disable,1162 .recalc_rate = dfll_clk_recalc_rate,1163 .determine_rate = dfll_clk_determine_rate,1164 .set_rate = dfll_clk_set_rate,1165};1166 1167static struct clk_init_data dfll_clk_init_data = {1168 .ops = &dfll_clk_ops,1169 .num_parents = 0,1170};1171 1172/**1173 * dfll_register_clk - register the DFLL output clock with the clock framework1174 * @td: DFLL instance1175 *1176 * Register the DFLL's output clock with the Linux clock framework and register1177 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL1178 * or -ENOMEM upon failure.1179 */1180static int dfll_register_clk(struct tegra_dfll *td)1181{1182 int ret;1183 1184 dfll_clk_init_data.name = td->output_clock_name;1185 td->dfll_clk_hw.init = &dfll_clk_init_data;1186 1187 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);1188 if (IS_ERR(td->dfll_clk)) {1189 dev_err(td->dev, "DFLL clock registration error\n");1190 return -EINVAL;1191 }1192 1193 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,1194 td->dfll_clk);1195 if (ret) {1196 dev_err(td->dev, "of_clk_add_provider() failed\n");1197 1198 clk_unregister(td->dfll_clk);1199 return ret;1200 }1201 1202 return 0;1203}1204 1205/**1206 * dfll_unregister_clk - unregister the DFLL output clock1207 * @td: DFLL instance1208 *1209 * Unregister the DFLL's output clock from the Linux clock framework1210 * and from clkdev. No return value.1211 */1212static void dfll_unregister_clk(struct tegra_dfll *td)1213{1214 of_clk_del_provider(td->dev->of_node);1215 clk_unregister(td->dfll_clk);1216 td->dfll_clk = NULL;1217}1218 1219/*1220 * Debugfs interface1221 */1222 1223#ifdef CONFIG_DEBUG_FS1224/*1225 * Monitor control1226 */1227 1228/**1229 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq1230 * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield1231 * @ref_rate: DFLL reference clock rate1232 *1233 * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles1234 * per second. Returns the converted value.1235 */1236static u64 dfll_calc_monitored_rate(u32 monitor_data,1237 unsigned long ref_rate)1238{1239 return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);1240}1241 1242/**1243 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor1244 * @td: DFLL instance1245 *1246 * If the DFLL is enabled, return the last rate reported by the DFLL's1247 * internal monitoring hardware. This works in both open-loop and1248 * closed-loop mode, and takes the output scaler setting into account.1249 * Assumes that the monitor was programmed to monitor frequency before1250 * the sample period started. If the driver believes that the DFLL is1251 * currently uninitialized or disabled, it will return 0, since1252 * otherwise the DFLL monitor data register will return the last1253 * measured rate from when the DFLL was active.1254 */1255static u64 dfll_read_monitor_rate(struct tegra_dfll *td)1256{1257 u32 v, s;1258 u64 pre_scaler_rate, post_scaler_rate;1259 1260 if (!dfll_is_running(td))1261 return 0;1262 1263 v = dfll_readl(td, DFLL_MONITOR_DATA);1264 v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;1265 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);1266 1267 s = dfll_readl(td, DFLL_FREQ_REQ);1268 s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;1269 post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);1270 1271 return post_scaler_rate;1272}1273 1274static int attr_enable_get(void *data, u64 *val)1275{1276 struct tegra_dfll *td = data;1277 1278 *val = dfll_is_running(td);1279 1280 return 0;1281}1282static int attr_enable_set(void *data, u64 val)1283{1284 struct tegra_dfll *td = data;1285 1286 return val ? dfll_enable(td) : dfll_disable(td);1287}1288DEFINE_DEBUGFS_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,1289 "%llu\n");1290 1291static int attr_lock_get(void *data, u64 *val)1292{1293 struct tegra_dfll *td = data;1294 1295 *val = (td->mode == DFLL_CLOSED_LOOP);1296 1297 return 0;1298}1299static int attr_lock_set(void *data, u64 val)1300{1301 struct tegra_dfll *td = data;1302 1303 return val ? dfll_lock(td) : dfll_unlock(td);1304}1305DEFINE_DEBUGFS_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, "%llu\n");1306 1307static int attr_rate_get(void *data, u64 *val)1308{1309 struct tegra_dfll *td = data;1310 1311 *val = dfll_read_monitor_rate(td);1312 1313 return 0;1314}1315 1316static int attr_rate_set(void *data, u64 val)1317{1318 struct tegra_dfll *td = data;1319 1320 return dfll_request_rate(td, val);1321}1322DEFINE_DEBUGFS_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");1323 1324static int attr_registers_show(struct seq_file *s, void *data)1325{1326 u32 val, offs;1327 struct tegra_dfll *td = s->private;1328 1329 seq_puts(s, "CONTROL REGISTERS:\n");1330 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) {1331 if (offs == DFLL_OUTPUT_CFG)1332 val = dfll_i2c_readl(td, offs);1333 else1334 val = dfll_readl(td, offs);1335 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val);1336 }1337 1338 seq_puts(s, "\nI2C and INTR REGISTERS:\n");1339 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4)1340 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,1341 dfll_i2c_readl(td, offs));1342 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4)1343 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,1344 dfll_i2c_readl(td, offs));1345 1346 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {1347 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");1348 offs = DFLL_I2C_CLK_DIVISOR;1349 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,1350 __raw_readl(td->i2c_controller_base + offs));1351 1352 seq_puts(s, "\nLUT:\n");1353 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)1354 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,1355 __raw_readl(td->lut_base + offs));1356 }1357 1358 return 0;1359}1360 1361DEFINE_SHOW_ATTRIBUTE(attr_registers);1362 1363static void dfll_debug_init(struct tegra_dfll *td)1364{1365 struct dentry *root;1366 1367 if (!td || (td->mode == DFLL_UNINITIALIZED))1368 return;1369 1370 root = debugfs_create_dir("tegra_dfll_fcpu", NULL);1371 td->debugfs_dir = root;1372 1373 debugfs_create_file_unsafe("enable", 0644, root, td,1374 &enable_fops);1375 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);1376 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);1377 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);1378}1379 1380#else1381static inline void dfll_debug_init(struct tegra_dfll *td) { }1382#endif /* CONFIG_DEBUG_FS */1383 1384/*1385 * DFLL initialization1386 */1387 1388/**1389 * dfll_set_default_params - program non-output related DFLL parameters1390 * @td: DFLL instance1391 *1392 * During DFLL driver initialization or resume from context loss,1393 * program parameters for the closed loop integrator, DVCO tuning,1394 * voltage droop control and monitor control.1395 */1396static void dfll_set_default_params(struct tegra_dfll *td)1397{1398 u32 val;1399 1400 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);1401 BUG_ON(val > DFLL_CONFIG_DIV_MASK);1402 dfll_writel(td, val, DFLL_CONFIG);1403 1404 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |1405 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |1406 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |1407 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |1408 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);1409 dfll_writel(td, val, DFLL_PARAMS);1410 1411 dfll_tune_low(td);1412 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);1413 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);1414}1415 1416/**1417 * dfll_init_clks - clk_get() the DFLL source clocks1418 * @td: DFLL instance1419 *1420 * Call clk_get() on the DFLL source clocks and save the pointers for later1421 * use. Returns 0 upon success or error (see devm_clk_get) if one or more1422 * of the clocks couldn't be looked up.1423 */1424static int dfll_init_clks(struct tegra_dfll *td)1425{1426 td->ref_clk = devm_clk_get(td->dev, "ref");1427 if (IS_ERR(td->ref_clk)) {1428 dev_err(td->dev, "missing ref clock\n");1429 return PTR_ERR(td->ref_clk);1430 }1431 1432 td->soc_clk = devm_clk_get(td->dev, "soc");1433 if (IS_ERR(td->soc_clk)) {1434 dev_err(td->dev, "missing soc clock\n");1435 return PTR_ERR(td->soc_clk);1436 }1437 1438 td->i2c_clk = devm_clk_get(td->dev, "i2c");1439 if (IS_ERR(td->i2c_clk)) {1440 dev_err(td->dev, "missing i2c clock\n");1441 return PTR_ERR(td->i2c_clk);1442 }1443 td->i2c_clk_rate = clk_get_rate(td->i2c_clk);1444 1445 return 0;1446}1447 1448/**1449 * dfll_init - Prepare the DFLL IP block for use1450 * @td: DFLL instance1451 *1452 * Do everything necessary to prepare the DFLL IP block for use. The1453 * DFLL will be left in DISABLED state. Called by dfll_probe().1454 * Returns 0 upon success, or passes along the error from whatever1455 * function returned it.1456 */1457static int dfll_init(struct tegra_dfll *td)1458{1459 int ret;1460 1461 td->ref_rate = clk_get_rate(td->ref_clk);1462 if (td->ref_rate != REF_CLOCK_RATE) {1463 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",1464 td->ref_rate, REF_CLOCK_RATE);1465 return -EINVAL;1466 }1467 1468 reset_control_deassert(td->dfll_rst);1469 reset_control_deassert(td->dvco_rst);1470 1471 ret = clk_prepare(td->ref_clk);1472 if (ret) {1473 dev_err(td->dev, "failed to prepare ref_clk\n");1474 return ret;1475 }1476 1477 ret = clk_prepare(td->soc_clk);1478 if (ret) {1479 dev_err(td->dev, "failed to prepare soc_clk\n");1480 goto di_err1;1481 }1482 1483 ret = clk_prepare(td->i2c_clk);1484 if (ret) {1485 dev_err(td->dev, "failed to prepare i2c_clk\n");1486 goto di_err2;1487 }1488 1489 td->last_unrounded_rate = 0;1490 1491 pm_runtime_enable(td->dev);1492 pm_runtime_get_sync(td->dev);1493 1494 dfll_set_mode(td, DFLL_DISABLED);1495 dfll_set_default_params(td);1496 1497 if (td->soc->init_clock_trimmers)1498 td->soc->init_clock_trimmers();1499 1500 dfll_set_open_loop_config(td);1501 1502 dfll_init_out_if(td);1503 1504 pm_runtime_put_sync(td->dev);1505 1506 return 0;1507 1508di_err2:1509 clk_unprepare(td->soc_clk);1510di_err1:1511 clk_unprepare(td->ref_clk);1512 1513 reset_control_assert(td->dvco_rst);1514 reset_control_assert(td->dfll_rst);1515 1516 return ret;1517}1518 1519/**1520 * tegra_dfll_suspend - check DFLL is disabled1521 * @dev: DFLL instance1522 *1523 * DFLL clock should be disabled by the CPUFreq driver. So, make1524 * sure it is disabled and disable all clocks needed by the DFLL.1525 */1526int tegra_dfll_suspend(struct device *dev)1527{1528 struct tegra_dfll *td = dev_get_drvdata(dev);1529 1530 if (dfll_is_running(td)) {1531 dev_err(td->dev, "DFLL still enabled while suspending\n");1532 return -EBUSY;1533 }1534 1535 reset_control_assert(td->dvco_rst);1536 reset_control_assert(td->dfll_rst);1537 1538 return 0;1539}1540EXPORT_SYMBOL(tegra_dfll_suspend);1541 1542/**1543 * tegra_dfll_resume - reinitialize DFLL on resume1544 * @dev: DFLL instance1545 *1546 * DFLL is disabled and reset during suspend and resume.1547 * So, reinitialize the DFLL IP block back for use.1548 * DFLL clock is enabled later in closed loop mode by CPUFreq1549 * driver before switching its clock source to DFLL output.1550 */1551int tegra_dfll_resume(struct device *dev)1552{1553 struct tegra_dfll *td = dev_get_drvdata(dev);1554 1555 reset_control_deassert(td->dfll_rst);1556 reset_control_deassert(td->dvco_rst);1557 1558 pm_runtime_get_sync(td->dev);1559 1560 dfll_set_mode(td, DFLL_DISABLED);1561 dfll_set_default_params(td);1562 1563 if (td->soc->init_clock_trimmers)1564 td->soc->init_clock_trimmers();1565 1566 dfll_set_open_loop_config(td);1567 1568 dfll_init_out_if(td);1569 1570 pm_runtime_put_sync(td->dev);1571 1572 return 0;1573}1574EXPORT_SYMBOL(tegra_dfll_resume);1575 1576/*1577 * DT data fetch1578 */1579 1580/*1581 * Find a PMIC voltage register-to-voltage mapping for the given voltage.1582 * An exact voltage match is required.1583 */1584static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)1585{1586 int i, n_voltages, reg_uV,reg_volt_id, align_step;1587 1588 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))1589 return -EINVAL;1590 1591 align_step = uV / td->soc->alignment.step_uv;1592 n_voltages = regulator_count_voltages(td->vdd_reg);1593 for (i = 0; i < n_voltages; i++) {1594 reg_uV = regulator_list_voltage(td->vdd_reg, i);1595 if (reg_uV < 0)1596 break;1597 1598 reg_volt_id = reg_uV / td->soc->alignment.step_uv;1599 1600 if (align_step == reg_volt_id)1601 return i;1602 }1603 1604 dev_err(td->dev, "no voltage map entry for %d uV\n", uV);1605 return -EINVAL;1606}1607 1608/*1609 * Find a PMIC voltage register-to-voltage mapping for the given voltage,1610 * rounding up to the closest supported voltage.1611 * */1612static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)1613{1614 int i, n_voltages, reg_uV, reg_volt_id, align_step;1615 1616 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))1617 return -EINVAL;1618 1619 align_step = uV / td->soc->alignment.step_uv;1620 n_voltages = regulator_count_voltages(td->vdd_reg);1621 for (i = 0; i < n_voltages; i++) {1622 reg_uV = regulator_list_voltage(td->vdd_reg, i);1623 if (reg_uV < 0)1624 break;1625 1626 reg_volt_id = reg_uV / td->soc->alignment.step_uv;1627 1628 if (align_step <= reg_volt_id)1629 return i;1630 }1631 1632 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);1633 return -EINVAL;1634}1635 1636/*1637 * dfll_build_pwm_lut - build the PWM regulator lookup table1638 * @td: DFLL instance1639 * @v_max: Vmax from OPP table1640 *1641 * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.1642 * In this case closed loop output is controlling duty cycle directly. The s/w1643 * look-up that maps PWM duty cycle to voltage is still built by this function.1644 */1645static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)1646{1647 int i;1648 unsigned long rate, reg_volt;1649 u8 lut_bottom = MAX_DFLL_VOLTAGES;1650 int v_min = td->soc->cvb->min_millivolts * 1000;1651 1652 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {1653 reg_volt = td->lut_uv[i];1654 1655 /* since opp voltage is exact mv */1656 reg_volt = (reg_volt / 1000) * 1000;1657 if (reg_volt > v_max)1658 break;1659 1660 td->lut[i] = i;1661 if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))1662 lut_bottom = i;1663 }1664 1665 /* determine voltage boundaries */1666 td->lut_size = i;1667 if ((lut_bottom == MAX_DFLL_VOLTAGES) ||1668 (lut_bottom + 1 >= td->lut_size)) {1669 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",1670 td->soc->cvb->min_millivolts);1671 return -EINVAL;1672 }1673 td->lut_bottom = lut_bottom;1674 1675 /* determine rate boundaries */1676 rate = get_dvco_rate_below(td, td->lut_bottom);1677 if (!rate) {1678 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",1679 td->soc->cvb->min_millivolts);1680 return -EINVAL;1681 }1682 td->dvco_rate_min = rate;1683 1684 return 0;1685}1686 1687/**1688 * dfll_build_i2c_lut - build the I2C voltage register lookup table1689 * @td: DFLL instance1690 * @v_max: Vmax from OPP table1691 *1692 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with1693 * PMIC voltage register values that span the entire DFLL operating range.1694 * This function builds the look-up table based on the OPP table provided by1695 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC1696 * register-to-voltage mapping queried from the regulator framework.1697 *1698 * On success, fills in td->lut and returns 0, or -err on failure.1699 */1700static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)1701{1702 unsigned long rate, v, v_opp;1703 int ret = -EINVAL;1704 int j, selector, lut;1705 1706 v = td->soc->cvb->min_millivolts * 1000;1707 lut = find_vdd_map_entry_exact(td, v);1708 if (lut < 0)1709 goto out;1710 td->lut[0] = lut;1711 td->lut_bottom = 0;1712 1713 for (j = 1, rate = 0; ; rate++) {1714 struct dev_pm_opp *opp;1715 1716 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);1717 if (IS_ERR(opp))1718 break;1719 v_opp = dev_pm_opp_get_voltage(opp);1720 1721 if (v_opp <= td->soc->cvb->min_millivolts * 1000)1722 td->dvco_rate_min = dev_pm_opp_get_freq(opp);1723 1724 dev_pm_opp_put(opp);1725 1726 for (;;) {1727 v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));1728 if (v >= v_opp)1729 break;1730 1731 selector = find_vdd_map_entry_min(td, v);1732 if (selector < 0)1733 goto out;1734 if (selector != td->lut[j - 1])1735 td->lut[j++] = selector;1736 }1737 1738 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;1739 selector = find_vdd_map_entry_exact(td, v);1740 if (selector < 0)1741 goto out;1742 if (selector != td->lut[j - 1])1743 td->lut[j++] = selector;1744 1745 if (v >= v_max)1746 break;1747 }1748 td->lut_size = j;1749 1750 if (!td->dvco_rate_min)1751 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",1752 td->soc->cvb->min_millivolts);1753 else {1754 ret = 0;1755 for (j = 0; j < td->lut_size; j++)1756 td->lut_uv[j] =1757 regulator_list_voltage(td->vdd_reg,1758 td->lut[j]);1759 }1760 1761out:1762 return ret;1763}1764 1765static int dfll_build_lut(struct tegra_dfll *td)1766{1767 unsigned long rate, v_max;1768 struct dev_pm_opp *opp;1769 1770 rate = ULONG_MAX;1771 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);1772 if (IS_ERR(opp)) {1773 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");1774 return -EINVAL;1775 }1776 v_max = dev_pm_opp_get_voltage(opp);1777 dev_pm_opp_put(opp);1778 1779 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)1780 return dfll_build_pwm_lut(td, v_max);1781 else1782 return dfll_build_i2c_lut(td, v_max);1783}1784 1785/**1786 * read_dt_param - helper function for reading required parameters from the DT1787 * @td: DFLL instance1788 * @param: DT property name1789 * @dest: output pointer for the value read1790 *1791 * Read a required numeric parameter from the DFLL device node, or complain1792 * if the property doesn't exist. Returns a boolean indicating success for1793 * easy chaining of multiple calls to this function.1794 */1795static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)1796{1797 int err = of_property_read_u32(td->dev->of_node, param, dest);1798 1799 if (err < 0) {1800 dev_err(td->dev, "failed to read DT parameter %s: %d\n",1801 param, err);1802 return false;1803 }1804 1805 return true;1806}1807 1808/**1809 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem1810 * @td: DFLL instance1811 *1812 * Read all the parameters required for operation in I2C mode. The parameters1813 * can originate from the device tree or the regulator subsystem.1814 * Returns 0 on success or -err on failure.1815 */1816static int dfll_fetch_i2c_params(struct tegra_dfll *td)1817{1818 struct regmap *regmap;1819 struct device *i2c_dev;1820 struct i2c_client *i2c_client;1821 int vsel_reg, vsel_mask;1822 int ret;1823 1824 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))1825 return -EINVAL;1826 1827 regmap = regulator_get_regmap(td->vdd_reg);1828 i2c_dev = regmap_get_device(regmap);1829 i2c_client = to_i2c_client(i2c_dev);1830 1831 td->i2c_slave_addr = i2c_client->addr;1832 1833 ret = regulator_get_hardware_vsel_register(td->vdd_reg,1834 &vsel_reg,1835 &vsel_mask);1836 if (ret < 0) {1837 dev_err(td->dev,1838 "regulator unsuitable for DFLL I2C operation\n");1839 return -EINVAL;1840 }1841 td->i2c_reg = vsel_reg;1842 1843 return 0;1844}1845 1846static int dfll_fetch_pwm_params(struct tegra_dfll *td)1847{1848 int ret, i;1849 u32 pwm_period;1850 1851 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {1852 dev_err(td->dev,1853 "Missing step or alignment info for PWM regulator");1854 return -EINVAL;1855 }1856 for (i = 0; i < MAX_DFLL_VOLTAGES; i++)1857 td->lut_uv[i] = td->soc->alignment.offset_uv +1858 i * td->soc->alignment.step_uv;1859 1860 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",1861 &td->reg_init_uV);1862 if (!ret) {1863 dev_err(td->dev, "couldn't get initialized voltage\n");1864 return -EINVAL;1865 }1866 1867 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);1868 if (!ret) {1869 dev_err(td->dev, "couldn't get PWM period\n");1870 return -EINVAL;1871 }1872 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);1873 1874 td->pwm_pin = devm_pinctrl_get(td->dev);1875 if (IS_ERR(td->pwm_pin)) {1876 dev_err(td->dev, "DT: missing pinctrl device\n");1877 return PTR_ERR(td->pwm_pin);1878 }1879 1880 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,1881 "dvfs_pwm_enable");1882 if (IS_ERR(td->pwm_enable_state)) {1883 dev_err(td->dev, "DT: missing pwm enabled state\n");1884 return PTR_ERR(td->pwm_enable_state);1885 }1886 1887 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,1888 "dvfs_pwm_disable");1889 if (IS_ERR(td->pwm_disable_state)) {1890 dev_err(td->dev, "DT: missing pwm disabled state\n");1891 return PTR_ERR(td->pwm_disable_state);1892 }1893 1894 return 0;1895}1896 1897/**1898 * dfll_fetch_common_params - read DFLL parameters from the device tree1899 * @td: DFLL instance1900 *1901 * Read all the DT parameters that are common to both I2C and PWM operation.1902 * Returns 0 on success or -EINVAL on any failure.1903 */1904static int dfll_fetch_common_params(struct tegra_dfll *td)1905{1906 bool ok = true;1907 1908 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);1909 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);1910 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);1911 ok &= read_dt_param(td, "nvidia,cf", &td->cf);1912 ok &= read_dt_param(td, "nvidia,ci", &td->ci);1913 ok &= read_dt_param(td, "nvidia,cg", &td->cg);1914 td->cg_scale = of_property_read_bool(td->dev->of_node,1915 "nvidia,cg-scale");1916 1917 if (of_property_read_string(td->dev->of_node, "clock-output-names",1918 &td->output_clock_name)) {1919 dev_err(td->dev, "missing clock-output-names property\n");1920 ok = false;1921 }1922 1923 return ok ? 0 : -EINVAL;1924}1925 1926/*1927 * API exported to per-SoC platform drivers1928 */1929 1930/**1931 * tegra_dfll_register - probe a Tegra DFLL device1932 * @pdev: DFLL platform_device *1933 * @soc: Per-SoC integration and characterization data for this DFLL instance1934 *1935 * Probe and initialize a DFLL device instance. Intended to be called1936 * by a SoC-specific shim driver that passes in per-SoC integration1937 * and configuration data via @soc. Returns 0 on success or -err on failure.1938 */1939int tegra_dfll_register(struct platform_device *pdev,1940 struct tegra_dfll_soc_data *soc)1941{1942 struct resource *mem;1943 struct tegra_dfll *td;1944 int ret;1945 1946 if (!soc) {1947 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");1948 return -EINVAL;1949 }1950 1951 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);1952 if (!td)1953 return -ENOMEM;1954 td->dev = &pdev->dev;1955 platform_set_drvdata(pdev, td);1956 1957 td->soc = soc;1958 1959 td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll");1960 if (IS_ERR(td->dfll_rst)) {1961 dev_err(td->dev, "couldn't get dfll reset\n");1962 return PTR_ERR(td->dfll_rst);1963 }1964 1965 td->dvco_rst = devm_reset_control_get(td->dev, "dvco");1966 if (IS_ERR(td->dvco_rst)) {1967 dev_err(td->dev, "couldn't get dvco reset\n");1968 return PTR_ERR(td->dvco_rst);1969 }1970 1971 ret = dfll_fetch_common_params(td);1972 if (ret) {1973 dev_err(td->dev, "couldn't parse device tree parameters\n");1974 return ret;1975 }1976 1977 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {1978 td->pmu_if = TEGRA_DFLL_PMU_PWM;1979 ret = dfll_fetch_pwm_params(td);1980 } else {1981 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");1982 if (IS_ERR(td->vdd_reg)) {1983 dev_err(td->dev, "couldn't get vdd_cpu regulator\n");1984 return PTR_ERR(td->vdd_reg);1985 }1986 td->pmu_if = TEGRA_DFLL_PMU_I2C;1987 ret = dfll_fetch_i2c_params(td);1988 }1989 if (ret)1990 return ret;1991 1992 ret = dfll_build_lut(td);1993 if (ret) {1994 dev_err(td->dev, "couldn't build LUT\n");1995 return ret;1996 }1997 1998 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);1999 if (!mem) {2000 dev_err(td->dev, "no control register resource\n");2001 return -ENODEV;2002 }2003 2004 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));2005 if (!td->base) {2006 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");2007 return -ENODEV;2008 }2009 2010 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);2011 if (!mem) {2012 dev_err(td->dev, "no i2c_base resource\n");2013 return -ENODEV;2014 }2015 2016 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));2017 if (!td->i2c_base) {2018 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");2019 return -ENODEV;2020 }2021 2022 mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);2023 if (!mem) {2024 dev_err(td->dev, "no i2c_controller_base resource\n");2025 return -ENODEV;2026 }2027 2028 td->i2c_controller_base = devm_ioremap(td->dev, mem->start,2029 resource_size(mem));2030 if (!td->i2c_controller_base) {2031 dev_err(td->dev,2032 "couldn't ioremap i2c_controller_base resource\n");2033 return -ENODEV;2034 }2035 2036 mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);2037 if (!mem) {2038 dev_err(td->dev, "no lut_base resource\n");2039 return -ENODEV;2040 }2041 2042 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));2043 if (!td->lut_base) {2044 dev_err(td->dev,2045 "couldn't ioremap lut_base resource\n");2046 return -ENODEV;2047 }2048 2049 ret = dfll_init_clks(td);2050 if (ret) {2051 dev_err(&pdev->dev, "DFLL clock init error\n");2052 return ret;2053 }2054 2055 /* Enable the clocks and set the device up */2056 ret = dfll_init(td);2057 if (ret)2058 return ret;2059 2060 ret = dfll_register_clk(td);2061 if (ret) {2062 dev_err(&pdev->dev, "DFLL clk registration failed\n");2063 return ret;2064 }2065 2066 dfll_debug_init(td);2067 2068 return 0;2069}2070EXPORT_SYMBOL(tegra_dfll_register);2071 2072/**2073 * tegra_dfll_unregister - release all of the DFLL driver resources for a device2074 * @pdev: DFLL platform_device *2075 *2076 * Unbind this driver from the DFLL hardware device represented by2077 * @pdev. The DFLL must be disabled for this to succeed. Returns a2078 * soc pointer upon success or -EBUSY if the DFLL is still active.2079 */2080struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)2081{2082 struct tegra_dfll *td = platform_get_drvdata(pdev);2083 2084 /*2085 * Note that exiting early here doesn't prevent unbinding the driver.2086 * Exiting early here only leaks some resources.2087 */2088 if (td->mode != DFLL_DISABLED) {2089 dev_err(&pdev->dev,2090 "must disable DFLL before removing driver\n");2091 return ERR_PTR(-EBUSY);2092 }2093 2094 debugfs_remove_recursive(td->debugfs_dir);2095 2096 dfll_unregister_clk(td);2097 pm_runtime_disable(&pdev->dev);2098 2099 clk_unprepare(td->ref_clk);2100 clk_unprepare(td->soc_clk);2101 clk_unprepare(td->i2c_clk);2102 2103 reset_control_assert(td->dvco_rst);2104 reset_control_assert(td->dfll_rst);2105 2106 return td->soc;2107}2108EXPORT_SYMBOL(tegra_dfll_unregister);2109