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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * This header provides IDs for clocks common between several Tegra SoCs4 */5#ifndef _TEGRA_CLK_ID_H6#define _TEGRA_CLK_ID_H7 8enum clk_id {9 tegra_clk_actmon,10 tegra_clk_adx,11 tegra_clk_adx1,12 tegra_clk_afi,13 tegra_clk_amx,14 tegra_clk_amx1,15 tegra_clk_apb2ape,16 tegra_clk_ahbdma,17 tegra_clk_apbdma,18 tegra_clk_apbif,19 tegra_clk_ape,20 tegra_clk_audio0,21 tegra_clk_audio0_2x,22 tegra_clk_audio0_mux,23 tegra_clk_audio1,24 tegra_clk_audio1_2x,25 tegra_clk_audio1_mux,26 tegra_clk_audio2,27 tegra_clk_audio2_2x,28 tegra_clk_audio2_mux,29 tegra_clk_audio3,30 tegra_clk_audio3_2x,31 tegra_clk_audio3_mux,32 tegra_clk_audio4,33 tegra_clk_audio4_2x,34 tegra_clk_audio4_mux,35 tegra_clk_bsea,36 tegra_clk_bsev,37 tegra_clk_cclk_g,38 tegra_clk_cclk_lp,39 tegra_clk_cilab,40 tegra_clk_cilcd,41 tegra_clk_cile,42 tegra_clk_clk_32k,43 tegra_clk_clk72Mhz,44 tegra_clk_clk72Mhz_8,45 tegra_clk_clk_m,46 tegra_clk_osc,47 tegra_clk_osc_div2,48 tegra_clk_osc_div4,49 tegra_clk_cml0,50 tegra_clk_cml1,51 tegra_clk_csi,52 tegra_clk_csite,53 tegra_clk_csite_8,54 tegra_clk_csus,55 tegra_clk_cve,56 tegra_clk_dam0,57 tegra_clk_dam1,58 tegra_clk_dam2,59 tegra_clk_d_audio,60 tegra_clk_dbgapb,61 tegra_clk_dds,62 tegra_clk_dfll_ref,63 tegra_clk_dfll_soc,64 tegra_clk_disp1,65 tegra_clk_disp1_8,66 tegra_clk_disp2,67 tegra_clk_disp2_8,68 tegra_clk_dp2,69 tegra_clk_dpaux,70 tegra_clk_dpaux1,71 tegra_clk_dsialp,72 tegra_clk_dsia_mux,73 tegra_clk_dsiblp,74 tegra_clk_dsib_mux,75 tegra_clk_dtv,76 tegra_clk_emc,77 tegra_clk_entropy,78 tegra_clk_entropy_8,79 tegra_clk_epp,80 tegra_clk_epp_8,81 tegra_clk_extern1,82 tegra_clk_extern2,83 tegra_clk_extern3,84 tegra_clk_fuse,85 tegra_clk_fuse_burn,86 tegra_clk_gpu,87 tegra_clk_gr2d,88 tegra_clk_gr2d_8,89 tegra_clk_gr3d,90 tegra_clk_gr3d_8,91 tegra_clk_hclk,92 tegra_clk_hda,93 tegra_clk_hda_8,94 tegra_clk_hda2codec_2x,95 tegra_clk_hda2codec_2x_8,96 tegra_clk_hda2hdmi,97 tegra_clk_hdmi,98 tegra_clk_hdmi_audio,99 tegra_clk_host1x,100 tegra_clk_host1x_8,101 tegra_clk_host1x_9,102 tegra_clk_hsic_trk,103 tegra_clk_i2c1,104 tegra_clk_i2c2,105 tegra_clk_i2c3,106 tegra_clk_i2c4,107 tegra_clk_i2c5,108 tegra_clk_i2c6,109 tegra_clk_i2cslow,110 tegra_clk_i2s0,111 tegra_clk_i2s0_sync,112 tegra_clk_i2s1,113 tegra_clk_i2s1_sync,114 tegra_clk_i2s2,115 tegra_clk_i2s2_sync,116 tegra_clk_i2s3,117 tegra_clk_i2s3_sync,118 tegra_clk_i2s4,119 tegra_clk_i2s4_sync,120 tegra_clk_isp,121 tegra_clk_isp_8,122 tegra_clk_isp_9,123 tegra_clk_ispb,124 tegra_clk_kbc,125 tegra_clk_kfuse,126 tegra_clk_la,127 tegra_clk_maud,128 tegra_clk_mipi,129 tegra_clk_mipibif,130 tegra_clk_mipi_cal,131 tegra_clk_mpe,132 tegra_clk_mselect,133 tegra_clk_msenc,134 tegra_clk_ndflash,135 tegra_clk_ndflash_8,136 tegra_clk_ndspeed,137 tegra_clk_ndspeed_8,138 tegra_clk_nor,139 tegra_clk_nvdec,140 tegra_clk_nvenc,141 tegra_clk_nvjpg,142 tegra_clk_owr,143 tegra_clk_owr_8,144 tegra_clk_pcie,145 tegra_clk_pclk,146 tegra_clk_pll_a,147 tegra_clk_pll_a_out0,148 tegra_clk_pll_a1,149 tegra_clk_pll_c,150 tegra_clk_pll_c2,151 tegra_clk_pll_c3,152 tegra_clk_pll_c4,153 tegra_clk_pll_c4_out0,154 tegra_clk_pll_c4_out1,155 tegra_clk_pll_c4_out2,156 tegra_clk_pll_c4_out3,157 tegra_clk_pll_c_out1,158 tegra_clk_pll_d,159 tegra_clk_pll_d2,160 tegra_clk_pll_d2_out0,161 tegra_clk_pll_d_out0,162 tegra_clk_pll_dp,163 tegra_clk_pll_e_out0,164 tegra_clk_pll_g_ref,165 tegra_clk_pll_m,166 tegra_clk_pll_m_out1,167 tegra_clk_pll_mb,168 tegra_clk_pll_p,169 tegra_clk_pll_p_out1,170 tegra_clk_pll_p_out2,171 tegra_clk_pll_p_out2_int,172 tegra_clk_pll_p_out3,173 tegra_clk_pll_p_out4,174 tegra_clk_pll_p_out4_cpu,175 tegra_clk_pll_p_out5,176 tegra_clk_pll_p_out_hsio,177 tegra_clk_pll_p_out_xusb,178 tegra_clk_pll_p_out_cpu,179 tegra_clk_pll_p_out_adsp,180 tegra_clk_pll_ref,181 tegra_clk_pll_re_out,182 tegra_clk_pll_re_vco,183 tegra_clk_pll_u,184 tegra_clk_pll_u_out,185 tegra_clk_pll_u_out1,186 tegra_clk_pll_u_out2,187 tegra_clk_pll_u_12m,188 tegra_clk_pll_u_480m,189 tegra_clk_pll_u_48m,190 tegra_clk_pll_u_60m,191 tegra_clk_pll_x,192 tegra_clk_pll_x_out0,193 tegra_clk_pwm,194 tegra_clk_qspi,195 tegra_clk_rtc,196 tegra_clk_sata,197 tegra_clk_sata_8,198 tegra_clk_sata_cold,199 tegra_clk_sata_oob,200 tegra_clk_sata_oob_8,201 tegra_clk_sbc1,202 tegra_clk_sbc1_8,203 tegra_clk_sbc1_9,204 tegra_clk_sbc2,205 tegra_clk_sbc2_8,206 tegra_clk_sbc2_9,207 tegra_clk_sbc3,208 tegra_clk_sbc3_8,209 tegra_clk_sbc3_9,210 tegra_clk_sbc4,211 tegra_clk_sbc4_8,212 tegra_clk_sbc4_9,213 tegra_clk_sbc5,214 tegra_clk_sbc5_8,215 tegra_clk_sbc6,216 tegra_clk_sbc6_8,217 tegra_clk_sclk,218 tegra_clk_sdmmc_legacy,219 tegra_clk_sdmmc1,220 tegra_clk_sdmmc1_8,221 tegra_clk_sdmmc1_9,222 tegra_clk_sdmmc2,223 tegra_clk_sdmmc2_8,224 tegra_clk_sdmmc3,225 tegra_clk_sdmmc3_8,226 tegra_clk_sdmmc3_9,227 tegra_clk_sdmmc4,228 tegra_clk_sdmmc4_8,229 tegra_clk_se,230 tegra_clk_se_10,231 tegra_clk_soc_therm,232 tegra_clk_soc_therm_8,233 tegra_clk_sor0,234 tegra_clk_sor0_out,235 tegra_clk_sor1,236 tegra_clk_sor1_out,237 tegra_clk_spdif,238 tegra_clk_spdif_2x,239 tegra_clk_spdif_in,240 tegra_clk_spdif_in_8,241 tegra_clk_spdif_in_sync,242 tegra_clk_spdif_mux,243 tegra_clk_spdif_out,244 tegra_clk_timer,245 tegra_clk_trace,246 tegra_clk_tsec,247 tegra_clk_tsec_8,248 tegra_clk_tsecb,249 tegra_clk_tsensor,250 tegra_clk_tvdac,251 tegra_clk_tvo,252 tegra_clk_uarta,253 tegra_clk_uarta_8,254 tegra_clk_uartb,255 tegra_clk_uartb_8,256 tegra_clk_uartc,257 tegra_clk_uartc_8,258 tegra_clk_uartd,259 tegra_clk_uartd_8,260 tegra_clk_uarte,261 tegra_clk_uarte_8,262 tegra_clk_uartape,263 tegra_clk_usb2,264 tegra_clk_usb2_hsic_trk,265 tegra_clk_usb2_trk,266 tegra_clk_usb3,267 tegra_clk_usbd,268 tegra_clk_vcp,269 tegra_clk_vde,270 tegra_clk_vde_8,271 tegra_clk_vfir,272 tegra_clk_vi,273 tegra_clk_vi_8,274 tegra_clk_vi_9,275 tegra_clk_vi_10,276 tegra_clk_vi_i2c,277 tegra_clk_vic03,278 tegra_clk_vic03_8,279 tegra_clk_vim2_clk,280 tegra_clk_vimclk_sync,281 tegra_clk_vi_sensor,282 tegra_clk_vi_sensor_8,283 tegra_clk_vi_sensor_9,284 tegra_clk_vi_sensor2,285 tegra_clk_vi_sensor2_8,286 tegra_clk_xusb_dev,287 tegra_clk_xusb_dev_src,288 tegra_clk_xusb_dev_src_8,289 tegra_clk_xusb_falcon_src,290 tegra_clk_xusb_falcon_src_8,291 tegra_clk_xusb_fs_src,292 tegra_clk_xusb_gate,293 tegra_clk_xusb_host,294 tegra_clk_xusb_host_src,295 tegra_clk_xusb_host_src_8,296 tegra_clk_xusb_hs_src,297 tegra_clk_xusb_hs_src_4,298 tegra_clk_xusb_ss,299 tegra_clk_xusb_ss_src,300 tegra_clk_xusb_ss_src_8,301 tegra_clk_xusb_ss_div2,302 tegra_clk_xusb_ssp_src,303 tegra_clk_sclk_mux,304 tegra_clk_sor_safe,305 tegra_clk_cec,306 tegra_clk_ispa,307 tegra_clk_dmic1,308 tegra_clk_dmic2,309 tegra_clk_dmic3,310 tegra_clk_dmic1_sync_clk,311 tegra_clk_dmic2_sync_clk,312 tegra_clk_dmic3_sync_clk,313 tegra_clk_dmic1_sync_clk_mux,314 tegra_clk_dmic2_sync_clk_mux,315 tegra_clk_dmic3_sync_clk_mux,316 tegra_clk_iqc1,317 tegra_clk_iqc2,318 tegra_clk_pll_a_out_adsp,319 tegra_clk_pll_a_out0_out_adsp,320 tegra_clk_adsp,321 tegra_clk_adsp_neon,322 tegra_clk_max,323};324 325#endif /* _TEGRA_CLK_ID_H */326