1598 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.4 */5 6#include <linux/io.h>7#include <linux/clk-provider.h>8#include <linux/clkdev.h>9#include <linux/of.h>10#include <linux/of_address.h>11#include <linux/delay.h>12#include <linux/export.h>13#include <linux/clk/tegra.h>14#include <dt-bindings/clock/tegra124-car.h>15#include <dt-bindings/reset/tegra124-car.h>16 17#include "clk.h"18#include "clk-id.h"19 20/*21 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register22 * banks present in the Tegra124/132 CAR IP block. The banks are23 * identified by single letters, e.g.: L, H, U, V, W, X. See24 * periph_regs[] in drivers/clk/tegra/clk.c25 */26#define TEGRA124_CAR_BANK_COUNT 627 28#define CLK_SOURCE_CSITE 0x1d429#define CLK_SOURCE_EMC 0x19c30#define CLK_SOURCE_SOR0 0x41431 32#define RST_DFLL_DVCO 0x2f433#define DVFS_DFLL_RESET_SHIFT 034 35#define PLLC_BASE 0x8036#define PLLC_OUT 0x8437#define PLLC_MISC2 0x8838#define PLLC_MISC 0x8c39#define PLLC2_BASE 0x4e840#define PLLC2_MISC 0x4ec41#define PLLC3_BASE 0x4fc42#define PLLC3_MISC 0x50043#define PLLM_BASE 0x9044#define PLLM_OUT 0x9445#define PLLM_MISC 0x9c46#define PLLP_BASE 0xa047#define PLLP_MISC 0xac48#define PLLA_BASE 0xb049#define PLLA_MISC 0xbc50#define PLLD_BASE 0xd051#define PLLD_MISC 0xdc52#define PLLU_BASE 0xc053#define PLLU_MISC 0xcc54#define PLLX_BASE 0xe055#define PLLX_MISC 0xe456#define PLLX_MISC2 0x51457#define PLLX_MISC3 0x51858#define PLLE_BASE 0xe859#define PLLE_MISC 0xec60#define PLLD2_BASE 0x4b861#define PLLD2_MISC 0x4bc62#define PLLE_AUX 0x48c63#define PLLRE_BASE 0x4c464#define PLLRE_MISC 0x4c865#define PLLDP_BASE 0x59066#define PLLDP_MISC 0x59467#define PLLC4_BASE 0x5a468#define PLLC4_MISC 0x5a869 70#define PLLC_IDDQ_BIT 2671#define PLLRE_IDDQ_BIT 1672#define PLLSS_IDDQ_BIT 1973 74#define PLL_BASE_LOCK BIT(27)75#define PLLE_MISC_LOCK BIT(11)76#define PLLRE_MISC_LOCK BIT(24)77 78#define PLL_MISC_LOCK_ENABLE 1879#define PLLC_MISC_LOCK_ENABLE 2480#define PLLDU_MISC_LOCK_ENABLE 2281#define PLLE_MISC_LOCK_ENABLE 982#define PLLRE_MISC_LOCK_ENABLE 3083#define PLLSS_MISC_LOCK_ENABLE 3084 85#define PLLXC_SW_MAX_P 686 87#define PMC_PLLM_WB0_OVERRIDE 0x1dc88#define PMC_PLLM_WB0_OVERRIDE_2 0x2b089 90#define CCLKG_BURST_POLICY 0x36891 92/* Tegra CPU clock and reset control regs */93#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x47094 95#define MASK(x) (BIT(x) - 1)96 97#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \98 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \99 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\100 0, TEGRA_PERIPH_NO_GATE, _clk_id,\101 _parents##_idx, 0, _lock)102 103#define NODIV(_name, _parents, _offset, \104 _mux_shift, _mux_mask, _clk_num, \105 _gate_flags, _clk_id, _lock) \106 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\107 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\108 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\109 _clk_id, _parents##_idx, 0, _lock)110 111#ifdef CONFIG_PM_SLEEP112static struct cpu_clk_suspend_context {113 u32 clk_csite_src;114 u32 cclkg_burst;115 u32 cclkg_divider;116} tegra124_cpu_clk_sctx;117#endif118 119static void __iomem *clk_base;120static void __iomem *pmc_base;121 122static unsigned long osc_freq;123static unsigned long pll_ref_freq;124 125static DEFINE_SPINLOCK(pll_d_lock);126static DEFINE_SPINLOCK(pll_e_lock);127static DEFINE_SPINLOCK(pll_re_lock);128static DEFINE_SPINLOCK(pll_u_lock);129static DEFINE_SPINLOCK(emc_lock);130static DEFINE_SPINLOCK(sor0_lock);131 132/* possible OSC frequencies in Hz */133static unsigned long tegra124_input_freq[] = {134 [ 0] = 13000000,135 [ 1] = 16800000,136 [ 4] = 19200000,137 [ 5] = 38400000,138 [ 8] = 12000000,139 [ 9] = 48000000,140 [12] = 26000000,141};142 143static struct div_nmp pllxc_nmp = {144 .divm_shift = 0,145 .divm_width = 8,146 .divn_shift = 8,147 .divn_width = 8,148 .divp_shift = 20,149 .divp_width = 4,150};151 152static const struct pdiv_map pllxc_p[] = {153 { .pdiv = 1, .hw_val = 0 },154 { .pdiv = 2, .hw_val = 1 },155 { .pdiv = 3, .hw_val = 2 },156 { .pdiv = 4, .hw_val = 3 },157 { .pdiv = 5, .hw_val = 4 },158 { .pdiv = 6, .hw_val = 5 },159 { .pdiv = 8, .hw_val = 6 },160 { .pdiv = 10, .hw_val = 7 },161 { .pdiv = 12, .hw_val = 8 },162 { .pdiv = 16, .hw_val = 9 },163 { .pdiv = 12, .hw_val = 10 },164 { .pdiv = 16, .hw_val = 11 },165 { .pdiv = 20, .hw_val = 12 },166 { .pdiv = 24, .hw_val = 13 },167 { .pdiv = 32, .hw_val = 14 },168 { .pdiv = 0, .hw_val = 0 },169};170 171static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {172 /* 1 GHz */173 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */174 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */175 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */176 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */177 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */178 { 0, 0, 0, 0, 0, 0 },179};180 181static struct tegra_clk_pll_params pll_x_params = {182 .input_min = 12000000,183 .input_max = 800000000,184 .cf_min = 12000000,185 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */186 .vco_min = 700000000,187 .vco_max = 3000000000UL,188 .base_reg = PLLX_BASE,189 .misc_reg = PLLX_MISC,190 .lock_mask = PLL_BASE_LOCK,191 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,192 .lock_delay = 300,193 .iddq_reg = PLLX_MISC3,194 .iddq_bit_idx = 3,195 .max_p = 6,196 .dyn_ramp_reg = PLLX_MISC2,197 .stepa_shift = 16,198 .stepb_shift = 24,199 .pdiv_tohw = pllxc_p,200 .div_nmp = &pllxc_nmp,201 .freq_table = pll_x_freq_table,202 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,203};204 205static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {206 { 12000000, 624000000, 104, 1, 2, 0 },207 { 12000000, 600000000, 100, 1, 2, 0 },208 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */209 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */210 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */211 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */212 { 0, 0, 0, 0, 0, 0 },213};214 215static struct tegra_clk_pll_params pll_c_params = {216 .input_min = 12000000,217 .input_max = 800000000,218 .cf_min = 12000000,219 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */220 .vco_min = 600000000,221 .vco_max = 1400000000,222 .base_reg = PLLC_BASE,223 .misc_reg = PLLC_MISC,224 .lock_mask = PLL_BASE_LOCK,225 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,226 .lock_delay = 300,227 .iddq_reg = PLLC_MISC,228 .iddq_bit_idx = PLLC_IDDQ_BIT,229 .max_p = PLLXC_SW_MAX_P,230 .dyn_ramp_reg = PLLC_MISC2,231 .stepa_shift = 17,232 .stepb_shift = 9,233 .pdiv_tohw = pllxc_p,234 .div_nmp = &pllxc_nmp,235 .freq_table = pll_c_freq_table,236 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,237};238 239static struct div_nmp pllcx_nmp = {240 .divm_shift = 0,241 .divm_width = 2,242 .divn_shift = 8,243 .divn_width = 8,244 .divp_shift = 20,245 .divp_width = 3,246};247 248static const struct pdiv_map pllc_p[] = {249 { .pdiv = 1, .hw_val = 0 },250 { .pdiv = 2, .hw_val = 1 },251 { .pdiv = 3, .hw_val = 2 },252 { .pdiv = 4, .hw_val = 3 },253 { .pdiv = 6, .hw_val = 4 },254 { .pdiv = 8, .hw_val = 5 },255 { .pdiv = 12, .hw_val = 6 },256 { .pdiv = 16, .hw_val = 7 },257 { .pdiv = 0, .hw_val = 0 },258};259 260static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {261 { 12000000, 600000000, 100, 1, 2, 0 },262 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */263 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */264 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */265 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */266 { 0, 0, 0, 0, 0, 0 },267};268 269static struct tegra_clk_pll_params pll_c2_params = {270 .input_min = 12000000,271 .input_max = 48000000,272 .cf_min = 12000000,273 .cf_max = 19200000,274 .vco_min = 600000000,275 .vco_max = 1200000000,276 .base_reg = PLLC2_BASE,277 .misc_reg = PLLC2_MISC,278 .lock_mask = PLL_BASE_LOCK,279 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,280 .lock_delay = 300,281 .pdiv_tohw = pllc_p,282 .div_nmp = &pllcx_nmp,283 .max_p = 7,284 .ext_misc_reg[0] = 0x4f0,285 .ext_misc_reg[1] = 0x4f4,286 .ext_misc_reg[2] = 0x4f8,287 .freq_table = pll_cx_freq_table,288 .flags = TEGRA_PLL_USE_LOCK,289};290 291static struct tegra_clk_pll_params pll_c3_params = {292 .input_min = 12000000,293 .input_max = 48000000,294 .cf_min = 12000000,295 .cf_max = 19200000,296 .vco_min = 600000000,297 .vco_max = 1200000000,298 .base_reg = PLLC3_BASE,299 .misc_reg = PLLC3_MISC,300 .lock_mask = PLL_BASE_LOCK,301 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,302 .lock_delay = 300,303 .pdiv_tohw = pllc_p,304 .div_nmp = &pllcx_nmp,305 .max_p = 7,306 .ext_misc_reg[0] = 0x504,307 .ext_misc_reg[1] = 0x508,308 .ext_misc_reg[2] = 0x50c,309 .freq_table = pll_cx_freq_table,310 .flags = TEGRA_PLL_USE_LOCK,311};312 313static struct div_nmp pllss_nmp = {314 .divm_shift = 0,315 .divm_width = 8,316 .divn_shift = 8,317 .divn_width = 8,318 .divp_shift = 20,319 .divp_width = 4,320};321 322static const struct pdiv_map pll12g_ssd_esd_p[] = {323 { .pdiv = 1, .hw_val = 0 },324 { .pdiv = 2, .hw_val = 1 },325 { .pdiv = 3, .hw_val = 2 },326 { .pdiv = 4, .hw_val = 3 },327 { .pdiv = 5, .hw_val = 4 },328 { .pdiv = 6, .hw_val = 5 },329 { .pdiv = 8, .hw_val = 6 },330 { .pdiv = 10, .hw_val = 7 },331 { .pdiv = 12, .hw_val = 8 },332 { .pdiv = 16, .hw_val = 9 },333 { .pdiv = 12, .hw_val = 10 },334 { .pdiv = 16, .hw_val = 11 },335 { .pdiv = 20, .hw_val = 12 },336 { .pdiv = 24, .hw_val = 13 },337 { .pdiv = 32, .hw_val = 14 },338 { .pdiv = 0, .hw_val = 0 },339};340 341static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {342 { 12000000, 600000000, 100, 1, 2, 0 },343 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */344 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */345 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */346 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */347 { 0, 0, 0, 0, 0, 0 },348};349 350static struct tegra_clk_pll_params pll_c4_params = {351 .input_min = 12000000,352 .input_max = 1000000000,353 .cf_min = 12000000,354 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */355 .vco_min = 600000000,356 .vco_max = 1200000000,357 .base_reg = PLLC4_BASE,358 .misc_reg = PLLC4_MISC,359 .lock_mask = PLL_BASE_LOCK,360 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,361 .lock_delay = 300,362 .iddq_reg = PLLC4_BASE,363 .iddq_bit_idx = PLLSS_IDDQ_BIT,364 .pdiv_tohw = pll12g_ssd_esd_p,365 .div_nmp = &pllss_nmp,366 .ext_misc_reg[0] = 0x5ac,367 .ext_misc_reg[1] = 0x5b0,368 .ext_misc_reg[2] = 0x5b4,369 .freq_table = pll_c4_freq_table,370 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,371};372 373static const struct pdiv_map pllm_p[] = {374 { .pdiv = 1, .hw_val = 0 },375 { .pdiv = 2, .hw_val = 1 },376 { .pdiv = 3, .hw_val = 2 },377 { .pdiv = 4, .hw_val = 3 },378 { .pdiv = 5, .hw_val = 4 },379 { .pdiv = 6, .hw_val = 5 },380 { .pdiv = 8, .hw_val = 6 },381 { .pdiv = 10, .hw_val = 7 },382 { .pdiv = 12, .hw_val = 8 },383 { .pdiv = 16, .hw_val = 9 },384 { .pdiv = 12, .hw_val = 10 },385 { .pdiv = 16, .hw_val = 11 },386 { .pdiv = 20, .hw_val = 12 },387 { .pdiv = 24, .hw_val = 13 },388 { .pdiv = 32, .hw_val = 14 },389 { .pdiv = 0, .hw_val = 0 },390};391 392static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {393 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */394 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */395 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */396 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */397 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */398 { 0, 0, 0, 0, 0, 0},399};400 401static struct div_nmp pllm_nmp = {402 .divm_shift = 0,403 .divm_width = 8,404 .override_divm_shift = 0,405 .divn_shift = 8,406 .divn_width = 8,407 .override_divn_shift = 8,408 .divp_shift = 20,409 .divp_width = 1,410 .override_divp_shift = 27,411};412 413static struct tegra_clk_pll_params pll_m_params = {414 .input_min = 12000000,415 .input_max = 500000000,416 .cf_min = 12000000,417 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */418 .vco_min = 400000000,419 .vco_max = 1066000000,420 .base_reg = PLLM_BASE,421 .misc_reg = PLLM_MISC,422 .lock_mask = PLL_BASE_LOCK,423 .lock_delay = 300,424 .max_p = 5,425 .pdiv_tohw = pllm_p,426 .div_nmp = &pllm_nmp,427 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,428 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,429 .freq_table = pll_m_freq_table,430 .flags = TEGRA_PLL_USE_LOCK,431};432 433static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {434 /* PLLE special case: use cpcon field to store cml divider value */435 { 336000000, 100000000, 100, 21, 16, 11 },436 { 312000000, 100000000, 200, 26, 24, 13 },437 { 13000000, 100000000, 200, 1, 26, 13 },438 { 12000000, 100000000, 200, 1, 24, 13 },439 { 0, 0, 0, 0, 0, 0 },440};441 442static const struct pdiv_map plle_p[] = {443 { .pdiv = 1, .hw_val = 0 },444 { .pdiv = 2, .hw_val = 1 },445 { .pdiv = 3, .hw_val = 2 },446 { .pdiv = 4, .hw_val = 3 },447 { .pdiv = 5, .hw_val = 4 },448 { .pdiv = 6, .hw_val = 5 },449 { .pdiv = 8, .hw_val = 6 },450 { .pdiv = 10, .hw_val = 7 },451 { .pdiv = 12, .hw_val = 8 },452 { .pdiv = 16, .hw_val = 9 },453 { .pdiv = 12, .hw_val = 10 },454 { .pdiv = 16, .hw_val = 11 },455 { .pdiv = 20, .hw_val = 12 },456 { .pdiv = 24, .hw_val = 13 },457 { .pdiv = 32, .hw_val = 14 },458 { .pdiv = 1, .hw_val = 0 },459};460 461static struct div_nmp plle_nmp = {462 .divm_shift = 0,463 .divm_width = 8,464 .divn_shift = 8,465 .divn_width = 8,466 .divp_shift = 24,467 .divp_width = 4,468};469 470static struct tegra_clk_pll_params pll_e_params = {471 .input_min = 12000000,472 .input_max = 1000000000,473 .cf_min = 12000000,474 .cf_max = 75000000,475 .vco_min = 1600000000,476 .vco_max = 2400000000U,477 .base_reg = PLLE_BASE,478 .misc_reg = PLLE_MISC,479 .aux_reg = PLLE_AUX,480 .lock_mask = PLLE_MISC_LOCK,481 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,482 .lock_delay = 300,483 .pdiv_tohw = plle_p,484 .div_nmp = &plle_nmp,485 .freq_table = pll_e_freq_table,486 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,487 .fixed_rate = 100000000,488};489 490static const struct clk_div_table pll_re_div_table[] = {491 { .val = 0, .div = 1 },492 { .val = 1, .div = 2 },493 { .val = 2, .div = 3 },494 { .val = 3, .div = 4 },495 { .val = 4, .div = 5 },496 { .val = 5, .div = 6 },497 { .val = 0, .div = 0 },498};499 500static struct div_nmp pllre_nmp = {501 .divm_shift = 0,502 .divm_width = 8,503 .divn_shift = 8,504 .divn_width = 8,505 .divp_shift = 16,506 .divp_width = 4,507};508 509static struct tegra_clk_pll_params pll_re_vco_params = {510 .input_min = 12000000,511 .input_max = 1000000000,512 .cf_min = 12000000,513 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */514 .vco_min = 300000000,515 .vco_max = 600000000,516 .base_reg = PLLRE_BASE,517 .misc_reg = PLLRE_MISC,518 .lock_mask = PLLRE_MISC_LOCK,519 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,520 .lock_delay = 300,521 .iddq_reg = PLLRE_MISC,522 .iddq_bit_idx = PLLRE_IDDQ_BIT,523 .div_nmp = &pllre_nmp,524 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |525 TEGRA_PLL_LOCK_MISC,526};527 528static struct div_nmp pllp_nmp = {529 .divm_shift = 0,530 .divm_width = 5,531 .divn_shift = 8,532 .divn_width = 10,533 .divp_shift = 20,534 .divp_width = 3,535};536 537static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {538 { 12000000, 408000000, 408, 12, 1, 8 },539 { 13000000, 408000000, 408, 13, 1, 8 },540 { 16800000, 408000000, 340, 14, 1, 8 },541 { 19200000, 408000000, 340, 16, 1, 8 },542 { 26000000, 408000000, 408, 26, 1, 8 },543 { 0, 0, 0, 0, 0, 0 },544};545 546static struct tegra_clk_pll_params pll_p_params = {547 .input_min = 2000000,548 .input_max = 31000000,549 .cf_min = 1000000,550 .cf_max = 6000000,551 .vco_min = 200000000,552 .vco_max = 700000000,553 .base_reg = PLLP_BASE,554 .misc_reg = PLLP_MISC,555 .lock_mask = PLL_BASE_LOCK,556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,557 .lock_delay = 300,558 .div_nmp = &pllp_nmp,559 .freq_table = pll_p_freq_table,560 .fixed_rate = 408000000,561 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |562 TEGRA_PLL_HAS_LOCK_ENABLE,563};564 565static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {566 { 9600000, 282240000, 147, 5, 1, 4 },567 { 9600000, 368640000, 192, 5, 1, 4 },568 { 9600000, 240000000, 200, 8, 1, 8 },569 { 28800000, 282240000, 245, 25, 1, 8 },570 { 28800000, 368640000, 320, 25, 1, 8 },571 { 28800000, 240000000, 200, 24, 1, 8 },572 { 0, 0, 0, 0, 0, 0 },573};574 575static struct tegra_clk_pll_params pll_a_params = {576 .input_min = 2000000,577 .input_max = 31000000,578 .cf_min = 1000000,579 .cf_max = 6000000,580 .vco_min = 200000000,581 .vco_max = 700000000,582 .base_reg = PLLA_BASE,583 .misc_reg = PLLA_MISC,584 .lock_mask = PLL_BASE_LOCK,585 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,586 .lock_delay = 300,587 .div_nmp = &pllp_nmp,588 .freq_table = pll_a_freq_table,589 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |590 TEGRA_PLL_HAS_LOCK_ENABLE,591};592 593static struct div_nmp plld_nmp = {594 .divm_shift = 0,595 .divm_width = 5,596 .divn_shift = 8,597 .divn_width = 11,598 .divp_shift = 20,599 .divp_width = 3,600};601 602static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {603 { 12000000, 216000000, 864, 12, 4, 12 },604 { 13000000, 216000000, 864, 13, 4, 12 },605 { 16800000, 216000000, 720, 14, 4, 12 },606 { 19200000, 216000000, 720, 16, 4, 12 },607 { 26000000, 216000000, 864, 26, 4, 12 },608 { 12000000, 594000000, 594, 12, 1, 12 },609 { 13000000, 594000000, 594, 13, 1, 12 },610 { 16800000, 594000000, 495, 14, 1, 12 },611 { 19200000, 594000000, 495, 16, 1, 12 },612 { 26000000, 594000000, 594, 26, 1, 12 },613 { 12000000, 1000000000, 1000, 12, 1, 12 },614 { 13000000, 1000000000, 1000, 13, 1, 12 },615 { 19200000, 1000000000, 625, 12, 1, 12 },616 { 26000000, 1000000000, 1000, 26, 1, 12 },617 { 0, 0, 0, 0, 0, 0 },618};619 620static struct tegra_clk_pll_params pll_d_params = {621 .input_min = 2000000,622 .input_max = 40000000,623 .cf_min = 1000000,624 .cf_max = 6000000,625 .vco_min = 500000000,626 .vco_max = 1000000000,627 .base_reg = PLLD_BASE,628 .misc_reg = PLLD_MISC,629 .lock_mask = PLL_BASE_LOCK,630 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,631 .lock_delay = 1000,632 .div_nmp = &plld_nmp,633 .freq_table = pll_d_freq_table,634 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |635 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,636};637 638static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {639 { 12000000, 594000000, 99, 1, 2, 0 },640 { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */641 { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */642 { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */643 { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */644 { 0, 0, 0, 0, 0, 0 },645};646 647static struct tegra_clk_pll_params tegra124_pll_d2_params = {648 .input_min = 12000000,649 .input_max = 1000000000,650 .cf_min = 12000000,651 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */652 .vco_min = 600000000,653 .vco_max = 1200000000,654 .base_reg = PLLD2_BASE,655 .misc_reg = PLLD2_MISC,656 .lock_mask = PLL_BASE_LOCK,657 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,658 .lock_delay = 300,659 .iddq_reg = PLLD2_BASE,660 .iddq_bit_idx = PLLSS_IDDQ_BIT,661 .pdiv_tohw = pll12g_ssd_esd_p,662 .div_nmp = &pllss_nmp,663 .ext_misc_reg[0] = 0x570,664 .ext_misc_reg[1] = 0x574,665 .ext_misc_reg[2] = 0x578,666 .max_p = 15,667 .freq_table = tegra124_pll_d2_freq_table,668 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,669};670 671static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {672 { 12000000, 600000000, 100, 1, 2, 0 },673 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */674 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */675 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */676 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */677 { 0, 0, 0, 0, 0, 0 },678};679 680static struct tegra_clk_pll_params pll_dp_params = {681 .input_min = 12000000,682 .input_max = 1000000000,683 .cf_min = 12000000,684 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */685 .vco_min = 600000000,686 .vco_max = 1200000000,687 .base_reg = PLLDP_BASE,688 .misc_reg = PLLDP_MISC,689 .lock_mask = PLL_BASE_LOCK,690 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,691 .lock_delay = 300,692 .iddq_reg = PLLDP_BASE,693 .iddq_bit_idx = PLLSS_IDDQ_BIT,694 .pdiv_tohw = pll12g_ssd_esd_p,695 .div_nmp = &pllss_nmp,696 .ext_misc_reg[0] = 0x598,697 .ext_misc_reg[1] = 0x59c,698 .ext_misc_reg[2] = 0x5a0,699 .max_p = 5,700 .freq_table = pll_dp_freq_table,701 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,702};703 704static const struct pdiv_map pllu_p[] = {705 { .pdiv = 1, .hw_val = 1 },706 { .pdiv = 2, .hw_val = 0 },707 { .pdiv = 0, .hw_val = 0 },708};709 710static struct div_nmp pllu_nmp = {711 .divm_shift = 0,712 .divm_width = 5,713 .divn_shift = 8,714 .divn_width = 10,715 .divp_shift = 20,716 .divp_width = 1,717};718 719static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {720 { 12000000, 480000000, 960, 12, 2, 12 },721 { 13000000, 480000000, 960, 13, 2, 12 },722 { 16800000, 480000000, 400, 7, 2, 5 },723 { 19200000, 480000000, 200, 4, 2, 3 },724 { 26000000, 480000000, 960, 26, 2, 12 },725 { 0, 0, 0, 0, 0, 0 },726};727 728static struct tegra_clk_pll_params pll_u_params = {729 .input_min = 2000000,730 .input_max = 40000000,731 .cf_min = 1000000,732 .cf_max = 6000000,733 .vco_min = 480000000,734 .vco_max = 960000000,735 .base_reg = PLLU_BASE,736 .misc_reg = PLLU_MISC,737 .lock_mask = PLL_BASE_LOCK,738 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,739 .lock_delay = 1000,740 .pdiv_tohw = pllu_p,741 .div_nmp = &pllu_nmp,742 .freq_table = pll_u_freq_table,743 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |744 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,745};746 747static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {748 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },749 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },750 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },751 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },752 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },753 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },754 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },755 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },756 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },757 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },758 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },759 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },760 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },761 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },762 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },763 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },764 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },765 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },766 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },767 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },768 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },769 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },770 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },771 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },772 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },773 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },774 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },775 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },776 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },777 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },778 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },779 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },780 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },781 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },782 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },783 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },784 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },785 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },786 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },787 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },788 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },789 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },790 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },791 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },792 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },793 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },794 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },795 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },796 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },797 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },798 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },799 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },800 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },801 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },802 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },803 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },804 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },805 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },806 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },807 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },808 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },809 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },810 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },811 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },812 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },813 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },814 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },815 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },816 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },817 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },818 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },819 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },820 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },821 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },822 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },823 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },824 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },825 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },826 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },827 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },828 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },829 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },830 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },831 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },832 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },833 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },834 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },835 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },836 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },837 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },838 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },839 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },840 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },841 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },842 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },843 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },844 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },845 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },846 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },847 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },848 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },849 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },850 [tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },851 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },852 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },853 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },854 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },855 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },856 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },859 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },860 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },861 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },862 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },863 [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },864 [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },865 [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },866 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },867 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },868 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },869 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },870 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },871 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },872 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },873 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },874 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },875 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },876 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },877 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },878 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },879 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },880 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },881 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },882 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },883 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },884 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },885 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },886 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },887 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },888 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },889 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },890 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },891 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },892 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },893 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },894 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },895 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },896 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },897 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },898 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },899 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },900 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },901 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },902 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },903 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },904 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },905 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },906 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },907 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },908 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },909 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },910 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },911 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },912 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },913 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },914 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },915 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },916 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },917 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },918 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },919 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },920 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },921 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },922 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },923 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },924 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },925 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },926 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },927 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },928 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },929 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },930 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },931 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },932};933 934static struct tegra_devclk devclks[] __initdata = {935 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },936 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },937 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },938 { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },939 { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },940 { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },941 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },942 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },943 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },944 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },945 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },946 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },947 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },948 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },949 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },950 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },951 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },952 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },953 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },954 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },955 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },956 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },957 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },958 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },959 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },960 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },961 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },962 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },963 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },964 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },965 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },966 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },967 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },968 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },969 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },970 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },971 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },972 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },973 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },974 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },975 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },976 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },977 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },978 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },979 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },980 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },981 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },982 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },983 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },984 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },985 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },986 { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },987 { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },988 { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },989 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },990 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },991 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },992 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },993 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },994 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },995 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },996 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },997 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },998 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },999 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },1000};1001 1002static const char * const sor0_parents[] = {1003 "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",1004 "pll_d2_out0", "clk_m",1005};1006 1007static const char * const sor0_out_parents[] = {1008 "clk_m", "sor0_pad_clkout",1009};1010 1011static struct tegra_periph_init_data tegra124_periph[] = {1012 TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,1013 CLK_SOURCE_SOR0, 29, 0x7, 0, 0, 0, 0,1014 0, 182, 0, tegra_clk_sor0, NULL, 0,1015 &sor0_lock),1016 TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,1017 CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,1018 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,1019 NULL, 0, &sor0_lock),1020};1021 1022static struct clk **clks;1023 1024static __init void tegra124_periph_clk_init(void __iomem *clk_base,1025 void __iomem *pmc_base)1026{1027 struct clk *clk;1028 unsigned int i;1029 1030 /* xusb_ss_div2 */1031 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,1032 1, 2);1033 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;1034 1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,1036 1, 17, 181);1037 clks[TEGRA124_CLK_DPAUX] = clk;1038 1039 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);1041 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;1042 1043 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,1044 clk_base, 0, 48,1045 periph_clk_enb_refcnt);1046 clks[TEGRA124_CLK_DSIA] = clk;1047 1048 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,1049 clk_base, 0, 82,1050 periph_clk_enb_refcnt);1051 clks[TEGRA124_CLK_DSIB] = clk;1052 1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,1054 &emc_lock);1055 clks[TEGRA124_CLK_MC] = clk;1056 1057 /* cml0 */1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,1059 0, 0, &pll_e_lock);1060 clk_register_clkdev(clk, "cml0", NULL);1061 clks[TEGRA124_CLK_CML0] = clk;1062 1063 /* cml1 */1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,1065 1, 0, &pll_e_lock);1066 clk_register_clkdev(clk, "cml1", NULL);1067 clks[TEGRA124_CLK_CML1] = clk;1068 1069 for (i = 0; i < ARRAY_SIZE(tegra124_periph); i++) {1070 struct tegra_periph_init_data *init = &tegra124_periph[i];1071 struct clk **clkp;1072 1073 clkp = tegra_lookup_dt_id(init->clk_id, tegra124_clks);1074 if (!clkp) {1075 pr_warn("clock %u not found\n", init->clk_id);1076 continue;1077 }1078 1079 clk = tegra_clk_register_periph_data(clk_base, init);1080 *clkp = clk;1081 }1082 1083 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);1084}1085 1086static void __init tegra124_pll_init(void __iomem *clk_base,1087 void __iomem *pmc)1088{1089 struct clk *clk;1090 1091 /* PLLC */1092 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,1093 pmc, 0, &pll_c_params, NULL);1094 clk_register_clkdev(clk, "pll_c", NULL);1095 clks[TEGRA124_CLK_PLL_C] = clk;1096 1097 /* PLLC_OUT1 */1098 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",1099 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,1100 8, 8, 1, NULL);1101 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",1102 clk_base + PLLC_OUT, 1, 0,1103 CLK_SET_RATE_PARENT, 0, NULL);1104 clk_register_clkdev(clk, "pll_c_out1", NULL);1105 clks[TEGRA124_CLK_PLL_C_OUT1] = clk;1106 1107 /* PLLC_UD */1108 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",1109 CLK_SET_RATE_PARENT, 1, 1);1110 clk_register_clkdev(clk, "pll_c_ud", NULL);1111 clks[TEGRA124_CLK_PLL_C_UD] = clk;1112 1113 /* PLLC2 */1114 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,1115 &pll_c2_params, NULL);1116 clk_register_clkdev(clk, "pll_c2", NULL);1117 clks[TEGRA124_CLK_PLL_C2] = clk;1118 1119 /* PLLC3 */1120 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,1121 &pll_c3_params, NULL);1122 clk_register_clkdev(clk, "pll_c3", NULL);1123 clks[TEGRA124_CLK_PLL_C3] = clk;1124 1125 /* PLLM */1126 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,1127 CLK_SET_RATE_GATE, &pll_m_params, NULL);1128 clk_register_clkdev(clk, "pll_m", NULL);1129 clks[TEGRA124_CLK_PLL_M] = clk;1130 1131 /* PLLM_OUT1 */1132 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,1134 8, 8, 1, NULL);1135 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",1136 clk_base + PLLM_OUT, 1, 0,1137 CLK_SET_RATE_PARENT, 0, NULL);1138 clk_register_clkdev(clk, "pll_m_out1", NULL);1139 clks[TEGRA124_CLK_PLL_M_OUT1] = clk;1140 1141 /* PLLM_UD */1142 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",1143 CLK_SET_RATE_PARENT, 1, 1);1144 clk_register_clkdev(clk, "pll_m_ud", NULL);1145 clks[TEGRA124_CLK_PLL_M_UD] = clk;1146 1147 /* PLLU */1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,1149 &pll_u_params, &pll_u_lock);1150 clk_register_clkdev(clk, "pll_u", NULL);1151 clks[TEGRA124_CLK_PLL_U] = clk;1152 1153 /* PLLU_480M */1154 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",1155 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,1156 22, 0, &pll_u_lock);1157 clk_register_clkdev(clk, "pll_u_480M", NULL);1158 clks[TEGRA124_CLK_PLL_U_480M] = clk;1159 1160 /* PLLU_60M */1161 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",1162 CLK_SET_RATE_PARENT, 1, 8);1163 clk_register_clkdev(clk, "pll_u_60M", NULL);1164 clks[TEGRA124_CLK_PLL_U_60M] = clk;1165 1166 /* PLLU_48M */1167 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",1168 CLK_SET_RATE_PARENT, 1, 10);1169 clk_register_clkdev(clk, "pll_u_48M", NULL);1170 clks[TEGRA124_CLK_PLL_U_48M] = clk;1171 1172 /* PLLU_12M */1173 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",1174 CLK_SET_RATE_PARENT, 1, 40);1175 clk_register_clkdev(clk, "pll_u_12M", NULL);1176 clks[TEGRA124_CLK_PLL_U_12M] = clk;1177 1178 /* PLLD */1179 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,1180 &pll_d_params, &pll_d_lock);1181 clk_register_clkdev(clk, "pll_d", NULL);1182 clks[TEGRA124_CLK_PLL_D] = clk;1183 1184 /* PLLD_OUT0 */1185 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",1186 CLK_SET_RATE_PARENT, 1, 2);1187 clk_register_clkdev(clk, "pll_d_out0", NULL);1188 clks[TEGRA124_CLK_PLL_D_OUT0] = clk;1189 1190 /* PLLRE */1191 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,1192 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);1193 clk_register_clkdev(clk, "pll_re_vco", NULL);1194 clks[TEGRA124_CLK_PLL_RE_VCO] = clk;1195 1196 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,1197 clk_base + PLLRE_BASE, 16, 4, 0,1198 pll_re_div_table, &pll_re_lock);1199 clk_register_clkdev(clk, "pll_re_out", NULL);1200 clks[TEGRA124_CLK_PLL_RE_OUT] = clk;1201 1202 /* PLLE */1203 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",1204 clk_base, 0, &pll_e_params, NULL);1205 clk_register_clkdev(clk, "pll_e", NULL);1206 clks[TEGRA124_CLK_PLL_E] = clk;1207 1208 /* PLLC4 */1209 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,1210 &pll_c4_params, NULL);1211 clk_register_clkdev(clk, "pll_c4", NULL);1212 clks[TEGRA124_CLK_PLL_C4] = clk;1213 1214 /* PLLDP */1215 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,1216 &pll_dp_params, NULL);1217 clk_register_clkdev(clk, "pll_dp", NULL);1218 clks[TEGRA124_CLK_PLL_DP] = clk;1219 1220 /* PLLD2 */1221 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,1222 &tegra124_pll_d2_params, NULL);1223 clk_register_clkdev(clk, "pll_d2", NULL);1224 clks[TEGRA124_CLK_PLL_D2] = clk;1225 1226 /* PLLD2_OUT0 */1227 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",1228 CLK_SET_RATE_PARENT, 1, 1);1229 clk_register_clkdev(clk, "pll_d2_out0", NULL);1230 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;1231 1232}1233 1234/* Tegra124 CPU clock and reset control functions */1235static void tegra124_wait_cpu_in_reset(u32 cpu)1236{1237 unsigned int reg;1238 1239 do {1240 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);1241 cpu_relax();1242 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */1243}1244 1245static void tegra124_disable_cpu_clock(u32 cpu)1246{1247 /* flow controller would take care in the power sequence. */1248}1249 1250#ifdef CONFIG_PM_SLEEP1251static void tegra124_cpu_clock_suspend(void)1252{1253 /* switch coresite to clk_m, save off original source */1254 tegra124_cpu_clk_sctx.clk_csite_src =1255 readl(clk_base + CLK_SOURCE_CSITE);1256 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);1257 1258 tegra124_cpu_clk_sctx.cclkg_burst =1259 readl(clk_base + CCLKG_BURST_POLICY);1260 tegra124_cpu_clk_sctx.cclkg_divider =1261 readl(clk_base + CCLKG_BURST_POLICY + 4);1262}1263 1264static void tegra124_cpu_clock_resume(void)1265{1266 writel(tegra124_cpu_clk_sctx.clk_csite_src,1267 clk_base + CLK_SOURCE_CSITE);1268 1269 writel(tegra124_cpu_clk_sctx.cclkg_burst,1270 clk_base + CCLKG_BURST_POLICY);1271 writel(tegra124_cpu_clk_sctx.cclkg_divider,1272 clk_base + CCLKG_BURST_POLICY + 4);1273}1274#endif1275 1276static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {1277 .wait_for_reset = tegra124_wait_cpu_in_reset,1278 .disable_clock = tegra124_disable_cpu_clock,1279#ifdef CONFIG_PM_SLEEP1280 .suspend = tegra124_cpu_clock_suspend,1281 .resume = tegra124_cpu_clock_resume,1282#endif1283};1284 1285static const struct of_device_id pmc_match[] __initconst = {1286 { .compatible = "nvidia,tegra124-pmc" },1287 { },1288};1289 1290static struct tegra_clk_init_table common_init_table[] __initdata = {1291 { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },1292 { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },1293 { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },1294 { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },1295 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 282240000, 0 },1296 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },1297 { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },1298 { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },1299 { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },1300 { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },1301 { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },1302 { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 },1303 { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },1304 { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },1305 { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },1306 { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },1307 { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },1308 { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },1309 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },1310 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },1311 { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },1312 { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },1313 { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },1314 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },1315 { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },1316 { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },1317 { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },1318 { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },1319 { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },1320 { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },1321 { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },1322 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },1323 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },1324 { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },1325 { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },1326 { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1327 { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1328 { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1329 { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1330 { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1331 { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1332 { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },1333 { TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 },1334 /* must be the last entry */1335 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },1336};1337 1338static struct tegra_clk_init_table tegra124_init_table[] __initdata = {1339 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },1340 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },1341 { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },1342 { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },1343 /* must be the last entry */1344 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },1345};1346 1347/* Tegra132 requires the SOC_THERM clock to remain active */1348static struct tegra_clk_init_table tegra132_init_table[] __initdata = {1349 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },1350 /* must be the last entry */1351 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },1352};1353 1354static struct tegra_audio_clk_info tegra124_audio_plls[] = {1355 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },1356};1357 1358/**1359 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs1360 *1361 * Program an initial clock rate and enable or disable clocks needed1362 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be1363 * called by assigning a pointer to it to tegra_clk_apply_init_table -1364 * this will be called as an arch_initcall. No return value.1365 */1366static void __init tegra124_clock_apply_init_table(void)1367{1368 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);1369 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);1370}1371 1372/**1373 * tegra124_car_barrier - wait for pending writes to the CAR to complete1374 *1375 * Wait for any outstanding writes to the CAR MMIO space from this CPU1376 * to complete before continuing execution. No return value.1377 */1378static void tegra124_car_barrier(void)1379{1380 readl_relaxed(clk_base + RST_DFLL_DVCO);1381}1382 1383/**1384 * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset1385 *1386 * Assert the reset line of the DFLL's DVCO. No return value.1387 */1388static void tegra124_clock_assert_dfll_dvco_reset(void)1389{1390 u32 v;1391 1392 v = readl_relaxed(clk_base + RST_DFLL_DVCO);1393 v |= (1 << DVFS_DFLL_RESET_SHIFT);1394 writel_relaxed(v, clk_base + RST_DFLL_DVCO);1395 tegra124_car_barrier();1396}1397 1398/**1399 * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset1400 *1401 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to1402 * operate. No return value.1403 */1404static void tegra124_clock_deassert_dfll_dvco_reset(void)1405{1406 u32 v;1407 1408 v = readl_relaxed(clk_base + RST_DFLL_DVCO);1409 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);1410 writel_relaxed(v, clk_base + RST_DFLL_DVCO);1411 tegra124_car_barrier();1412}1413 1414static int tegra124_reset_assert(unsigned long id)1415{1416 if (id == TEGRA124_RST_DFLL_DVCO)1417 tegra124_clock_assert_dfll_dvco_reset();1418 else1419 return -EINVAL;1420 1421 return 0;1422}1423 1424static int tegra124_reset_deassert(unsigned long id)1425{1426 if (id == TEGRA124_RST_DFLL_DVCO)1427 tegra124_clock_deassert_dfll_dvco_reset();1428 else1429 return -EINVAL;1430 1431 return 0;1432}1433 1434/**1435 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs1436 *1437 * Program an initial clock rate and enable or disable clocks needed1438 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be1439 * called by assigning a pointer to it to tegra_clk_apply_init_table -1440 * this will be called as an arch_initcall. No return value.1441 */1442static void __init tegra132_clock_apply_init_table(void)1443{1444 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);1445 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);1446}1447 1448/**1449 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T1321450 * @np: struct device_node * of the DT node for the SoC CAR IP block1451 *1452 * Register most of the clocks controlled by the CAR IP block.1453 * Everything in this function should be common to Tegra124 and Tegra132.1454 * No return value.1455 */1456static void __init tegra124_132_clock_init_pre(struct device_node *np)1457{1458 struct device_node *node;1459 u32 plld_base;1460 1461 clk_base = of_iomap(np, 0);1462 if (!clk_base) {1463 pr_err("ioremap tegra124/tegra132 CAR failed\n");1464 return;1465 }1466 1467 node = of_find_matching_node(NULL, pmc_match);1468 if (!node) {1469 pr_err("Failed to find pmc node\n");1470 WARN_ON(1);1471 return;1472 }1473 1474 pmc_base = of_iomap(node, 0);1475 of_node_put(node);1476 if (!pmc_base) {1477 pr_err("Can't map pmc registers\n");1478 WARN_ON(1);1479 return;1480 }1481 1482 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,1483 TEGRA124_CAR_BANK_COUNT);1484 if (!clks)1485 return;1486 1487 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,1488 ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,1489 &pll_ref_freq) < 0)1490 return;1491 1492 tegra_fixed_clk_init(tegra124_clks);1493 tegra124_pll_init(clk_base, pmc_base);1494 tegra124_periph_clk_init(clk_base, pmc_base);1495 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,1496 tegra124_audio_plls,1497 ARRAY_SIZE(tegra124_audio_plls), 24576000);1498 1499 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */1500 plld_base = readl(clk_base + PLLD_BASE);1501 plld_base &= ~BIT(25);1502 writel(plld_base, clk_base + PLLD_BASE);1503}1504 1505static struct clk *tegra124_clk_src_onecell_get(struct of_phandle_args *clkspec,1506 void *data)1507{1508 struct clk_hw *hw;1509 struct clk *clk;1510 1511 clk = of_clk_src_onecell_get(clkspec, data);1512 if (IS_ERR(clk))1513 return clk;1514 1515 hw = __clk_get_hw(clk);1516 1517 if (clkspec->args[0] == TEGRA124_CLK_EMC) {1518 if (!tegra124_clk_emc_driver_available(hw))1519 return ERR_PTR(-EPROBE_DEFER);1520 }1521 1522 return clk;1523}1524 1525/**1526 * tegra124_132_clock_init_post - clock initialization postamble for T124/T1321527 * @np: struct device_node * of the DT node for the SoC CAR IP block1528 *1529 * Register most of the clocks controlled by the CAR IP block.1530 * Everything in this function should be common to Tegra1241531 * and Tegra132. This function must be called after1532 * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.1533 * No return value.1534 */1535static void __init tegra124_132_clock_init_post(struct device_node *np)1536{1537 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,1538 &pll_x_params);1539 tegra_init_special_resets(1, tegra124_reset_assert,1540 tegra124_reset_deassert);1541 tegra_add_of_provider(np, tegra124_clk_src_onecell_get);1542 1543 clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,1544 &emc_lock);1545 1546 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));1547 1548 tegra_cpu_car_ops = &tegra124_cpu_car_ops;1549}1550 1551/**1552 * tegra124_clock_init - Tegra124-specific clock initialization1553 * @np: struct device_node * of the DT node for the SoC CAR IP block1554 *1555 * Register most SoC clocks for the Tegra124 system-on-chip. Most of1556 * this code is shared between the Tegra124 and Tegra132 SoCs,1557 * although some of the initial clock settings and CPU clocks differ.1558 * Intended to be called by the OF init code when a DT node with the1559 * "nvidia,tegra124-car" string is encountered, and declared with1560 * CLK_OF_DECLARE. No return value.1561 */1562static void __init tegra124_clock_init(struct device_node *np)1563{1564 tegra124_132_clock_init_pre(np);1565 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;1566 tegra124_132_clock_init_post(np);1567}1568 1569/**1570 * tegra132_clock_init - Tegra132-specific clock initialization1571 * @np: struct device_node * of the DT node for the SoC CAR IP block1572 *1573 * Register most SoC clocks for the Tegra132 system-on-chip. Most of1574 * this code is shared between the Tegra124 and Tegra132 SoCs,1575 * although some of the initial clock settings and CPU clocks differ.1576 * Intended to be called by the OF init code when a DT node with the1577 * "nvidia,tegra132-car" string is encountered, and declared with1578 * CLK_OF_DECLARE. No return value.1579 */1580static void __init tegra132_clock_init(struct device_node *np)1581{1582 tegra124_132_clock_init_pre(np);1583 1584 /*1585 * On Tegra132, these clocks are controlled by the1586 * CLUSTER_clocks IP block, located in the CPU complex1587 */1588 tegra124_clks[tegra_clk_cclk_g].present = false;1589 tegra124_clks[tegra_clk_cclk_lp].present = false;1590 tegra124_clks[tegra_clk_pll_x].present = false;1591 tegra124_clks[tegra_clk_pll_x_out0].present = false;1592 1593 tegra_clk_apply_init_table = tegra132_clock_apply_init_table;1594 tegra124_132_clock_init_post(np);1595}1596CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);1597CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);1598