1201 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.4 */5 6#include <linux/io.h>7#include <linux/clk-provider.h>8#include <linux/clkdev.h>9#include <linux/init.h>10#include <linux/of.h>11#include <linux/of_address.h>12#include <linux/platform_device.h>13#include <linux/clk/tegra.h>14#include <linux/delay.h>15#include <dt-bindings/clock/tegra20-car.h>16 17#include "clk.h"18#include "clk-id.h"19 20#define MISC_CLK_ENB 0x4821 22#define OSC_CTRL 0x5023#define OSC_CTRL_OSC_FREQ_MASK (3u<<30)24#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30)25#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30)26#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)27#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30)28#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK)29 30#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28)31#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28)32#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28)33#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28)34 35#define OSC_FREQ_DET 0x5836#define OSC_FREQ_DET_TRIG (1u<<31)37 38#define OSC_FREQ_DET_STATUS 0x5c39#define OSC_FREQ_DET_BUSYu (1<<31)40#define OSC_FREQ_DET_CNT_MASK 0xFFFFu41 42#define TEGRA20_CLK_PERIPH_BANKS 343 44#define PLLS_BASE 0xf045#define PLLS_MISC 0xf446#define PLLC_BASE 0x8047#define PLLC_MISC 0x8c48#define PLLM_BASE 0x9049#define PLLM_MISC 0x9c50#define PLLP_BASE 0xa051#define PLLP_MISC 0xac52#define PLLA_BASE 0xb053#define PLLA_MISC 0xbc54#define PLLU_BASE 0xc055#define PLLU_MISC 0xcc56#define PLLD_BASE 0xd057#define PLLD_MISC 0xdc58#define PLLX_BASE 0xe059#define PLLX_MISC 0xe460#define PLLE_BASE 0xe861#define PLLE_MISC 0xec62 63#define PLL_BASE_LOCK BIT(27)64#define PLLE_MISC_LOCK BIT(11)65 66#define PLL_MISC_LOCK_ENABLE 1867#define PLLDU_MISC_LOCK_ENABLE 2268#define PLLE_MISC_LOCK_ENABLE 969 70#define PLLC_OUT 0x8471#define PLLM_OUT 0x9472#define PLLP_OUTA 0xa473#define PLLP_OUTB 0xa874#define PLLA_OUT 0xb475 76#define CCLK_BURST_POLICY 0x2077#define SUPER_CCLK_DIVIDER 0x2478#define SCLK_BURST_POLICY 0x2879#define SUPER_SCLK_DIVIDER 0x2c80#define CLK_SYSTEM_RATE 0x3081 82#define CCLK_BURST_POLICY_SHIFT 2883#define CCLK_RUN_POLICY_SHIFT 484#define CCLK_IDLE_POLICY_SHIFT 085#define CCLK_IDLE_POLICY 186#define CCLK_RUN_POLICY 287#define CCLK_BURST_POLICY_PLLX 888 89#define CLK_SOURCE_I2S1 0x10090#define CLK_SOURCE_I2S2 0x10491#define CLK_SOURCE_PWM 0x11092#define CLK_SOURCE_SPI 0x11493#define CLK_SOURCE_XIO 0x12094#define CLK_SOURCE_TWC 0x12c95#define CLK_SOURCE_IDE 0x14496#define CLK_SOURCE_HDMI 0x18c97#define CLK_SOURCE_DISP1 0x13898#define CLK_SOURCE_DISP2 0x13c99#define CLK_SOURCE_CSITE 0x1d4100#define CLK_SOURCE_I2C1 0x124101#define CLK_SOURCE_I2C2 0x198102#define CLK_SOURCE_I2C3 0x1b8103#define CLK_SOURCE_DVC 0x128104#define CLK_SOURCE_UARTA 0x178105#define CLK_SOURCE_UARTB 0x17c106#define CLK_SOURCE_UARTC 0x1a0107#define CLK_SOURCE_UARTD 0x1c0108#define CLK_SOURCE_UARTE 0x1c4109#define CLK_SOURCE_EMC 0x19c110 111#define AUDIO_SYNC_CLK 0x38112 113/* Tegra CPU clock and reset control regs */114#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c115#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340116#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344117 118#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))119#define CPU_RESET(cpu) (0x1111ul << (cpu))120 121#ifdef CONFIG_PM_SLEEP122static struct cpu_clk_suspend_context {123 u32 pllx_misc;124 u32 pllx_base;125 126 u32 cpu_burst;127 u32 clk_csite_src;128 u32 cclk_divider;129} tegra20_cpu_clk_sctx;130#endif131 132static void __iomem *clk_base;133static void __iomem *pmc_base;134 135#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \136 _clk_num, _gate_flags, _clk_id) \137 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \138 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \139 _clk_num, \140 _gate_flags, _clk_id)141 142#define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \143 _clk_num, _gate_flags, _clk_id) \144 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \145 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \146 _clk_num, _gate_flags, \147 _clk_id)148 149#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \150 _mux_shift, _mux_width, _clk_num, \151 _gate_flags, _clk_id) \152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \153 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \154 _clk_num, _gate_flags, \155 _clk_id)156 157static struct clk **clks;158 159static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {160 { 12000000, 600000000, 600, 12, 1, 8 },161 { 13000000, 600000000, 600, 13, 1, 8 },162 { 19200000, 600000000, 500, 16, 1, 6 },163 { 26000000, 600000000, 600, 26, 1, 8 },164 { 0, 0, 0, 0, 0, 0 },165};166 167static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {168 { 12000000, 666000000, 666, 12, 1, 8 },169 { 13000000, 666000000, 666, 13, 1, 8 },170 { 19200000, 666000000, 555, 16, 1, 8 },171 { 26000000, 666000000, 666, 26, 1, 8 },172 { 12000000, 600000000, 600, 12, 1, 8 },173 { 13000000, 600000000, 600, 13, 1, 8 },174 { 19200000, 600000000, 375, 12, 1, 6 },175 { 26000000, 600000000, 600, 26, 1, 8 },176 { 0, 0, 0, 0, 0, 0 },177};178 179static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {180 { 12000000, 216000000, 432, 12, 2, 8 },181 { 13000000, 216000000, 432, 13, 2, 8 },182 { 19200000, 216000000, 90, 4, 2, 1 },183 { 26000000, 216000000, 432, 26, 2, 8 },184 { 12000000, 432000000, 432, 12, 1, 8 },185 { 13000000, 432000000, 432, 13, 1, 8 },186 { 19200000, 432000000, 90, 4, 1, 1 },187 { 26000000, 432000000, 432, 26, 1, 8 },188 { 0, 0, 0, 0, 0, 0 },189};190 191static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {192 { 28800000, 56448000, 49, 25, 1, 1 },193 { 28800000, 73728000, 64, 25, 1, 1 },194 { 28800000, 24000000, 5, 6, 1, 1 },195 { 0, 0, 0, 0, 0, 0 },196};197 198static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {199 { 12000000, 216000000, 216, 12, 1, 4 },200 { 13000000, 216000000, 216, 13, 1, 4 },201 { 19200000, 216000000, 135, 12, 1, 3 },202 { 26000000, 216000000, 216, 26, 1, 4 },203 { 12000000, 594000000, 594, 12, 1, 8 },204 { 13000000, 594000000, 594, 13, 1, 8 },205 { 19200000, 594000000, 495, 16, 1, 8 },206 { 26000000, 594000000, 594, 26, 1, 8 },207 { 12000000, 1000000000, 1000, 12, 1, 12 },208 { 13000000, 1000000000, 1000, 13, 1, 12 },209 { 19200000, 1000000000, 625, 12, 1, 8 },210 { 26000000, 1000000000, 1000, 26, 1, 12 },211 { 0, 0, 0, 0, 0, 0 },212};213 214static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {215 { 12000000, 480000000, 960, 12, 1, 0 },216 { 13000000, 480000000, 960, 13, 1, 0 },217 { 19200000, 480000000, 200, 4, 1, 0 },218 { 26000000, 480000000, 960, 26, 1, 0 },219 { 0, 0, 0, 0, 0, 0 },220};221 222static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {223 /* 1 GHz */224 { 12000000, 1000000000, 1000, 12, 1, 12 },225 { 13000000, 1000000000, 1000, 13, 1, 12 },226 { 19200000, 1000000000, 625, 12, 1, 8 },227 { 26000000, 1000000000, 1000, 26, 1, 12 },228 /* 912 MHz */229 { 12000000, 912000000, 912, 12, 1, 12 },230 { 13000000, 912000000, 912, 13, 1, 12 },231 { 19200000, 912000000, 760, 16, 1, 8 },232 { 26000000, 912000000, 912, 26, 1, 12 },233 /* 816 MHz */234 { 12000000, 816000000, 816, 12, 1, 12 },235 { 13000000, 816000000, 816, 13, 1, 12 },236 { 19200000, 816000000, 680, 16, 1, 8 },237 { 26000000, 816000000, 816, 26, 1, 12 },238 /* 760 MHz */239 { 12000000, 760000000, 760, 12, 1, 12 },240 { 13000000, 760000000, 760, 13, 1, 12 },241 { 19200000, 760000000, 950, 24, 1, 8 },242 { 26000000, 760000000, 760, 26, 1, 12 },243 /* 750 MHz */244 { 12000000, 750000000, 750, 12, 1, 12 },245 { 13000000, 750000000, 750, 13, 1, 12 },246 { 19200000, 750000000, 625, 16, 1, 8 },247 { 26000000, 750000000, 750, 26, 1, 12 },248 /* 608 MHz */249 { 12000000, 608000000, 608, 12, 1, 12 },250 { 13000000, 608000000, 608, 13, 1, 12 },251 { 19200000, 608000000, 380, 12, 1, 8 },252 { 26000000, 608000000, 608, 26, 1, 12 },253 /* 456 MHz */254 { 12000000, 456000000, 456, 12, 1, 12 },255 { 13000000, 456000000, 456, 13, 1, 12 },256 { 19200000, 456000000, 380, 16, 1, 8 },257 { 26000000, 456000000, 456, 26, 1, 12 },258 /* 312 MHz */259 { 12000000, 312000000, 312, 12, 1, 12 },260 { 13000000, 312000000, 312, 13, 1, 12 },261 { 19200000, 312000000, 260, 16, 1, 8 },262 { 26000000, 312000000, 312, 26, 1, 12 },263 { 0, 0, 0, 0, 0, 0 },264};265 266static const struct pdiv_map plle_p[] = {267 { .pdiv = 1, .hw_val = 1 },268 { .pdiv = 0, .hw_val = 0 },269};270 271static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {272 { 12000000, 100000000, 200, 24, 1, 0 },273 { 0, 0, 0, 0, 0, 0 },274};275 276/* PLL parameters */277static struct tegra_clk_pll_params pll_c_params = {278 .input_min = 2000000,279 .input_max = 31000000,280 .cf_min = 1000000,281 .cf_max = 6000000,282 .vco_min = 20000000,283 .vco_max = 1400000000,284 .base_reg = PLLC_BASE,285 .misc_reg = PLLC_MISC,286 .lock_mask = PLL_BASE_LOCK,287 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,288 .lock_delay = 300,289 .freq_table = pll_c_freq_table,290 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,291};292 293static struct tegra_clk_pll_params pll_m_params = {294 .input_min = 2000000,295 .input_max = 31000000,296 .cf_min = 1000000,297 .cf_max = 6000000,298 .vco_min = 20000000,299 .vco_max = 1200000000,300 .base_reg = PLLM_BASE,301 .misc_reg = PLLM_MISC,302 .lock_mask = PLL_BASE_LOCK,303 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,304 .lock_delay = 300,305 .freq_table = pll_m_freq_table,306 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,307};308 309static struct tegra_clk_pll_params pll_p_params = {310 .input_min = 2000000,311 .input_max = 31000000,312 .cf_min = 1000000,313 .cf_max = 6000000,314 .vco_min = 20000000,315 .vco_max = 1400000000,316 .base_reg = PLLP_BASE,317 .misc_reg = PLLP_MISC,318 .lock_mask = PLL_BASE_LOCK,319 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,320 .lock_delay = 300,321 .freq_table = pll_p_freq_table,322 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |323 TEGRA_PLL_HAS_LOCK_ENABLE,324 .fixed_rate = 216000000,325};326 327static struct tegra_clk_pll_params pll_a_params = {328 .input_min = 2000000,329 .input_max = 31000000,330 .cf_min = 1000000,331 .cf_max = 6000000,332 .vco_min = 20000000,333 .vco_max = 1400000000,334 .base_reg = PLLA_BASE,335 .misc_reg = PLLA_MISC,336 .lock_mask = PLL_BASE_LOCK,337 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,338 .lock_delay = 300,339 .freq_table = pll_a_freq_table,340 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,341};342 343static struct tegra_clk_pll_params pll_d_params = {344 .input_min = 2000000,345 .input_max = 40000000,346 .cf_min = 1000000,347 .cf_max = 6000000,348 .vco_min = 40000000,349 .vco_max = 1000000000,350 .base_reg = PLLD_BASE,351 .misc_reg = PLLD_MISC,352 .lock_mask = PLL_BASE_LOCK,353 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,354 .lock_delay = 1000,355 .freq_table = pll_d_freq_table,356 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,357};358 359static const struct pdiv_map pllu_p[] = {360 { .pdiv = 1, .hw_val = 1 },361 { .pdiv = 2, .hw_val = 0 },362 { .pdiv = 0, .hw_val = 0 },363};364 365static struct tegra_clk_pll_params pll_u_params = {366 .input_min = 2000000,367 .input_max = 40000000,368 .cf_min = 1000000,369 .cf_max = 6000000,370 .vco_min = 48000000,371 .vco_max = 960000000,372 .base_reg = PLLU_BASE,373 .misc_reg = PLLU_MISC,374 .lock_mask = PLL_BASE_LOCK,375 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,376 .lock_delay = 1000,377 .pdiv_tohw = pllu_p,378 .freq_table = pll_u_freq_table,379 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,380};381 382static struct tegra_clk_pll_params pll_x_params = {383 .input_min = 2000000,384 .input_max = 31000000,385 .cf_min = 1000000,386 .cf_max = 6000000,387 .vco_min = 20000000,388 .vco_max = 1200000000,389 .base_reg = PLLX_BASE,390 .misc_reg = PLLX_MISC,391 .lock_mask = PLL_BASE_LOCK,392 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,393 .lock_delay = 300,394 .freq_table = pll_x_freq_table,395 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,396 .pre_rate_change = tegra_cclk_pre_pllx_rate_change,397 .post_rate_change = tegra_cclk_post_pllx_rate_change,398};399 400static struct tegra_clk_pll_params pll_e_params = {401 .input_min = 12000000,402 .input_max = 12000000,403 .cf_min = 0,404 .cf_max = 0,405 .vco_min = 0,406 .vco_max = 0,407 .base_reg = PLLE_BASE,408 .misc_reg = PLLE_MISC,409 .lock_mask = PLLE_MISC_LOCK,410 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,411 .lock_delay = 0,412 .pdiv_tohw = plle_p,413 .freq_table = pll_e_freq_table,414 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |415 TEGRA_PLL_HAS_LOCK_ENABLE,416 .fixed_rate = 100000000,417};418 419static struct tegra_devclk devclks[] = {420 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },421 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },422 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },423 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },424 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },425 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },426 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },427 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },428 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },429 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },430 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },431 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },432 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },433 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },434 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },435 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },436 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },437 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },438 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },439 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },440 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },441 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },442 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },443 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },447 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },449 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },450 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },451 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },452 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },453 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },454 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },455 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },456 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },457 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },458 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },459 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },460 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },461 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },462 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },463 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },464 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },465 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },466 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },467 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },468 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },469 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },470 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },471 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },472 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },473 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },474 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },475 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },476 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },477 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },478 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },479 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },480 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },481 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },482 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },483 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },484 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },485 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },486 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },487 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },488 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },489 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },490 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },491 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },492 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },493 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },494 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },495 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },496 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },497 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },498 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },499 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },500 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },501 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },502 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },503 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },504 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },505 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },506 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },507 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },508 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },509 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },510 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },511 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },512 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },513 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },514};515 516static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {517 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },518 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },519 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },520 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },521 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },522 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },523 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },524 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },525 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },526 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },527 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },528 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },529 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },530 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },531 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },532 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },533 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },534 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },535 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },536 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },537 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },538 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },539 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },540 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },541 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },542 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },543 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },544 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },545 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },546 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },547 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },548 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },549 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },550 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },551 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },552 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },553 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },554 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },555 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },556 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },557 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },558 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },559 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },560 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },561 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },562 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },563 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },564 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },565 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },566 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },567 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },568 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },569 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },570};571 572static unsigned long tegra20_clk_measure_input_freq(void)573{574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);575 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;576 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;577 unsigned long input_freq;578 579 switch (auto_clk_control) {580 case OSC_CTRL_OSC_FREQ_12MHZ:581 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);582 input_freq = 12000000;583 break;584 case OSC_CTRL_OSC_FREQ_13MHZ:585 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);586 input_freq = 13000000;587 break;588 case OSC_CTRL_OSC_FREQ_19_2MHZ:589 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);590 input_freq = 19200000;591 break;592 case OSC_CTRL_OSC_FREQ_26MHZ:593 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);594 input_freq = 26000000;595 break;596 default:597 pr_err("Unexpected clock autodetect value %d",598 auto_clk_control);599 BUG();600 return 0;601 }602 603 return input_freq;604}605 606static unsigned int tegra20_get_pll_ref_div(void)607{608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &609 OSC_CTRL_PLL_REF_DIV_MASK;610 611 switch (pll_ref_div) {612 case OSC_CTRL_PLL_REF_DIV_1:613 return 1;614 case OSC_CTRL_PLL_REF_DIV_2:615 return 2;616 case OSC_CTRL_PLL_REF_DIV_4:617 return 4;618 default:619 pr_err("Invalid pll ref divider %d\n", pll_ref_div);620 BUG();621 }622 return 0;623}624 625static void tegra20_pll_init(void)626{627 struct clk *clk;628 629 /* PLLC */630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,631 &pll_c_params, NULL);632 clks[TEGRA20_CLK_PLL_C] = clk;633 634 /* PLLC_OUT1 */635 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,637 8, 8, 1, NULL);638 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,640 0, NULL);641 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;642 643 /* PLLM */644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,645 CLK_SET_RATE_GATE, &pll_m_params, NULL);646 clks[TEGRA20_CLK_PLL_M] = clk;647 648 /* PLLM_OUT1 */649 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,651 8, 8, 1, NULL);652 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",653 clk_base + PLLM_OUT, 1, 0,654 CLK_SET_RATE_PARENT, 0, NULL);655 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;656 657 /* PLLX */658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,659 &pll_x_params, NULL);660 clks[TEGRA20_CLK_PLL_X] = clk;661 662 /* PLLU */663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,664 &pll_u_params, NULL);665 clks[TEGRA20_CLK_PLL_U] = clk;666 667 /* PLLD */668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,669 &pll_d_params, NULL);670 clks[TEGRA20_CLK_PLL_D] = clk;671 672 /* PLLD_OUT0 */673 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",674 CLK_SET_RATE_PARENT, 1, 2);675 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;676 677 /* PLLA */678 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,679 &pll_a_params, NULL);680 clks[TEGRA20_CLK_PLL_A] = clk;681 682 /* PLLA_OUT0 */683 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",684 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,685 8, 8, 1, NULL);686 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",687 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |688 CLK_SET_RATE_PARENT, 0, NULL);689 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;690 691 /* PLLE */692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,693 0, &pll_e_params, NULL);694 clks[TEGRA20_CLK_PLL_E] = clk;695}696 697static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",698 "pll_p", "pll_p_out4",699 "pll_p_out3", "clk_d", "pll_x" };700static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",701 "pll_p_out3", "pll_p_out2", "clk_d",702 "clk_32k", "pll_m_out1" };703 704static void tegra20_super_clk_init(void)705{706 struct clk *clk;707 708 /* CCLK */709 clk = tegra_clk_register_super_cclk("cclk", cclk_parents,710 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,711 clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,712 NULL);713 clks[TEGRA20_CLK_CCLK] = clk;714 715 /* twd */716 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);717 clks[TEGRA20_CLK_TWD] = clk;718}719 720static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",721 "pll_a_out0", "unused", "unused",722 "unused" };723 724static void __init tegra20_audio_clk_init(void)725{726 struct clk *clk;727 728 /* audio */729 clk = clk_register_mux(NULL, "audio_mux", audio_parents,730 ARRAY_SIZE(audio_parents),731 CLK_SET_RATE_NO_REPARENT,732 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);733 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,734 clk_base + AUDIO_SYNC_CLK, 4,735 CLK_GATE_SET_TO_DISABLE, NULL);736 clks[TEGRA20_CLK_AUDIO] = clk;737 738 /* audio_2x */739 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",740 CLK_SET_RATE_PARENT, 2, 1);741 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",742 TEGRA_PERIPH_NO_RESET, clk_base,743 CLK_SET_RATE_PARENT, 89,744 periph_clk_enb_refcnt);745 clks[TEGRA20_CLK_AUDIO_2X] = clk;746}747 748static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",749 "clk_m" };750static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",751 "clk_m" };752static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",753 "clk_32k" };754static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };755static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",756 "clk_m" };757 758static struct tegra_periph_init_data tegra_periph_clk_list[] = {759 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),760 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),761 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),762 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),763 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),764 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),765 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),766 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),767 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),768 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),769 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),770 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),771};772 773static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {774 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),775 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),776 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),777 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),778 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),779 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),780 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),781};782 783static void __init tegra20_periph_clk_init(void)784{785 struct tegra_periph_init_data *data;786 struct clk *clk;787 unsigned int i;788 789 /* ac97 */790 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",791 TEGRA_PERIPH_ON_APB,792 clk_base, 0, 3, periph_clk_enb_refcnt);793 clks[TEGRA20_CLK_AC97] = clk;794 795 /* emc */796 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);797 798 clks[TEGRA20_CLK_EMC] = clk;799 800 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,801 NULL);802 clks[TEGRA20_CLK_MC] = clk;803 804 /* dsi */805 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,806 48, periph_clk_enb_refcnt);807 clk_register_clkdev(clk, NULL, "dsi");808 clks[TEGRA20_CLK_DSI] = clk;809 810 /* pex */811 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,812 periph_clk_enb_refcnt);813 clks[TEGRA20_CLK_PEX] = clk;814 815 /* dev1 OSC divider */816 clk_register_divider(NULL, "dev1_osc_div", "clk_m",817 0, clk_base + MISC_CLK_ENB, 22, 2,818 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,819 NULL);820 821 /* dev2 OSC divider */822 clk_register_divider(NULL, "dev2_osc_div", "clk_m",823 0, clk_base + MISC_CLK_ENB, 20, 2,824 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,825 NULL);826 827 /* cdev1 */828 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,829 clk_base, 0, 94, periph_clk_enb_refcnt);830 clks[TEGRA20_CLK_CDEV1] = clk;831 832 /* cdev2 */833 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,834 clk_base, 0, 93, periph_clk_enb_refcnt);835 clks[TEGRA20_CLK_CDEV2] = clk;836 837 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {838 data = &tegra_periph_clk_list[i];839 clk = tegra_clk_register_periph_data(clk_base, data);840 clks[data->clk_id] = clk;841 }842 843 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {844 data = &tegra_periph_nodiv_clk_list[i];845 clk = tegra_clk_register_periph_nodiv(data->name,846 data->p.parent_names,847 data->num_parents, &data->periph,848 clk_base, data->offset);849 clks[data->clk_id] = clk;850 }851 852 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);853}854 855static void __init tegra20_osc_clk_init(void)856{857 struct clk *clk;858 unsigned long input_freq;859 unsigned int pll_ref_div;860 861 input_freq = tegra20_clk_measure_input_freq();862 863 /* clk_m */864 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,865 input_freq);866 clks[TEGRA20_CLK_CLK_M] = clk;867 868 /* pll_ref */869 pll_ref_div = tegra20_get_pll_ref_div();870 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",871 CLK_SET_RATE_PARENT, 1, pll_ref_div);872 clks[TEGRA20_CLK_PLL_REF] = clk;873}874 875/* Tegra20 CPU clock and reset control functions */876static void tegra20_wait_cpu_in_reset(u32 cpu)877{878 unsigned int reg;879 880 do {881 reg = readl(clk_base +882 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);883 cpu_relax();884 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */885 886 return;887}888 889static void tegra20_put_cpu_in_reset(u32 cpu)890{891 writel(CPU_RESET(cpu),892 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);893 dmb();894}895 896static void tegra20_cpu_out_of_reset(u32 cpu)897{898 writel(CPU_RESET(cpu),899 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);900 wmb();901}902 903static void tegra20_enable_cpu_clock(u32 cpu)904{905 unsigned int reg;906 907 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);908 writel(reg & ~CPU_CLOCK(cpu),909 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);910 barrier();911 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);912}913 914static void tegra20_disable_cpu_clock(u32 cpu)915{916 unsigned int reg;917 918 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);919 writel(reg | CPU_CLOCK(cpu),920 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);921}922 923#ifdef CONFIG_PM_SLEEP924static bool tegra20_cpu_rail_off_ready(void)925{926 unsigned int cpu_rst_status;927 928 cpu_rst_status = readl(clk_base +929 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);930 931 return !!(cpu_rst_status & 0x2);932}933 934static void tegra20_cpu_clock_suspend(void)935{936 /* switch coresite to clk_m, save off original source */937 tegra20_cpu_clk_sctx.clk_csite_src =938 readl(clk_base + CLK_SOURCE_CSITE);939 writel(3<<30, clk_base + CLK_SOURCE_CSITE);940 941 tegra20_cpu_clk_sctx.cpu_burst =942 readl(clk_base + CCLK_BURST_POLICY);943 tegra20_cpu_clk_sctx.pllx_base =944 readl(clk_base + PLLX_BASE);945 tegra20_cpu_clk_sctx.pllx_misc =946 readl(clk_base + PLLX_MISC);947 tegra20_cpu_clk_sctx.cclk_divider =948 readl(clk_base + SUPER_CCLK_DIVIDER);949}950 951static void tegra20_cpu_clock_resume(void)952{953 unsigned int reg, policy;954 u32 misc, base;955 956 /* Is CPU complex already running on PLLX? */957 reg = readl(clk_base + CCLK_BURST_POLICY);958 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;959 960 if (policy == CCLK_IDLE_POLICY)961 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;962 else if (policy == CCLK_RUN_POLICY)963 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;964 else965 BUG();966 967 if (reg != CCLK_BURST_POLICY_PLLX) {968 misc = readl_relaxed(clk_base + PLLX_MISC);969 base = readl_relaxed(clk_base + PLLX_BASE);970 971 if (misc != tegra20_cpu_clk_sctx.pllx_misc ||972 base != tegra20_cpu_clk_sctx.pllx_base) {973 /* restore PLLX settings if CPU is on different PLL */974 writel(tegra20_cpu_clk_sctx.pllx_misc,975 clk_base + PLLX_MISC);976 writel(tegra20_cpu_clk_sctx.pllx_base,977 clk_base + PLLX_BASE);978 979 /* wait for PLL stabilization if PLLX was enabled */980 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))981 udelay(300);982 }983 }984 985 /*986 * Restore original burst policy setting for calls resulting from CPU987 * LP2 in idle or system suspend.988 */989 writel(tegra20_cpu_clk_sctx.cclk_divider,990 clk_base + SUPER_CCLK_DIVIDER);991 writel(tegra20_cpu_clk_sctx.cpu_burst,992 clk_base + CCLK_BURST_POLICY);993 994 writel(tegra20_cpu_clk_sctx.clk_csite_src,995 clk_base + CLK_SOURCE_CSITE);996}997#endif998 999static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {1000 .wait_for_reset = tegra20_wait_cpu_in_reset,1001 .put_in_reset = tegra20_put_cpu_in_reset,1002 .out_of_reset = tegra20_cpu_out_of_reset,1003 .enable_clock = tegra20_enable_cpu_clock,1004 .disable_clock = tegra20_disable_cpu_clock,1005#ifdef CONFIG_PM_SLEEP1006 .rail_off_ready = tegra20_cpu_rail_off_ready,1007 .suspend = tegra20_cpu_clock_suspend,1008 .resume = tegra20_cpu_clock_resume,1009#endif1010};1011 1012static struct tegra_clk_init_table init_table[] = {1013 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },1014 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },1015 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },1016 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },1017 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },1018 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },1019 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 },1020 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 },1021 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 },1022 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },1023 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },1024 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },1025 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },1026 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },1027 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },1028 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },1029 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },1030 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },1031 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },1032 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },1033 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },1034 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },1035 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },1036 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },1037 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },1038 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },1039 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },1040 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },1041 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },1042 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },1043 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },1044 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },1045 { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },1046 { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },1047 /* must be the last entry */1048 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },1049};1050 1051/*1052 * Some clocks may be used by different drivers depending on the board1053 * configuration. List those here to register them twice in the clock lookup1054 * table under two names.1055 */1056static struct tegra_clk_duplicate tegra_clk_duplicates[] = {1057 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),1058 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),1059 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),1060 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),1061 /* must be the last entry */1062 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),1063};1064 1065static const struct of_device_id pmc_match[] __initconst = {1066 { .compatible = "nvidia,tegra20-pmc" },1067 { },1068};1069 1070static bool tegra20_car_initialized;1071 1072static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,1073 void *data)1074{1075 struct clk_hw *parent_hw;1076 struct clk_hw *hw;1077 struct clk *clk;1078 1079 /*1080 * Timer clocks are needed early, the rest of the clocks shouldn't be1081 * available to device drivers until clock tree is fully initialized.1082 */1083 if (clkspec->args[0] != TEGRA20_CLK_RTC &&1084 clkspec->args[0] != TEGRA20_CLK_TWD &&1085 clkspec->args[0] != TEGRA20_CLK_TIMER &&1086 !tegra20_car_initialized)1087 return ERR_PTR(-EPROBE_DEFER);1088 1089 clk = of_clk_src_onecell_get(clkspec, data);1090 if (IS_ERR(clk))1091 return clk;1092 1093 hw = __clk_get_hw(clk);1094 1095 /*1096 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent1097 * clock is created by the pinctrl driver. It is possible for clk user1098 * to request these clocks before pinctrl driver got probed and hence1099 * user will get an orphaned clock. That might be undesirable because1100 * user may expect parent clock to be enabled by the child.1101 */1102 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||1103 clkspec->args[0] == TEGRA20_CLK_CDEV2) {1104 parent_hw = clk_hw_get_parent(hw);1105 if (!parent_hw)1106 return ERR_PTR(-EPROBE_DEFER);1107 }1108 1109 if (clkspec->args[0] == TEGRA20_CLK_EMC) {1110 if (!tegra20_clk_emc_driver_available(hw))1111 return ERR_PTR(-EPROBE_DEFER);1112 }1113 1114 return clk;1115}1116 1117static void __init tegra20_clock_init(struct device_node *np)1118{1119 struct device_node *node;1120 1121 clk_base = of_iomap(np, 0);1122 if (!clk_base) {1123 pr_err("Can't map CAR registers\n");1124 BUG();1125 }1126 1127 node = of_find_matching_node(NULL, pmc_match);1128 if (!node) {1129 pr_err("Failed to find pmc node\n");1130 BUG();1131 }1132 1133 pmc_base = of_iomap(node, 0);1134 of_node_put(node);1135 if (!pmc_base) {1136 pr_err("Can't map pmc registers\n");1137 BUG();1138 }1139 1140 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,1141 TEGRA20_CLK_PERIPH_BANKS);1142 if (!clks)1143 return;1144 1145 tegra20_osc_clk_init();1146 tegra_fixed_clk_init(tegra20_clks);1147 tegra20_pll_init();1148 tegra20_super_clk_init();1149 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);1150 tegra20_periph_clk_init();1151 tegra20_audio_clk_init();1152 1153 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);1154 1155 tegra_add_of_provider(np, tegra20_clk_src_onecell_get);1156 1157 tegra_cpu_car_ops = &tegra20_cpu_car_ops;1158}1159CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);1160 1161/*1162 * Clocks that use runtime PM can't be created at the tegra20_clock_init1163 * time because drivers' base isn't initialized yet, and thus platform1164 * devices can't be created for the clocks. Hence we need to split the1165 * registration of the clocks into two phases. The first phase registers1166 * essential clocks which don't require RPM and are actually used during1167 * early boot. The second phase registers clocks which use RPM and this1168 * is done when device drivers' core API is ready.1169 */1170static int tegra20_car_probe(struct platform_device *pdev)1171{1172 struct clk *clk;1173 1174 clk = tegra_clk_register_super_mux("sclk", sclk_parents,1175 ARRAY_SIZE(sclk_parents),1176 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,1177 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);1178 clks[TEGRA20_CLK_SCLK] = clk;1179 1180 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));1181 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);1182 tegra20_car_initialized = true;1183 1184 return 0;1185}1186 1187static const struct of_device_id tegra20_car_match[] = {1188 { .compatible = "nvidia,tegra20-car" },1189 { }1190};1191 1192static struct platform_driver tegra20_car_driver = {1193 .driver = {1194 .name = "tegra20-car",1195 .of_match_table = tegra20_car_match,1196 .suppress_bind_attrs = true,1197 },1198 .probe = tegra20_car_probe,1199};1200builtin_platform_driver(tegra20_car_driver);1201