brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012-2020 NVIDIA CORPORATION.  All rights reserved.4 */5 6#include <linux/io.h>7#include <linux/clk.h>8#include <linux/clk-provider.h>9#include <linux/clkdev.h>10#include <linux/of.h>11#include <linux/of_address.h>12#include <linux/syscore_ops.h>13#include <linux/delay.h>14#include <linux/export.h>15#include <linux/mutex.h>16#include <linux/clk/tegra.h>17#include <dt-bindings/clock/tegra210-car.h>18#include <dt-bindings/reset/tegra210-car.h>19#include <linux/sizes.h>20#include <soc/tegra/pmc.h>21 22#include "clk.h"23#include "clk-id.h"24 25/*26 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register27 * banks present in the Tegra210 CAR IP block.  The banks are28 * identified by single letters, e.g.: L, H, U, V, W, X, Y.  See29 * periph_regs[] in drivers/clk/tegra/clk.c30 */31#define TEGRA210_CAR_BANK_COUNT			732 33#define CLK_SOURCE_CSITE 0x1d434#define CLK_SOURCE_EMC 0x19c35#define CLK_SOURCE_SOR1 0x41036#define CLK_SOURCE_SOR0 0x41437#define CLK_SOURCE_LA 0x1f838#define CLK_SOURCE_SDMMC2 0x15439#define CLK_SOURCE_SDMMC4 0x16440#define CLK_SOURCE_EMC_DLL 0x66441 42#define PLLC_BASE 0x8043#define PLLC_OUT 0x8444#define PLLC_MISC0 0x8845#define PLLC_MISC1 0x8c46#define PLLC_MISC2 0x5d047#define PLLC_MISC3 0x5d448 49#define PLLC2_BASE 0x4e850#define PLLC2_MISC0 0x4ec51#define PLLC2_MISC1 0x4f052#define PLLC2_MISC2 0x4f453#define PLLC2_MISC3 0x4f854 55#define PLLC3_BASE 0x4fc56#define PLLC3_MISC0 0x50057#define PLLC3_MISC1 0x50458#define PLLC3_MISC2 0x50859#define PLLC3_MISC3 0x50c60 61#define PLLM_BASE 0x9062#define PLLM_MISC1 0x9863#define PLLM_MISC2 0x9c64#define PLLP_BASE 0xa065#define PLLP_MISC0 0xac66#define PLLP_MISC1 0x68067#define PLLA_BASE 0xb068#define PLLA_MISC0 0xbc69#define PLLA_MISC1 0xb870#define PLLA_MISC2 0x5d871#define PLLD_BASE 0xd072#define PLLD_MISC0 0xdc73#define PLLD_MISC1 0xd874#define PLLU_BASE 0xc075#define PLLU_OUTA 0xc476#define PLLU_MISC0 0xcc77#define PLLU_MISC1 0xc878#define PLLX_BASE 0xe079#define PLLX_MISC0 0xe480#define PLLX_MISC1 0x51081#define PLLX_MISC2 0x51482#define PLLX_MISC3 0x51883#define PLLX_MISC4 0x5f084#define PLLX_MISC5 0x5f485#define PLLE_BASE 0xe886#define PLLE_MISC0 0xec87#define PLLD2_BASE 0x4b888#define PLLD2_MISC0 0x4bc89#define PLLD2_MISC1 0x57090#define PLLD2_MISC2 0x57491#define PLLD2_MISC3 0x57892#define PLLE_AUX 0x48c93#define PLLRE_BASE 0x4c494#define PLLRE_MISC0 0x4c895#define PLLRE_OUT1 0x4cc96#define PLLDP_BASE 0x59097#define PLLDP_MISC 0x59498 99#define PLLC4_BASE 0x5a4100#define PLLC4_MISC0 0x5a8101#define PLLC4_OUT 0x5e4102#define PLLMB_BASE 0x5e8103#define PLLMB_MISC1 0x5ec104#define PLLA1_BASE 0x6a4105#define PLLA1_MISC0 0x6a8106#define PLLA1_MISC1 0x6ac107#define PLLA1_MISC2 0x6b0108#define PLLA1_MISC3 0x6b4109 110#define PLLU_IDDQ_BIT 31111#define PLLCX_IDDQ_BIT 27112#define PLLRE_IDDQ_BIT 24113#define PLLA_IDDQ_BIT 25114#define PLLD_IDDQ_BIT 20115#define PLLSS_IDDQ_BIT 18116#define PLLM_IDDQ_BIT 5117#define PLLMB_IDDQ_BIT 17118#define PLLXP_IDDQ_BIT 3119 120#define PLLCX_RESET_BIT 30121 122#define PLL_BASE_LOCK BIT(27)123#define PLLCX_BASE_LOCK BIT(26)124#define PLLE_MISC_LOCK BIT(11)125#define PLLRE_MISC_LOCK BIT(27)126 127#define PLL_MISC_LOCK_ENABLE 18128#define PLLC_MISC_LOCK_ENABLE 24129#define PLLDU_MISC_LOCK_ENABLE 22130#define PLLU_MISC_LOCK_ENABLE 29131#define PLLE_MISC_LOCK_ENABLE 9132#define PLLRE_MISC_LOCK_ENABLE 30133#define PLLSS_MISC_LOCK_ENABLE 30134#define PLLP_MISC_LOCK_ENABLE 18135#define PLLM_MISC_LOCK_ENABLE 4136#define PLLMB_MISC_LOCK_ENABLE 16137#define PLLA_MISC_LOCK_ENABLE 28138#define PLLU_MISC_LOCK_ENABLE 29139#define PLLD_MISC_LOCK_ENABLE 18140 141#define PLLA_SDM_DIN_MASK 0xffff142#define PLLA_SDM_EN_MASK BIT(26)143 144#define PLLD_SDM_EN_MASK BIT(16)145 146#define PLLD2_SDM_EN_MASK BIT(31)147#define PLLD2_SSC_EN_MASK 0148 149#define PLLDP_SS_CFG	0x598150#define PLLDP_SDM_EN_MASK BIT(31)151#define PLLDP_SSC_EN_MASK BIT(30)152#define PLLDP_SS_CTRL1	0x59c153#define PLLDP_SS_CTRL2	0x5a0154 155#define PMC_PLLM_WB0_OVERRIDE 0x1dc156#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0157 158#define UTMIP_PLL_CFG2 0x488159#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)160#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)161#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)162#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)163#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)164#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)165#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)166#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)167#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)168#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)169 170#define UTMIP_PLL_CFG1 0x484171#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)172#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)173#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)174#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)175#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)176#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)177#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)178 179#define SATA_PLL_CFG0				0x490180#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)181#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET	BIT(2)182#define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL		BIT(4)183#define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE	BIT(5)184#define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE	BIT(6)185#define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE	BIT(7)186 187#define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ		BIT(13)188#define SATA_PLL_CFG0_SEQ_ENABLE		BIT(24)189 190#define XUSBIO_PLL_CFG0				0x51c191#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)192#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL	BIT(2)193#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET	BIT(6)194#define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ	BIT(13)195#define XUSBIO_PLL_CFG0_SEQ_ENABLE		BIT(24)196 197#define UTMIPLL_HW_PWRDN_CFG0			0x52c198#define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK	BIT(31)199#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE	BIT(25)200#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE	BIT(24)201#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE	BIT(7)202#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET	BIT(6)203#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE	BIT(5)204#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL	BIT(4)205#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL	BIT(2)206#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE	BIT(1)207#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL	BIT(0)208 209#define PLLU_HW_PWRDN_CFG0			0x530210#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE	BIT(28)211#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE		BIT(24)212#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT	BIT(7)213#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET		BIT(6)214#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL	BIT(2)215#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL	BIT(0)216 217#define XUSB_PLL_CFG0				0x534218#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY		0x3ff219#define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK	(0x3ff << 14)220 221#define SPARE_REG0 0x55c222#define CLK_M_DIVISOR_SHIFT 2223#define CLK_M_DIVISOR_MASK 0x3224 225#define CLK_MASK_ARM	0x44226#define MISC_CLK_ENB	0x48227 228#define RST_DFLL_DVCO 0x2f4229#define DVFS_DFLL_RESET_SHIFT 0230 231#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET	0x284232#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR	0x288233#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL		BIT(14)234 235#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8236#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac237#define CPU_SOFTRST_CTRL 0x380238 239#define LVL2_CLK_GATE_OVRA 0xf8240#define LVL2_CLK_GATE_OVRC 0x3a0241#define LVL2_CLK_GATE_OVRD 0x3a4242#define LVL2_CLK_GATE_OVRE 0x554243 244/* I2S registers to handle during APE MBIST WAR */245#define TEGRA210_I2S_BASE  0x1000246#define TEGRA210_I2S_SIZE  0x100247#define TEGRA210_I2S_CTRLS 5248#define TEGRA210_I2S_CG    0x88249#define TEGRA210_I2S_CTRL  0xa0250 251/* DISPA registers to handle during MBIST WAR */252#define DC_CMD_DISPLAY_COMMAND 0xc8253#define DC_COM_DSC_TOP_CTL 0xcf8254 255/* VIC register to handle during MBIST WAR */256#define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c257 258/* APE, DISPA and VIC base addesses needed for MBIST WAR */259#define TEGRA210_AHUB_BASE  0x702d0000260#define TEGRA210_DISPA_BASE 0x54200000261#define TEGRA210_VIC_BASE  0x54340000262 263/*264 * SDM fractional divisor is 16-bit 2's complement signed number within265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to267 * indicate that SDM is disabled.268 *269 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13270 */271#define PLL_SDM_COEFF BIT(13)272#define sdin_din_to_data(din)	((u16)((din) ? : 0xFFFFU))273#define sdin_data_to_din(dat)	(((dat) == 0xFFFFU) ? 0 : (s16)dat)274/* This macro returns ndiv effective scaled to SDM range */275#define sdin_get_n_eff(cfg)	((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \276		(PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))277 278/* Tegra CPU clock and reset control regs */279#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470280 281#ifdef CONFIG_PM_SLEEP282static struct cpu_clk_suspend_context {283	u32 clk_csite_src;284} tegra210_cpu_clk_sctx;285#endif286 287struct tegra210_domain_mbist_war {288	void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);289	const u32 lvl2_offset;290	const u32 lvl2_mask;291	const unsigned int num_clks;292	const unsigned int *clk_init_data;293	struct clk_bulk_data *clks;294};295 296static struct clk **clks;297 298static void __iomem *clk_base;299static void __iomem *pmc_base;300static void __iomem *ahub_base;301static void __iomem *dispa_base;302static void __iomem *vic_base;303 304static unsigned long osc_freq;305static unsigned long pll_ref_freq;306 307static DEFINE_SPINLOCK(pll_d_lock);308static DEFINE_SPINLOCK(pll_e_lock);309static DEFINE_SPINLOCK(pll_re_lock);310static DEFINE_SPINLOCK(pll_u_lock);311static DEFINE_SPINLOCK(sor0_lock);312static DEFINE_SPINLOCK(sor1_lock);313static DEFINE_SPINLOCK(emc_lock);314static DEFINE_MUTEX(lvl2_ovr_lock);315 316/* possible OSC frequencies in Hz */317static unsigned long tegra210_input_freq[] = {318	[5] = 38400000,319	[8] = 12000000,320};321 322#define PLL_ENABLE			(1 << 30)323 324#define PLLCX_MISC1_IDDQ		(1 << 27)325#define PLLCX_MISC0_RESET		(1 << 30)326 327#define PLLCX_MISC0_DEFAULT_VALUE	0x40080000328#define PLLCX_MISC0_WRITE_MASK		0x400ffffb329#define PLLCX_MISC1_DEFAULT_VALUE	0x08000000330#define PLLCX_MISC1_WRITE_MASK		0x08003cff331#define PLLCX_MISC2_DEFAULT_VALUE	0x1f720f05332#define PLLCX_MISC2_WRITE_MASK		0xffffff17333#define PLLCX_MISC3_DEFAULT_VALUE	0x000000c4334#define PLLCX_MISC3_WRITE_MASK		0x00ffffff335 336/* PLLA */337#define PLLA_BASE_IDDQ			(1 << 25)338#define PLLA_BASE_LOCK			(1 << 27)339 340#define PLLA_MISC0_LOCK_ENABLE		(1 << 28)341#define PLLA_MISC0_LOCK_OVERRIDE	(1 << 27)342 343#define PLLA_MISC2_EN_SDM		(1 << 26)344#define PLLA_MISC2_EN_DYNRAMP		(1 << 25)345 346#define PLLA_MISC0_DEFAULT_VALUE	0x12000020347#define PLLA_MISC0_WRITE_MASK		0x7fffffff348#define PLLA_MISC2_DEFAULT_VALUE	0x0349#define PLLA_MISC2_WRITE_MASK		0x06ffffff350 351/* PLLD */352#define PLLD_BASE_CSI_CLKSOURCE		(1 << 23)353 354#define PLLD_MISC0_EN_SDM		(1 << 16)355#define PLLD_MISC0_LOCK_OVERRIDE	(1 << 17)356#define PLLD_MISC0_LOCK_ENABLE		(1 << 18)357#define PLLD_MISC0_IDDQ			(1 << 20)358#define PLLD_MISC0_DSI_CLKENABLE	(1 << 21)359 360#define PLLD_MISC0_DEFAULT_VALUE	0x00140000361#define PLLD_MISC0_WRITE_MASK		0x3ff7ffff362#define PLLD_MISC1_DEFAULT_VALUE	0x20363#define PLLD_MISC1_WRITE_MASK		0x00ffffff364 365/* PLLD2 and PLLDP  and PLLC4 */366#define PLLDSS_BASE_LOCK		(1 << 27)367#define PLLDSS_BASE_LOCK_OVERRIDE	(1 << 24)368#define PLLDSS_BASE_IDDQ		(1 << 18)369#define PLLDSS_BASE_REF_SEL_SHIFT	25370#define PLLDSS_BASE_REF_SEL_MASK	(0x3 << PLLDSS_BASE_REF_SEL_SHIFT)371 372#define PLLDSS_MISC0_LOCK_ENABLE	(1 << 30)373 374#define PLLDSS_MISC1_CFG_EN_SDM		(1 << 31)375#define PLLDSS_MISC1_CFG_EN_SSC		(1 << 30)376 377#define PLLD2_MISC0_DEFAULT_VALUE	0x40000020378#define PLLD2_MISC1_CFG_DEFAULT_VALUE	0x10000000379#define PLLD2_MISC2_CTRL1_DEFAULT_VALUE	0x0380#define PLLD2_MISC3_CTRL2_DEFAULT_VALUE	0x0381 382#define PLLDP_MISC0_DEFAULT_VALUE	0x40000020383#define PLLDP_MISC1_CFG_DEFAULT_VALUE	0xc0000000384#define PLLDP_MISC2_CTRL1_DEFAULT_VALUE	0xf400f0da385#define PLLDP_MISC3_CTRL2_DEFAULT_VALUE	0x2004f400386 387#define PLLDSS_MISC0_WRITE_MASK		0x47ffffff388#define PLLDSS_MISC1_CFG_WRITE_MASK	0xf8000000389#define PLLDSS_MISC2_CTRL1_WRITE_MASK	0xffffffff390#define PLLDSS_MISC3_CTRL2_WRITE_MASK	0xffffffff391 392#define PLLC4_MISC0_DEFAULT_VALUE	0x40000000393 394/* PLLRE */395#define PLLRE_MISC0_LOCK_ENABLE		(1 << 30)396#define PLLRE_MISC0_LOCK_OVERRIDE	(1 << 29)397#define PLLRE_MISC0_LOCK		(1 << 27)398#define PLLRE_MISC0_IDDQ		(1 << 24)399 400#define PLLRE_BASE_DEFAULT_VALUE	0x0401#define PLLRE_MISC0_DEFAULT_VALUE	0x41000000402 403#define PLLRE_BASE_DEFAULT_MASK		0x1c000000404#define PLLRE_MISC0_WRITE_MASK		0x67ffffff405 406/* PLLE */407#define PLLE_MISC_IDDQ_SW_CTRL		(1 << 14)408#define PLLE_AUX_USE_LOCKDET		(1 << 3)409#define PLLE_AUX_SS_SEQ_INCLUDE		(1 << 31)410#define PLLE_AUX_ENABLE_SWCTL		(1 << 4)411#define PLLE_AUX_SS_SWCTL		(1 << 6)412#define PLLE_AUX_SEQ_ENABLE		(1 << 24)413 414/* PLLX */415#define PLLX_USE_DYN_RAMP		1416#define PLLX_BASE_LOCK			(1 << 27)417 418#define PLLX_MISC0_FO_G_DISABLE		(0x1 << 28)419#define PLLX_MISC0_LOCK_ENABLE		(0x1 << 18)420 421#define PLLX_MISC2_DYNRAMP_STEPB_SHIFT	24422#define PLLX_MISC2_DYNRAMP_STEPB_MASK	(0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)423#define PLLX_MISC2_DYNRAMP_STEPA_SHIFT	16424#define PLLX_MISC2_DYNRAMP_STEPA_MASK	(0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)425#define PLLX_MISC2_NDIV_NEW_SHIFT	8426#define PLLX_MISC2_NDIV_NEW_MASK	(0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)427#define PLLX_MISC2_LOCK_OVERRIDE	(0x1 << 4)428#define PLLX_MISC2_DYNRAMP_DONE		(0x1 << 2)429#define PLLX_MISC2_EN_DYNRAMP		(0x1 << 0)430 431#define PLLX_MISC3_IDDQ			(0x1 << 3)432 433#define PLLX_MISC0_DEFAULT_VALUE	PLLX_MISC0_LOCK_ENABLE434#define PLLX_MISC0_WRITE_MASK		0x10c40000435#define PLLX_MISC1_DEFAULT_VALUE	0x20436#define PLLX_MISC1_WRITE_MASK		0x00ffffff437#define PLLX_MISC2_DEFAULT_VALUE	0x0438#define PLLX_MISC2_WRITE_MASK		0xffffff11439#define PLLX_MISC3_DEFAULT_VALUE	PLLX_MISC3_IDDQ440#define PLLX_MISC3_WRITE_MASK		0x01ff0f0f441#define PLLX_MISC4_DEFAULT_VALUE	0x0442#define PLLX_MISC4_WRITE_MASK		0x8000ffff443#define PLLX_MISC5_DEFAULT_VALUE	0x0444#define PLLX_MISC5_WRITE_MASK		0x0000ffff445 446#define PLLX_HW_CTRL_CFG		0x548447#define PLLX_HW_CTRL_CFG_SWCTRL		(0x1 << 0)448 449/* PLLMB */450#define PLLMB_BASE_LOCK			(1 << 27)451 452#define PLLMB_MISC1_LOCK_OVERRIDE	(1 << 18)453#define PLLMB_MISC1_IDDQ		(1 << 17)454#define PLLMB_MISC1_LOCK_ENABLE		(1 << 16)455 456#define PLLMB_MISC1_DEFAULT_VALUE	0x00030000457#define PLLMB_MISC1_WRITE_MASK		0x0007ffff458 459/* PLLP */460#define PLLP_BASE_OVERRIDE		(1 << 28)461#define PLLP_BASE_LOCK			(1 << 27)462 463#define PLLP_MISC0_LOCK_ENABLE		(1 << 18)464#define PLLP_MISC0_LOCK_OVERRIDE	(1 << 17)465#define PLLP_MISC0_IDDQ			(1 << 3)466 467#define PLLP_MISC1_HSIO_EN_SHIFT	29468#define PLLP_MISC1_HSIO_EN		(1 << PLLP_MISC1_HSIO_EN_SHIFT)469#define PLLP_MISC1_XUSB_EN_SHIFT	28470#define PLLP_MISC1_XUSB_EN		(1 << PLLP_MISC1_XUSB_EN_SHIFT)471 472#define PLLP_MISC0_DEFAULT_VALUE	0x00040008473#define PLLP_MISC1_DEFAULT_VALUE	0x0474 475#define PLLP_MISC0_WRITE_MASK		0xdc6000f476#define PLLP_MISC1_WRITE_MASK		0x70ffffff477 478/* PLLU */479#define PLLU_BASE_LOCK			(1 << 27)480#define PLLU_BASE_OVERRIDE		(1 << 24)481#define PLLU_BASE_CLKENABLE_USB		(1 << 21)482#define PLLU_BASE_CLKENABLE_HSIC	(1 << 22)483#define PLLU_BASE_CLKENABLE_ICUSB	(1 << 23)484#define PLLU_BASE_CLKENABLE_48M		(1 << 25)485#define PLLU_BASE_CLKENABLE_ALL		(PLLU_BASE_CLKENABLE_USB |\486					 PLLU_BASE_CLKENABLE_HSIC |\487					 PLLU_BASE_CLKENABLE_ICUSB |\488					 PLLU_BASE_CLKENABLE_48M)489 490#define PLLU_MISC0_IDDQ			(1 << 31)491#define PLLU_MISC0_LOCK_ENABLE		(1 << 29)492#define PLLU_MISC1_LOCK_OVERRIDE	(1 << 0)493 494#define PLLU_MISC0_DEFAULT_VALUE	0xa0000000495#define PLLU_MISC1_DEFAULT_VALUE	0x0496 497#define PLLU_MISC0_WRITE_MASK		0xbfffffff498#define PLLU_MISC1_WRITE_MASK		0x00000007499 500bool tegra210_plle_hw_sequence_is_enabled(void)501{502	u32 value;503 504	value = readl_relaxed(clk_base + PLLE_AUX);505	if (value & PLLE_AUX_SEQ_ENABLE)506		return true;507 508	return false;509}510EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_is_enabled);511 512int tegra210_plle_hw_sequence_start(void)513{514	u32 value;515 516	if (tegra210_plle_hw_sequence_is_enabled())517		return 0;518 519	/* skip if PLLE is not enabled yet */520	value = readl_relaxed(clk_base + PLLE_MISC0);521	if (!(value & PLLE_MISC_LOCK))522		return -EIO;523 524	value &= ~PLLE_MISC_IDDQ_SW_CTRL;525	writel_relaxed(value, clk_base + PLLE_MISC0);526 527	value = readl_relaxed(clk_base + PLLE_AUX);528	value |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);529	value &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);530	writel_relaxed(value, clk_base + PLLE_AUX);531 532	fence_udelay(1, clk_base);533 534	value |= PLLE_AUX_SEQ_ENABLE;535	writel_relaxed(value, clk_base + PLLE_AUX);536 537	fence_udelay(1, clk_base);538 539	return 0;540}541EXPORT_SYMBOL_GPL(tegra210_plle_hw_sequence_start);542 543void tegra210_xusb_pll_hw_control_enable(void)544{545	u32 val;546 547	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);548	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |549		 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);550	val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |551	       XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;552	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);553}554EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);555 556void tegra210_xusb_pll_hw_sequence_start(void)557{558	u32 val;559 560	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);561	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;562	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);563}564EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);565 566void tegra210_sata_pll_hw_control_enable(void)567{568	u32 val;569 570	val = readl_relaxed(clk_base + SATA_PLL_CFG0);571	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;572	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |573	       SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;574	writel_relaxed(val, clk_base + SATA_PLL_CFG0);575}576EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);577 578void tegra210_sata_pll_hw_sequence_start(void)579{580	u32 val;581 582	val = readl_relaxed(clk_base + SATA_PLL_CFG0);583	val |= SATA_PLL_CFG0_SEQ_ENABLE;584	writel_relaxed(val, clk_base + SATA_PLL_CFG0);585}586EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);587 588void tegra210_set_sata_pll_seq_sw(bool state)589{590	u32 val;591 592	val = readl_relaxed(clk_base + SATA_PLL_CFG0);593	if (state) {594		val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;595		val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;596		val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;597		val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;598	} else {599		val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;600		val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;601		val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;602		val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;603	}604	writel_relaxed(val, clk_base + SATA_PLL_CFG0);605}606EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);607 608void tegra210_clk_emc_dll_enable(bool flag)609{610	u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET :611		     CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR;612 613	writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);614}615EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable);616 617void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value)618{619	writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);620}621EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting);622 623void tegra210_clk_emc_update_setting(u32 emc_src_value)624{625	writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);626}627EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting);628 629static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)630{631	u32 val;632 633	val = readl_relaxed(clk_base + mbist->lvl2_offset);634	writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);635	fence_udelay(1, clk_base);636	writel_relaxed(val, clk_base + mbist->lvl2_offset);637	fence_udelay(1, clk_base);638}639 640static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)641{642	u32 csi_src, ovra, ovre;643	unsigned long flags = 0;644 645	spin_lock_irqsave(&pll_d_lock, flags);646 647	csi_src = readl_relaxed(clk_base + PLLD_BASE);648	writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);649	fence_udelay(1, clk_base);650 651	ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);652	writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);653	ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);654	writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);655	fence_udelay(1, clk_base);656 657	writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);658	writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);659	writel_relaxed(csi_src, clk_base + PLLD_BASE);660	fence_udelay(1, clk_base);661 662	spin_unlock_irqrestore(&pll_d_lock, flags);663}664 665static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)666{667	u32 ovra, dsc_top_ctrl;668 669	ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);670	writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);671	fence_udelay(1, clk_base);672 673	dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);674	writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);675	readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);676	writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);677	readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);678 679	writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);680	fence_udelay(1, clk_base);681}682 683static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)684{685	u32 ovre, val;686 687	ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);688	writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);689	fence_udelay(1, clk_base);690 691	val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);692	writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),693			vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);694	fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);695 696	writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);697	readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);698 699	writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);700	fence_udelay(1, clk_base);701}702 703static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)704{705	void __iomem *i2s_base;706	unsigned int i;707	u32 ovrc, ovre;708 709	ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);710	ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);711	writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);712	writel_relaxed(ovre | BIT(10) | BIT(11),713			clk_base + LVL2_CLK_GATE_OVRE);714	fence_udelay(1, clk_base);715 716	i2s_base = ahub_base + TEGRA210_I2S_BASE;717 718	for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {719		u32 i2s_ctrl;720 721		i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);722		writel_relaxed(i2s_ctrl | BIT(10),723				i2s_base + TEGRA210_I2S_CTRL);724		writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);725		readl(i2s_base + TEGRA210_I2S_CG);726		writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);727		writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);728		readl(i2s_base + TEGRA210_I2S_CTRL);729 730		i2s_base += TEGRA210_I2S_SIZE;731	}732 733	writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);734	writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);735	fence_udelay(1, clk_base);736}737 738static inline void _pll_misc_chk_default(void __iomem *base,739					struct tegra_clk_pll_params *params,740					u8 misc_num, u32 default_val, u32 mask)741{742	u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);743 744	boot_val &= mask;745	default_val &= mask;746	if (boot_val != default_val) {747		pr_warn("boot misc%d 0x%x: expected 0x%x\n",748			misc_num, boot_val, default_val);749		pr_warn(" (comparison mask = 0x%x)\n", mask);750		params->defaults_set = false;751	}752}753 754/*755 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1756 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition757 * that changes NDIV only, while PLL is already locked.758 */759static void pllcx_check_defaults(struct tegra_clk_pll_params *params)760{761	u32 default_val;762 763	default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);764	_pll_misc_chk_default(clk_base, params, 0, default_val,765			PLLCX_MISC0_WRITE_MASK);766 767	default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);768	_pll_misc_chk_default(clk_base, params, 1, default_val,769			PLLCX_MISC1_WRITE_MASK);770 771	default_val = PLLCX_MISC2_DEFAULT_VALUE;772	_pll_misc_chk_default(clk_base, params, 2, default_val,773			PLLCX_MISC2_WRITE_MASK);774 775	default_val = PLLCX_MISC3_DEFAULT_VALUE;776	_pll_misc_chk_default(clk_base, params, 3, default_val,777			PLLCX_MISC3_WRITE_MASK);778}779 780static void tegra210_pllcx_set_defaults(const char *name,781					struct tegra_clk_pll *pllcx)782{783	pllcx->params->defaults_set = true;784 785	if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {786		/* PLL is ON: only check if defaults already set */787		pllcx_check_defaults(pllcx->params);788		if (!pllcx->params->defaults_set)789			pr_warn("%s already enabled. Postponing set full defaults\n",790				name);791		return;792	}793 794	/* Defaults assert PLL reset, and set IDDQ */795	writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,796			clk_base + pllcx->params->ext_misc_reg[0]);797	writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,798			clk_base + pllcx->params->ext_misc_reg[1]);799	writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,800			clk_base + pllcx->params->ext_misc_reg[2]);801	writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,802			clk_base + pllcx->params->ext_misc_reg[3]);803	udelay(1);804}805 806static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)807{808	tegra210_pllcx_set_defaults("PLL_C", pllcx);809}810 811static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)812{813	tegra210_pllcx_set_defaults("PLL_C2", pllcx);814}815 816static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)817{818	tegra210_pllcx_set_defaults("PLL_C3", pllcx);819}820 821static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)822{823	tegra210_pllcx_set_defaults("PLL_A1", pllcx);824}825 826/*827 * PLLA828 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.829 * Fractional SDM is allowed to provide exact audio rates.830 */831static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)832{833	u32 mask;834	u32 val = readl_relaxed(clk_base + plla->params->base_reg);835 836	plla->params->defaults_set = true;837 838	if (val & PLL_ENABLE) {839		/*840		 * PLL is ON: check if defaults already set, then set those841		 * that can be updated in flight.842		 */843		if (val & PLLA_BASE_IDDQ) {844			pr_warn("PLL_A boot enabled with IDDQ set\n");845			plla->params->defaults_set = false;846		}847 848		pr_warn("PLL_A already enabled. Postponing set full defaults\n");849 850		val = PLLA_MISC0_DEFAULT_VALUE;	/* ignore lock enable */851		mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;852		_pll_misc_chk_default(clk_base, plla->params, 0, val,853				~mask & PLLA_MISC0_WRITE_MASK);854 855		val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */856		_pll_misc_chk_default(clk_base, plla->params, 2, val,857				PLLA_MISC2_EN_DYNRAMP);858 859		/* Enable lock detect */860		val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);861		val &= ~mask;862		val |= PLLA_MISC0_DEFAULT_VALUE & mask;863		writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);864		udelay(1);865 866		return;867	}868 869	/* set IDDQ, enable lock detect, disable dynamic ramp and SDM */870	val |= PLLA_BASE_IDDQ;871	writel_relaxed(val, clk_base + plla->params->base_reg);872	writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,873			clk_base + plla->params->ext_misc_reg[0]);874	writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,875			clk_base + plla->params->ext_misc_reg[2]);876	udelay(1);877}878 879/*880 * PLLD881 * PLL with fractional SDM.882 */883static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)884{885	u32 val;886	u32 mask = 0xffff;887 888	plld->params->defaults_set = true;889 890	if (readl_relaxed(clk_base + plld->params->base_reg) &891			PLL_ENABLE) {892 893		/*894		 * PLL is ON: check if defaults already set, then set those895		 * that can be updated in flight.896		 */897		val = PLLD_MISC1_DEFAULT_VALUE;898		_pll_misc_chk_default(clk_base, plld->params, 1,899				val, PLLD_MISC1_WRITE_MASK);900 901		/* ignore lock, DSI and SDM controls, make sure IDDQ not set */902		val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);903		mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |904			PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;905		_pll_misc_chk_default(clk_base, plld->params, 0, val,906				~mask & PLLD_MISC0_WRITE_MASK);907 908		if (!plld->params->defaults_set)909			pr_warn("PLL_D already enabled. Postponing set full defaults\n");910 911		/* Enable lock detect */912		mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;913		val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);914		val &= ~mask;915		val |= PLLD_MISC0_DEFAULT_VALUE & mask;916		writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);917		udelay(1);918 919		return;920	}921 922	val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);923	val &= PLLD_MISC0_DSI_CLKENABLE;924	val |= PLLD_MISC0_DEFAULT_VALUE;925	/* set IDDQ, enable lock detect, disable SDM */926	writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);927	writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +928			plld->params->ext_misc_reg[1]);929	udelay(1);930}931 932/*933 * PLLD2, PLLDP934 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).935 */936static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,937		u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)938{939	u32 default_val;940	u32 val = readl_relaxed(clk_base + plldss->params->base_reg);941 942	plldss->params->defaults_set = true;943 944	if (val & PLL_ENABLE) {945 946		/*947		 * PLL is ON: check if defaults already set, then set those948		 * that can be updated in flight.949		 */950		if (val & PLLDSS_BASE_IDDQ) {951			pr_warn("plldss boot enabled with IDDQ set\n");952			plldss->params->defaults_set = false;953		}954 955		/* ignore lock enable */956		default_val = misc0_val;957		_pll_misc_chk_default(clk_base, plldss->params, 0, default_val,958				     PLLDSS_MISC0_WRITE_MASK &959				     (~PLLDSS_MISC0_LOCK_ENABLE));960 961		/*962		 * If SSC is used, check all settings, otherwise just confirm963		 * that SSC is not used on boot as well. Do nothing when using964		 * this function for PLLC4 that has only MISC0.965		 */966		if (plldss->params->ssc_ctrl_en_mask) {967			default_val = misc1_val;968			_pll_misc_chk_default(clk_base, plldss->params, 1,969				default_val, PLLDSS_MISC1_CFG_WRITE_MASK);970			default_val = misc2_val;971			_pll_misc_chk_default(clk_base, plldss->params, 2,972				default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);973			default_val = misc3_val;974			_pll_misc_chk_default(clk_base, plldss->params, 3,975				default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);976		} else if (plldss->params->ext_misc_reg[1]) {977			default_val = misc1_val;978			_pll_misc_chk_default(clk_base, plldss->params, 1,979				default_val, PLLDSS_MISC1_CFG_WRITE_MASK &980				(~PLLDSS_MISC1_CFG_EN_SDM));981		}982 983		if (!plldss->params->defaults_set)984			pr_warn("%s already enabled. Postponing set full defaults\n",985				 pll_name);986 987		/* Enable lock detect */988		if (val & PLLDSS_BASE_LOCK_OVERRIDE) {989			val &= ~PLLDSS_BASE_LOCK_OVERRIDE;990			writel_relaxed(val, clk_base +991					plldss->params->base_reg);992		}993 994		val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);995		val &= ~PLLDSS_MISC0_LOCK_ENABLE;996		val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;997		writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);998		udelay(1);999 1000		return;1001	}1002 1003	/* set IDDQ, enable lock detect, configure SDM/SSC  */1004	val |= PLLDSS_BASE_IDDQ;1005	val &= ~PLLDSS_BASE_LOCK_OVERRIDE;1006	writel_relaxed(val, clk_base + plldss->params->base_reg);1007 1008	/* When using this function for PLLC4 exit here */1009	if (!plldss->params->ext_misc_reg[1]) {1010		writel_relaxed(misc0_val, clk_base +1011				plldss->params->ext_misc_reg[0]);1012		udelay(1);1013		return;1014	}1015 1016	writel_relaxed(misc0_val, clk_base +1017			plldss->params->ext_misc_reg[0]);1018	/* if SSC used set by 1st enable */1019	writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),1020			clk_base + plldss->params->ext_misc_reg[1]);1021	writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);1022	writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);1023	udelay(1);1024}1025 1026static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)1027{1028	plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,1029			PLLD2_MISC1_CFG_DEFAULT_VALUE,1030			PLLD2_MISC2_CTRL1_DEFAULT_VALUE,1031			PLLD2_MISC3_CTRL2_DEFAULT_VALUE);1032}1033 1034static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)1035{1036	plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,1037			PLLDP_MISC1_CFG_DEFAULT_VALUE,1038			PLLDP_MISC2_CTRL1_DEFAULT_VALUE,1039			PLLDP_MISC3_CTRL2_DEFAULT_VALUE);1040}1041 1042/*1043 * PLLC41044 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.1045 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.1046 */1047static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)1048{1049	plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);1050}1051 1052/*1053 * PLLRE1054 * VCO is exposed to the clock tree directly along with post-divider output1055 */1056static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)1057{1058	u32 mask;1059	u32 val = readl_relaxed(clk_base + pllre->params->base_reg);1060 1061	pllre->params->defaults_set = true;1062 1063	if (val & PLL_ENABLE) {1064		/*1065		 * PLL is ON: check if defaults already set, then set those1066		 * that can be updated in flight.1067		 */1068		val &= PLLRE_BASE_DEFAULT_MASK;1069		if (val != PLLRE_BASE_DEFAULT_VALUE) {1070			pr_warn("pllre boot base 0x%x : expected 0x%x\n",1071				val, PLLRE_BASE_DEFAULT_VALUE);1072			pr_warn("(comparison mask = 0x%x)\n",1073				PLLRE_BASE_DEFAULT_MASK);1074			pllre->params->defaults_set = false;1075		}1076 1077		/* Ignore lock enable */1078		val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);1079		mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;1080		_pll_misc_chk_default(clk_base, pllre->params, 0, val,1081				~mask & PLLRE_MISC0_WRITE_MASK);1082 1083		/* The PLL doesn't work if it's in IDDQ. */1084		val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);1085		if (val & PLLRE_MISC0_IDDQ)1086			pr_warn("unexpected IDDQ bit set for enabled clock\n");1087 1088		/* Enable lock detect */1089		val &= ~mask;1090		val |= PLLRE_MISC0_DEFAULT_VALUE & mask;1091		writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);1092		udelay(1);1093 1094		if (!pllre->params->defaults_set)1095			pr_warn("PLL_RE already enabled. Postponing set full defaults\n");1096 1097		return;1098	}1099 1100	/* set IDDQ, enable lock detect */1101	val &= ~PLLRE_BASE_DEFAULT_MASK;1102	val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;1103	writel_relaxed(val, clk_base + pllre->params->base_reg);1104	writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,1105			clk_base + pllre->params->ext_misc_reg[0]);1106	udelay(1);1107}1108 1109static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)1110{1111	unsigned long input_rate;1112 1113	/* cf rate */1114	if (!IS_ERR_OR_NULL(hw->clk))1115		input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));1116	else1117		input_rate = 38400000;1118 1119	input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);1120 1121	switch (input_rate) {1122	case 12000000:1123	case 12800000:1124	case 13000000:1125		*step_a = 0x2B;1126		*step_b = 0x0B;1127		return;1128	case 19200000:1129		*step_a = 0x12;1130		*step_b = 0x08;1131		return;1132	case 38400000:1133		*step_a = 0x04;1134		*step_b = 0x05;1135		return;1136	default:1137		pr_err("%s: Unexpected reference rate %lu\n",1138			__func__, input_rate);1139		BUG();1140	}1141}1142 1143static void pllx_check_defaults(struct tegra_clk_pll *pll)1144{1145	u32 default_val;1146 1147	default_val = PLLX_MISC0_DEFAULT_VALUE;1148	/* ignore lock enable */1149	_pll_misc_chk_default(clk_base, pll->params, 0, default_val,1150			PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));1151 1152	default_val = PLLX_MISC1_DEFAULT_VALUE;1153	_pll_misc_chk_default(clk_base, pll->params, 1, default_val,1154			PLLX_MISC1_WRITE_MASK);1155 1156	/* ignore all but control bit */1157	default_val = PLLX_MISC2_DEFAULT_VALUE;1158	_pll_misc_chk_default(clk_base, pll->params, 2,1159			default_val, PLLX_MISC2_EN_DYNRAMP);1160 1161	default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);1162	_pll_misc_chk_default(clk_base, pll->params, 3, default_val,1163			PLLX_MISC3_WRITE_MASK);1164 1165	default_val = PLLX_MISC4_DEFAULT_VALUE;1166	_pll_misc_chk_default(clk_base, pll->params, 4, default_val,1167			PLLX_MISC4_WRITE_MASK);1168 1169	default_val = PLLX_MISC5_DEFAULT_VALUE;1170	_pll_misc_chk_default(clk_base, pll->params, 5, default_val,1171			PLLX_MISC5_WRITE_MASK);1172}1173 1174static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)1175{1176	u32 val;1177	u32 step_a, step_b;1178 1179	pllx->params->defaults_set = true;1180 1181	/* Get ready dyn ramp state machine settings */1182	pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);1183	val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &1184		(~PLLX_MISC2_DYNRAMP_STEPB_MASK);1185	val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;1186	val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;1187 1188	if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {1189 1190		/*1191		 * PLL is ON: check if defaults already set, then set those1192		 * that can be updated in flight.1193		 */1194		pllx_check_defaults(pllx);1195 1196		if (!pllx->params->defaults_set)1197			pr_warn("PLL_X already enabled. Postponing set full defaults\n");1198		/* Configure dyn ramp, disable lock override */1199		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);1200 1201		/* Enable lock detect */1202		val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);1203		val &= ~PLLX_MISC0_LOCK_ENABLE;1204		val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;1205		writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);1206		udelay(1);1207 1208		return;1209	}1210 1211	/* Enable lock detect and CPU output */1212	writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +1213			pllx->params->ext_misc_reg[0]);1214 1215	/* Setup */1216	writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +1217			pllx->params->ext_misc_reg[1]);1218 1219	/* Configure dyn ramp state machine, disable lock override */1220	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);1221 1222	/* Set IDDQ */1223	writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +1224			pllx->params->ext_misc_reg[3]);1225 1226	/* Disable SDM */1227	writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +1228			pllx->params->ext_misc_reg[4]);1229	writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +1230			pllx->params->ext_misc_reg[5]);1231	udelay(1);1232}1233 1234/* PLLMB */1235static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)1236{1237	u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);1238 1239	pllmb->params->defaults_set = true;1240 1241	if (val & PLL_ENABLE) {1242 1243		/*1244		 * PLL is ON: check if defaults already set, then set those1245		 * that can be updated in flight.1246		 */1247		val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);1248		mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;1249		_pll_misc_chk_default(clk_base, pllmb->params, 0, val,1250				~mask & PLLMB_MISC1_WRITE_MASK);1251 1252		if (!pllmb->params->defaults_set)1253			pr_warn("PLL_MB already enabled. Postponing set full defaults\n");1254		/* Enable lock detect */1255		val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);1256		val &= ~mask;1257		val |= PLLMB_MISC1_DEFAULT_VALUE & mask;1258		writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);1259		udelay(1);1260 1261		return;1262	}1263 1264	/* set IDDQ, enable lock detect */1265	writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,1266			clk_base + pllmb->params->ext_misc_reg[0]);1267	udelay(1);1268}1269 1270/*1271 * PLLP1272 * VCO is exposed to the clock tree directly along with post-divider output.1273 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,1274 * respectively.1275 */1276static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)1277{1278	u32 val, mask;1279 1280	/* Ignore lock enable (will be set), make sure not in IDDQ if enabled */1281	val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);1282	mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;1283	if (!enabled)1284		mask |= PLLP_MISC0_IDDQ;1285	_pll_misc_chk_default(clk_base, pll->params, 0, val,1286			~mask & PLLP_MISC0_WRITE_MASK);1287 1288	/* Ignore branch controls */1289	val = PLLP_MISC1_DEFAULT_VALUE;1290	mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;1291	_pll_misc_chk_default(clk_base, pll->params, 1, val,1292			~mask & PLLP_MISC1_WRITE_MASK);1293}1294 1295static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)1296{1297	u32 mask;1298	u32 val = readl_relaxed(clk_base + pllp->params->base_reg);1299 1300	pllp->params->defaults_set = true;1301 1302	if (val & PLL_ENABLE) {1303 1304		/*1305		 * PLL is ON: check if defaults already set, then set those1306		 * that can be updated in flight.1307		 */1308		pllp_check_defaults(pllp, true);1309		if (!pllp->params->defaults_set)1310			pr_warn("PLL_P already enabled. Postponing set full defaults\n");1311 1312		/* Enable lock detect */1313		val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);1314		mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;1315		val &= ~mask;1316		val |= PLLP_MISC0_DEFAULT_VALUE & mask;1317		writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);1318		udelay(1);1319 1320		return;1321	}1322 1323	/* set IDDQ, enable lock detect */1324	writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,1325			clk_base + pllp->params->ext_misc_reg[0]);1326 1327	/* Preserve branch control */1328	val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);1329	mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;1330	val &= mask;1331	val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;1332	writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);1333	udelay(1);1334}1335 1336/*1337 * PLLU1338 * VCO is exposed to the clock tree directly along with post-divider output.1339 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,1340 * respectively.1341 */1342static void pllu_check_defaults(struct tegra_clk_pll_params *params,1343				bool hw_control)1344{1345	u32 val, mask;1346 1347	/* Ignore lock enable (will be set) and IDDQ if under h/w control */1348	val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);1349	mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);1350	_pll_misc_chk_default(clk_base, params, 0, val,1351			~mask & PLLU_MISC0_WRITE_MASK);1352 1353	val = PLLU_MISC1_DEFAULT_VALUE;1354	mask = PLLU_MISC1_LOCK_OVERRIDE;1355	_pll_misc_chk_default(clk_base, params, 1, val,1356			~mask & PLLU_MISC1_WRITE_MASK);1357}1358 1359static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)1360{1361	u32 val = readl_relaxed(clk_base + pllu->base_reg);1362 1363	pllu->defaults_set = true;1364 1365	if (val & PLL_ENABLE) {1366 1367		/*1368		 * PLL is ON: check if defaults already set, then set those1369		 * that can be updated in flight.1370		 */1371		pllu_check_defaults(pllu, false);1372		if (!pllu->defaults_set)1373			pr_warn("PLL_U already enabled. Postponing set full defaults\n");1374 1375		/* Enable lock detect */1376		val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);1377		val &= ~PLLU_MISC0_LOCK_ENABLE;1378		val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;1379		writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);1380 1381		val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);1382		val &= ~PLLU_MISC1_LOCK_OVERRIDE;1383		val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;1384		writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);1385		udelay(1);1386 1387		return;1388	}1389 1390	/* set IDDQ, enable lock detect */1391	writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,1392			clk_base + pllu->ext_misc_reg[0]);1393	writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,1394			clk_base + pllu->ext_misc_reg[1]);1395	udelay(1);1396}1397 1398#define mask(w) ((1 << (w)) - 1)1399#define divm_mask(p) mask(p->params->div_nmp->divm_width)1400#define divn_mask(p) mask(p->params->div_nmp->divn_width)1401#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\1402		      mask(p->params->div_nmp->divp_width))1403 1404#define divm_shift(p) ((p)->params->div_nmp->divm_shift)1405#define divn_shift(p) ((p)->params->div_nmp->divn_shift)1406#define divp_shift(p) ((p)->params->div_nmp->divp_shift)1407 1408#define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))1409#define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))1410#define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))1411 1412#define PLL_LOCKDET_DELAY 2	/* Lock detection safety delays */1413static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,1414				  u32 reg, u32 mask)1415{1416	int i;1417	u32 val = 0;1418 1419	for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {1420		udelay(PLL_LOCKDET_DELAY);1421		val = readl_relaxed(clk_base + reg);1422		if ((val & mask) == mask) {1423			udelay(PLL_LOCKDET_DELAY);1424			return 0;1425		}1426	}1427	return -ETIMEDOUT;1428}1429 1430static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,1431		struct tegra_clk_pll_freq_table *cfg)1432{1433	u32 val, base, ndiv_new_mask;1434 1435	ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)1436			 << PLLX_MISC2_NDIV_NEW_SHIFT;1437 1438	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);1439	val &= (~ndiv_new_mask);1440	val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;1441	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);1442	udelay(1);1443 1444	val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);1445	val |= PLLX_MISC2_EN_DYNRAMP;1446	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);1447	udelay(1);1448 1449	tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],1450			       PLLX_MISC2_DYNRAMP_DONE);1451 1452	base = readl_relaxed(clk_base + pllx->params->base_reg) &1453		(~divn_mask_shifted(pllx));1454	base |= cfg->n << pllx->params->div_nmp->divn_shift;1455	writel_relaxed(base, clk_base + pllx->params->base_reg);1456	udelay(1);1457 1458	val &= ~PLLX_MISC2_EN_DYNRAMP;1459	writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);1460	udelay(1);1461 1462	pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",1463		 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,1464		 cfg->input_rate / cfg->m * cfg->n /1465		 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);1466 1467	return 0;1468}1469 1470/*1471 * Common configuration for PLLs with fixed input divider policy:1472 * - always set fixed M-value based on the reference rate1473 * - always set P-value value 1:1 for output rates above VCO minimum, and1474 *   choose minimum necessary P-value for output rates below VCO maximum1475 * - calculate N-value based on selected M and P1476 * - calculate SDM_DIN fractional part1477 */1478static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,1479			       struct tegra_clk_pll_freq_table *cfg,1480			       unsigned long rate, unsigned long input_rate)1481{1482	struct tegra_clk_pll *pll = to_clk_pll(hw);1483	struct tegra_clk_pll_params *params = pll->params;1484	int p;1485	unsigned long cf, p_rate;1486	u32 pdiv;1487 1488	if (!rate)1489		return -EINVAL;1490 1491	if (!(params->flags & TEGRA_PLL_VCO_OUT)) {1492		p = DIV_ROUND_UP(params->vco_min, rate);1493		p = params->round_p_to_pdiv(p, &pdiv);1494	} else {1495		p = rate >= params->vco_min ? 1 : -EINVAL;1496	}1497 1498	if (p < 0)1499		return -EINVAL;1500 1501	cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);1502	cfg->p = p;1503 1504	/* Store P as HW value, as that is what is expected */1505	cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);1506 1507	p_rate = rate * p;1508	if (p_rate > params->vco_max)1509		p_rate = params->vco_max;1510	cf = input_rate / cfg->m;1511	cfg->n = p_rate / cf;1512 1513	cfg->sdm_data = 0;1514	cfg->output_rate = input_rate;1515	if (params->sdm_ctrl_reg) {1516		unsigned long rem = p_rate - cf * cfg->n;1517		/* If ssc is enabled SDM enabled as well, even for integer n */1518		if (rem || params->ssc_ctrl_reg) {1519			u64 s = rem * PLL_SDM_COEFF;1520 1521			do_div(s, cf);1522			s -= PLL_SDM_COEFF / 2;1523			cfg->sdm_data = sdin_din_to_data(s);1524		}1525		cfg->output_rate *= sdin_get_n_eff(cfg);1526		cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;1527	} else {1528		cfg->output_rate *= cfg->n;1529		cfg->output_rate /= p * cfg->m;1530	}1531 1532	cfg->input_rate = input_rate;1533 1534	return 0;1535}1536 1537/*1538 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate1539 *1540 * @cfg: struct tegra_clk_pll_freq_table * cfg1541 *1542 * For Normal mode:1543 *     Fvco = Fref * NDIV / MDIV1544 *1545 * For fractional mode:1546 *     Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV1547 */1548static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)1549{1550	cfg->n = sdin_get_n_eff(cfg);1551	cfg->m *= PLL_SDM_COEFF;1552}1553 1554static unsigned long1555tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,1556			    unsigned long parent_rate)1557{1558	unsigned long vco_min = params->vco_min;1559 1560	params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);1561	vco_min = min(vco_min, params->vco_min);1562 1563	return vco_min;1564}1565 1566static struct div_nmp pllx_nmp = {1567	.divm_shift = 0,1568	.divm_width = 8,1569	.divn_shift = 8,1570	.divn_width = 8,1571	.divp_shift = 20,1572	.divp_width = 5,1573};1574/*1575 * PLL post divider maps - two types: quasi-linear and exponential1576 * post divider.1577 */1578#define PLL_QLIN_PDIV_MAX	161579static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {1580	{ .pdiv =  1, .hw_val =  0 },1581	{ .pdiv =  2, .hw_val =  1 },1582	{ .pdiv =  3, .hw_val =  2 },1583	{ .pdiv =  4, .hw_val =  3 },1584	{ .pdiv =  5, .hw_val =  4 },1585	{ .pdiv =  6, .hw_val =  5 },1586	{ .pdiv =  8, .hw_val =  6 },1587	{ .pdiv =  9, .hw_val =  7 },1588	{ .pdiv = 10, .hw_val =  8 },1589	{ .pdiv = 12, .hw_val =  9 },1590	{ .pdiv = 15, .hw_val = 10 },1591	{ .pdiv = 16, .hw_val = 11 },1592	{ .pdiv = 18, .hw_val = 12 },1593	{ .pdiv = 20, .hw_val = 13 },1594	{ .pdiv = 24, .hw_val = 14 },1595	{ .pdiv = 30, .hw_val = 15 },1596	{ .pdiv = 32, .hw_val = 16 },1597};1598 1599static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)1600{1601	int i;1602 1603	if (p) {1604		for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {1605			if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {1606				if (pdiv)1607					*pdiv = i;1608				return pll_qlin_pdiv_to_hw[i].pdiv;1609			}1610		}1611	}1612 1613	return -EINVAL;1614}1615 1616#define PLL_EXPO_PDIV_MAX	71617static const struct pdiv_map pll_expo_pdiv_to_hw[] = {1618	{ .pdiv =   1, .hw_val = 0 },1619	{ .pdiv =   2, .hw_val = 1 },1620	{ .pdiv =   4, .hw_val = 2 },1621	{ .pdiv =   8, .hw_val = 3 },1622	{ .pdiv =  16, .hw_val = 4 },1623	{ .pdiv =  32, .hw_val = 5 },1624	{ .pdiv =  64, .hw_val = 6 },1625	{ .pdiv = 128, .hw_val = 7 },1626};1627 1628static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)1629{1630	if (p) {1631		u32 i = fls(p);1632 1633		if (i == ffs(p))1634			i--;1635 1636		if (i <= PLL_EXPO_PDIV_MAX) {1637			if (pdiv)1638				*pdiv = i;1639			return 1 << i;1640		}1641	}1642	return -EINVAL;1643}1644 1645static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {1646	/* 1 GHz */1647	{ 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */1648	{ 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */1649	{ 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */1650	{        0,          0,   0, 0, 0, 0 },1651};1652 1653static struct tegra_clk_pll_params pll_x_params = {1654	.input_min = 12000000,1655	.input_max = 800000000,1656	.cf_min = 12000000,1657	.cf_max = 38400000,1658	.vco_min = 1350000000,1659	.vco_max = 3000000000UL,1660	.base_reg = PLLX_BASE,1661	.misc_reg = PLLX_MISC0,1662	.lock_mask = PLL_BASE_LOCK,1663	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,1664	.lock_delay = 300,1665	.ext_misc_reg[0] = PLLX_MISC0,1666	.ext_misc_reg[1] = PLLX_MISC1,1667	.ext_misc_reg[2] = PLLX_MISC2,1668	.ext_misc_reg[3] = PLLX_MISC3,1669	.ext_misc_reg[4] = PLLX_MISC4,1670	.ext_misc_reg[5] = PLLX_MISC5,1671	.iddq_reg = PLLX_MISC3,1672	.iddq_bit_idx = PLLXP_IDDQ_BIT,1673	.max_p = PLL_QLIN_PDIV_MAX,1674	.mdiv_default = 2,1675	.dyn_ramp_reg = PLLX_MISC2,1676	.stepa_shift = 16,1677	.stepb_shift = 24,1678	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1679	.pdiv_tohw = pll_qlin_pdiv_to_hw,1680	.div_nmp = &pllx_nmp,1681	.freq_table = pll_x_freq_table,1682	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,1683	.dyn_ramp = tegra210_pllx_dyn_ramp,1684	.set_defaults = tegra210_pllx_set_defaults,1685	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1686};1687 1688static struct div_nmp pllc_nmp = {1689	.divm_shift = 0,1690	.divm_width = 8,1691	.divn_shift = 10,1692	.divn_width = 8,1693	.divp_shift = 20,1694	.divp_width = 5,1695};1696 1697static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {1698	{ 12000000, 510000000, 85, 1, 2, 0 },1699	{ 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */1700	{ 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */1701	{        0,         0,  0, 0, 0, 0 },1702};1703 1704static struct tegra_clk_pll_params pll_c_params = {1705	.input_min = 12000000,1706	.input_max = 700000000,1707	.cf_min = 12000000,1708	.cf_max = 50000000,1709	.vco_min = 600000000,1710	.vco_max = 1200000000,1711	.base_reg = PLLC_BASE,1712	.misc_reg = PLLC_MISC0,1713	.lock_mask = PLL_BASE_LOCK,1714	.lock_delay = 300,1715	.iddq_reg = PLLC_MISC1,1716	.iddq_bit_idx = PLLCX_IDDQ_BIT,1717	.reset_reg = PLLC_MISC0,1718	.reset_bit_idx = PLLCX_RESET_BIT,1719	.max_p = PLL_QLIN_PDIV_MAX,1720	.ext_misc_reg[0] = PLLC_MISC0,1721	.ext_misc_reg[1] = PLLC_MISC1,1722	.ext_misc_reg[2] = PLLC_MISC2,1723	.ext_misc_reg[3] = PLLC_MISC3,1724	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1725	.pdiv_tohw = pll_qlin_pdiv_to_hw,1726	.mdiv_default = 3,1727	.div_nmp = &pllc_nmp,1728	.freq_table = pll_cx_freq_table,1729	.flags = TEGRA_PLL_USE_LOCK,1730	.set_defaults = _pllc_set_defaults,1731	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1732};1733 1734static struct div_nmp pllcx_nmp = {1735	.divm_shift = 0,1736	.divm_width = 8,1737	.divn_shift = 10,1738	.divn_width = 8,1739	.divp_shift = 20,1740	.divp_width = 5,1741};1742 1743static struct tegra_clk_pll_params pll_c2_params = {1744	.input_min = 12000000,1745	.input_max = 700000000,1746	.cf_min = 12000000,1747	.cf_max = 50000000,1748	.vco_min = 600000000,1749	.vco_max = 1200000000,1750	.base_reg = PLLC2_BASE,1751	.misc_reg = PLLC2_MISC0,1752	.iddq_reg = PLLC2_MISC1,1753	.iddq_bit_idx = PLLCX_IDDQ_BIT,1754	.reset_reg = PLLC2_MISC0,1755	.reset_bit_idx = PLLCX_RESET_BIT,1756	.lock_mask = PLLCX_BASE_LOCK,1757	.lock_delay = 300,1758	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1759	.pdiv_tohw = pll_qlin_pdiv_to_hw,1760	.mdiv_default = 3,1761	.div_nmp = &pllcx_nmp,1762	.max_p = PLL_QLIN_PDIV_MAX,1763	.ext_misc_reg[0] = PLLC2_MISC0,1764	.ext_misc_reg[1] = PLLC2_MISC1,1765	.ext_misc_reg[2] = PLLC2_MISC2,1766	.ext_misc_reg[3] = PLLC2_MISC3,1767	.freq_table = pll_cx_freq_table,1768	.flags = TEGRA_PLL_USE_LOCK,1769	.set_defaults = _pllc2_set_defaults,1770	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1771};1772 1773static struct tegra_clk_pll_params pll_c3_params = {1774	.input_min = 12000000,1775	.input_max = 700000000,1776	.cf_min = 12000000,1777	.cf_max = 50000000,1778	.vco_min = 600000000,1779	.vco_max = 1200000000,1780	.base_reg = PLLC3_BASE,1781	.misc_reg = PLLC3_MISC0,1782	.lock_mask = PLLCX_BASE_LOCK,1783	.lock_delay = 300,1784	.iddq_reg = PLLC3_MISC1,1785	.iddq_bit_idx = PLLCX_IDDQ_BIT,1786	.reset_reg = PLLC3_MISC0,1787	.reset_bit_idx = PLLCX_RESET_BIT,1788	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1789	.pdiv_tohw = pll_qlin_pdiv_to_hw,1790	.mdiv_default = 3,1791	.div_nmp = &pllcx_nmp,1792	.max_p = PLL_QLIN_PDIV_MAX,1793	.ext_misc_reg[0] = PLLC3_MISC0,1794	.ext_misc_reg[1] = PLLC3_MISC1,1795	.ext_misc_reg[2] = PLLC3_MISC2,1796	.ext_misc_reg[3] = PLLC3_MISC3,1797	.freq_table = pll_cx_freq_table,1798	.flags = TEGRA_PLL_USE_LOCK,1799	.set_defaults = _pllc3_set_defaults,1800	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1801};1802 1803static struct div_nmp pllss_nmp = {1804	.divm_shift = 0,1805	.divm_width = 8,1806	.divn_shift = 8,1807	.divn_width = 8,1808	.divp_shift = 19,1809	.divp_width = 5,1810};1811 1812static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {1813	{ 12000000, 600000000, 50, 1, 1, 0 },1814	{ 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */1815	{ 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */1816	{        0,         0,  0, 0, 0, 0 },1817};1818 1819static const struct clk_div_table pll_vco_post_div_table[] = {1820	{ .val =  0, .div =  1 },1821	{ .val =  1, .div =  2 },1822	{ .val =  2, .div =  3 },1823	{ .val =  3, .div =  4 },1824	{ .val =  4, .div =  5 },1825	{ .val =  5, .div =  6 },1826	{ .val =  6, .div =  8 },1827	{ .val =  7, .div = 10 },1828	{ .val =  8, .div = 12 },1829	{ .val =  9, .div = 16 },1830	{ .val = 10, .div = 12 },1831	{ .val = 11, .div = 16 },1832	{ .val = 12, .div = 20 },1833	{ .val = 13, .div = 24 },1834	{ .val = 14, .div = 32 },1835	{ .val =  0, .div =  0 },1836};1837 1838static struct tegra_clk_pll_params pll_c4_vco_params = {1839	.input_min = 9600000,1840	.input_max = 800000000,1841	.cf_min = 9600000,1842	.cf_max = 19200000,1843	.vco_min = 500000000,1844	.vco_max = 1080000000,1845	.base_reg = PLLC4_BASE,1846	.misc_reg = PLLC4_MISC0,1847	.lock_mask = PLL_BASE_LOCK,1848	.lock_delay = 300,1849	.max_p = PLL_QLIN_PDIV_MAX,1850	.ext_misc_reg[0] = PLLC4_MISC0,1851	.iddq_reg = PLLC4_BASE,1852	.iddq_bit_idx = PLLSS_IDDQ_BIT,1853	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1854	.pdiv_tohw = pll_qlin_pdiv_to_hw,1855	.mdiv_default = 3,1856	.div_nmp = &pllss_nmp,1857	.freq_table = pll_c4_vco_freq_table,1858	.set_defaults = tegra210_pllc4_set_defaults,1859	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,1860	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1861};1862 1863static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {1864	{ 12000000,  800000000,  66, 1, 1, 0 }, /* actual: 792.0 MHz */1865	{ 13000000,  800000000,  61, 1, 1, 0 }, /* actual: 793.0 MHz */1866	{ 38400000,  297600000,  93, 4, 3, 0 },1867	{ 38400000,  400000000, 125, 4, 3, 0 },1868	{ 38400000,  532800000, 111, 4, 2, 0 },1869	{ 38400000,  665600000, 104, 3, 2, 0 },1870	{ 38400000,  800000000, 125, 3, 2, 0 },1871	{ 38400000,  931200000,  97, 4, 1, 0 },1872	{ 38400000, 1065600000, 111, 4, 1, 0 },1873	{ 38400000, 1200000000, 125, 4, 1, 0 },1874	{ 38400000, 1331200000, 104, 3, 1, 0 },1875	{ 38400000, 1459200000,  76, 2, 1, 0 },1876	{ 38400000, 1600000000, 125, 3, 1, 0 },1877	{        0,          0,   0, 0, 0, 0 },1878};1879 1880static struct div_nmp pllm_nmp = {1881	.divm_shift = 0,1882	.divm_width = 8,1883	.override_divm_shift = 0,1884	.divn_shift = 8,1885	.divn_width = 8,1886	.override_divn_shift = 8,1887	.divp_shift = 20,1888	.divp_width = 5,1889	.override_divp_shift = 27,1890};1891 1892static struct tegra_clk_pll_params pll_m_params = {1893	.input_min = 9600000,1894	.input_max = 500000000,1895	.cf_min = 9600000,1896	.cf_max = 19200000,1897	.vco_min = 800000000,1898	.vco_max = 1866000000,1899	.base_reg = PLLM_BASE,1900	.misc_reg = PLLM_MISC2,1901	.lock_mask = PLL_BASE_LOCK,1902	.lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,1903	.lock_delay = 300,1904	.iddq_reg = PLLM_MISC2,1905	.iddq_bit_idx = PLLM_IDDQ_BIT,1906	.max_p = PLL_QLIN_PDIV_MAX,1907	.ext_misc_reg[0] = PLLM_MISC2,1908	.ext_misc_reg[1] = PLLM_MISC1,1909	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1910	.pdiv_tohw = pll_qlin_pdiv_to_hw,1911	.div_nmp = &pllm_nmp,1912	.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,1913	.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,1914	.freq_table = pll_m_freq_table,1915	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,1916	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1917};1918 1919static struct tegra_clk_pll_params pll_mb_params = {1920	.input_min = 9600000,1921	.input_max = 500000000,1922	.cf_min = 9600000,1923	.cf_max = 19200000,1924	.vco_min = 800000000,1925	.vco_max = 1866000000,1926	.base_reg = PLLMB_BASE,1927	.misc_reg = PLLMB_MISC1,1928	.lock_mask = PLL_BASE_LOCK,1929	.lock_delay = 300,1930	.iddq_reg = PLLMB_MISC1,1931	.iddq_bit_idx = PLLMB_IDDQ_BIT,1932	.max_p = PLL_QLIN_PDIV_MAX,1933	.ext_misc_reg[0] = PLLMB_MISC1,1934	.round_p_to_pdiv = pll_qlin_p_to_pdiv,1935	.pdiv_tohw = pll_qlin_pdiv_to_hw,1936	.div_nmp = &pllm_nmp,1937	.freq_table = pll_m_freq_table,1938	.flags = TEGRA_PLL_USE_LOCK,1939	.set_defaults = tegra210_pllmb_set_defaults,1940	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1941};1942 1943 1944static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {1945	/* PLLE special case: use cpcon field to store cml divider value */1946	{ 672000000, 100000000, 125, 42, 0, 13 },1947	{ 624000000, 100000000, 125, 39, 0, 13 },1948	{ 336000000, 100000000, 125, 21, 0, 13 },1949	{ 312000000, 100000000, 200, 26, 0, 14 },1950	{  38400000, 100000000, 125,  2, 0, 14 },1951	{  12000000, 100000000, 200,  1, 0, 14 },1952	{         0,         0,   0,  0, 0,  0 },1953};1954 1955static struct div_nmp plle_nmp = {1956	.divm_shift = 0,1957	.divm_width = 8,1958	.divn_shift = 8,1959	.divn_width = 8,1960	.divp_shift = 24,1961	.divp_width = 5,1962};1963 1964static struct tegra_clk_pll_params pll_e_params = {1965	.input_min = 12000000,1966	.input_max = 800000000,1967	.cf_min = 12000000,1968	.cf_max = 38400000,1969	.vco_min = 1600000000,1970	.vco_max = 2500000000U,1971	.base_reg = PLLE_BASE,1972	.misc_reg = PLLE_MISC0,1973	.aux_reg = PLLE_AUX,1974	.lock_mask = PLLE_MISC_LOCK,1975	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,1976	.lock_delay = 300,1977	.div_nmp = &plle_nmp,1978	.freq_table = pll_e_freq_table,1979	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |1980		 TEGRA_PLL_HAS_LOCK_ENABLE,1981	.fixed_rate = 100000000,1982	.calc_rate = tegra210_pll_fixed_mdiv_cfg,1983};1984 1985static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {1986	{ 12000000, 672000000, 56, 1, 1, 0 },1987	{ 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */1988	{ 38400000, 672000000, 70, 4, 1, 0 },1989	{        0,         0,  0, 0, 0, 0 },1990};1991 1992static struct div_nmp pllre_nmp = {1993	.divm_shift = 0,1994	.divm_width = 8,1995	.divn_shift = 8,1996	.divn_width = 8,1997	.divp_shift = 16,1998	.divp_width = 5,1999};2000 2001static struct tegra_clk_pll_params pll_re_vco_params = {2002	.input_min = 9600000,2003	.input_max = 800000000,2004	.cf_min = 9600000,2005	.cf_max = 19200000,2006	.vco_min = 350000000,2007	.vco_max = 700000000,2008	.base_reg = PLLRE_BASE,2009	.misc_reg = PLLRE_MISC0,2010	.lock_mask = PLLRE_MISC_LOCK,2011	.lock_delay = 300,2012	.max_p = PLL_QLIN_PDIV_MAX,2013	.ext_misc_reg[0] = PLLRE_MISC0,2014	.iddq_reg = PLLRE_MISC0,2015	.iddq_bit_idx = PLLRE_IDDQ_BIT,2016	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2017	.pdiv_tohw = pll_qlin_pdiv_to_hw,2018	.div_nmp = &pllre_nmp,2019	.freq_table = pll_re_vco_freq_table,2020	.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,2021	.set_defaults = tegra210_pllre_set_defaults,2022	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2023};2024 2025static struct div_nmp pllp_nmp = {2026	.divm_shift = 0,2027	.divm_width = 8,2028	.divn_shift = 10,2029	.divn_width = 8,2030	.divp_shift = 20,2031	.divp_width = 5,2032};2033 2034static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {2035	{ 12000000, 408000000, 34, 1, 1, 0 },2036	{ 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */2037	{        0,         0,  0, 0, 0, 0 },2038};2039 2040static struct tegra_clk_pll_params pll_p_params = {2041	.input_min = 9600000,2042	.input_max = 800000000,2043	.cf_min = 9600000,2044	.cf_max = 19200000,2045	.vco_min = 350000000,2046	.vco_max = 700000000,2047	.base_reg = PLLP_BASE,2048	.misc_reg = PLLP_MISC0,2049	.lock_mask = PLL_BASE_LOCK,2050	.lock_delay = 300,2051	.iddq_reg = PLLP_MISC0,2052	.iddq_bit_idx = PLLXP_IDDQ_BIT,2053	.ext_misc_reg[0] = PLLP_MISC0,2054	.ext_misc_reg[1] = PLLP_MISC1,2055	.div_nmp = &pllp_nmp,2056	.freq_table = pll_p_freq_table,2057	.fixed_rate = 408000000,2058	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,2059	.set_defaults = tegra210_pllp_set_defaults,2060	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2061};2062 2063static struct tegra_clk_pll_params pll_a1_params = {2064	.input_min = 12000000,2065	.input_max = 700000000,2066	.cf_min = 12000000,2067	.cf_max = 50000000,2068	.vco_min = 600000000,2069	.vco_max = 1200000000,2070	.base_reg = PLLA1_BASE,2071	.misc_reg = PLLA1_MISC0,2072	.lock_mask = PLLCX_BASE_LOCK,2073	.lock_delay = 300,2074	.iddq_reg = PLLA1_MISC1,2075	.iddq_bit_idx = PLLCX_IDDQ_BIT,2076	.reset_reg = PLLA1_MISC0,2077	.reset_bit_idx = PLLCX_RESET_BIT,2078	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2079	.pdiv_tohw = pll_qlin_pdiv_to_hw,2080	.div_nmp = &pllc_nmp,2081	.ext_misc_reg[0] = PLLA1_MISC0,2082	.ext_misc_reg[1] = PLLA1_MISC1,2083	.ext_misc_reg[2] = PLLA1_MISC2,2084	.ext_misc_reg[3] = PLLA1_MISC3,2085	.freq_table = pll_cx_freq_table,2086	.flags = TEGRA_PLL_USE_LOCK,2087	.set_defaults = _plla1_set_defaults,2088	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2089};2090 2091static struct div_nmp plla_nmp = {2092	.divm_shift = 0,2093	.divm_width = 8,2094	.divn_shift = 8,2095	.divn_width = 8,2096	.divp_shift = 20,2097	.divp_width = 5,2098};2099 2100static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {2101	{ 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */2102	{ 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */2103	{ 12000000, 240000000, 60, 1, 3, 1,      0 },2104	{ 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */2105	{ 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */2106	{ 13000000, 240000000, 55, 1, 3, 1,      0 }, /* actual: 238.3 MHz */2107	{ 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */2108	{ 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */2109	{ 38400000, 240000000, 75, 3, 3, 1,      0 },2110	{        0,         0,  0, 0, 0, 0,      0 },2111};2112 2113static struct tegra_clk_pll_params pll_a_params = {2114	.input_min = 12000000,2115	.input_max = 800000000,2116	.cf_min = 12000000,2117	.cf_max = 19200000,2118	.vco_min = 500000000,2119	.vco_max = 1000000000,2120	.base_reg = PLLA_BASE,2121	.misc_reg = PLLA_MISC0,2122	.lock_mask = PLL_BASE_LOCK,2123	.lock_delay = 300,2124	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2125	.pdiv_tohw = pll_qlin_pdiv_to_hw,2126	.iddq_reg = PLLA_BASE,2127	.iddq_bit_idx = PLLA_IDDQ_BIT,2128	.div_nmp = &plla_nmp,2129	.sdm_din_reg = PLLA_MISC1,2130	.sdm_din_mask = PLLA_SDM_DIN_MASK,2131	.sdm_ctrl_reg = PLLA_MISC2,2132	.sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,2133	.ext_misc_reg[0] = PLLA_MISC0,2134	.ext_misc_reg[1] = PLLA_MISC1,2135	.ext_misc_reg[2] = PLLA_MISC2,2136	.freq_table = pll_a_freq_table,2137	.flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,2138	.set_defaults = tegra210_plla_set_defaults,2139	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2140	.set_gain = tegra210_clk_pll_set_gain,2141	.adjust_vco = tegra210_clk_adjust_vco_min,2142};2143 2144static struct div_nmp plld_nmp = {2145	.divm_shift = 0,2146	.divm_width = 8,2147	.divn_shift = 11,2148	.divn_width = 8,2149	.divp_shift = 20,2150	.divp_width = 3,2151};2152 2153static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {2154	{ 12000000, 594000000, 99, 1, 2, 0,      0 },2155	{ 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */2156	{ 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },2157	{        0,         0,  0, 0, 0, 0,      0 },2158};2159 2160static struct tegra_clk_pll_params pll_d_params = {2161	.input_min = 12000000,2162	.input_max = 800000000,2163	.cf_min = 12000000,2164	.cf_max = 38400000,2165	.vco_min = 750000000,2166	.vco_max = 1500000000,2167	.base_reg = PLLD_BASE,2168	.misc_reg = PLLD_MISC0,2169	.lock_mask = PLL_BASE_LOCK,2170	.lock_delay = 1000,2171	.iddq_reg = PLLD_MISC0,2172	.iddq_bit_idx = PLLD_IDDQ_BIT,2173	.round_p_to_pdiv = pll_expo_p_to_pdiv,2174	.pdiv_tohw = pll_expo_pdiv_to_hw,2175	.div_nmp = &plld_nmp,2176	.sdm_din_reg = PLLD_MISC0,2177	.sdm_din_mask = PLLA_SDM_DIN_MASK,2178	.sdm_ctrl_reg = PLLD_MISC0,2179	.sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,2180	.ext_misc_reg[0] = PLLD_MISC0,2181	.ext_misc_reg[1] = PLLD_MISC1,2182	.freq_table = pll_d_freq_table,2183	.flags = TEGRA_PLL_USE_LOCK,2184	.mdiv_default = 1,2185	.set_defaults = tegra210_plld_set_defaults,2186	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2187	.set_gain = tegra210_clk_pll_set_gain,2188	.adjust_vco = tegra210_clk_adjust_vco_min,2189};2190 2191static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {2192	{ 12000000, 594000000, 99, 1, 2, 0, 0xf000 },2193	{ 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */2194	{ 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },2195	{        0,         0,  0, 0, 0, 0,      0 },2196};2197 2198/* s/w policy, always tegra_pll_ref */2199static struct tegra_clk_pll_params pll_d2_params = {2200	.input_min = 12000000,2201	.input_max = 800000000,2202	.cf_min = 12000000,2203	.cf_max = 38400000,2204	.vco_min = 750000000,2205	.vco_max = 1500000000,2206	.base_reg = PLLD2_BASE,2207	.misc_reg = PLLD2_MISC0,2208	.lock_mask = PLL_BASE_LOCK,2209	.lock_delay = 300,2210	.iddq_reg = PLLD2_BASE,2211	.iddq_bit_idx = PLLSS_IDDQ_BIT,2212	.sdm_din_reg = PLLD2_MISC3,2213	.sdm_din_mask = PLLA_SDM_DIN_MASK,2214	.sdm_ctrl_reg = PLLD2_MISC1,2215	.sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,2216	/* disable spread-spectrum for pll_d2 */2217	.ssc_ctrl_reg = 0,2218	.ssc_ctrl_en_mask = 0,2219	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2220	.pdiv_tohw = pll_qlin_pdiv_to_hw,2221	.div_nmp = &pllss_nmp,2222	.ext_misc_reg[0] = PLLD2_MISC0,2223	.ext_misc_reg[1] = PLLD2_MISC1,2224	.ext_misc_reg[2] = PLLD2_MISC2,2225	.ext_misc_reg[3] = PLLD2_MISC3,2226	.max_p = PLL_QLIN_PDIV_MAX,2227	.mdiv_default = 1,2228	.freq_table = tegra210_pll_d2_freq_table,2229	.set_defaults = tegra210_plld2_set_defaults,2230	.flags = TEGRA_PLL_USE_LOCK,2231	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2232	.set_gain = tegra210_clk_pll_set_gain,2233	.adjust_vco = tegra210_clk_adjust_vco_min,2234};2235 2236static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {2237	{ 12000000, 270000000, 90, 1, 4, 0, 0xf000 },2238	{ 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */2239	{ 38400000, 270000000, 28, 1, 4, 0, 0xf400 },2240	{        0,         0,  0, 0, 0, 0,      0 },2241};2242 2243static struct tegra_clk_pll_params pll_dp_params = {2244	.input_min = 12000000,2245	.input_max = 800000000,2246	.cf_min = 12000000,2247	.cf_max = 38400000,2248	.vco_min = 750000000,2249	.vco_max = 1500000000,2250	.base_reg = PLLDP_BASE,2251	.misc_reg = PLLDP_MISC,2252	.lock_mask = PLL_BASE_LOCK,2253	.lock_delay = 300,2254	.iddq_reg = PLLDP_BASE,2255	.iddq_bit_idx = PLLSS_IDDQ_BIT,2256	.sdm_din_reg = PLLDP_SS_CTRL2,2257	.sdm_din_mask = PLLA_SDM_DIN_MASK,2258	.sdm_ctrl_reg = PLLDP_SS_CFG,2259	.sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,2260	.ssc_ctrl_reg = PLLDP_SS_CFG,2261	.ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,2262	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2263	.pdiv_tohw = pll_qlin_pdiv_to_hw,2264	.div_nmp = &pllss_nmp,2265	.ext_misc_reg[0] = PLLDP_MISC,2266	.ext_misc_reg[1] = PLLDP_SS_CFG,2267	.ext_misc_reg[2] = PLLDP_SS_CTRL1,2268	.ext_misc_reg[3] = PLLDP_SS_CTRL2,2269	.max_p = PLL_QLIN_PDIV_MAX,2270	.mdiv_default = 1,2271	.freq_table = pll_dp_freq_table,2272	.set_defaults = tegra210_plldp_set_defaults,2273	.flags = TEGRA_PLL_USE_LOCK,2274	.calc_rate = tegra210_pll_fixed_mdiv_cfg,2275	.set_gain = tegra210_clk_pll_set_gain,2276	.adjust_vco = tegra210_clk_adjust_vco_min,2277};2278 2279static struct div_nmp pllu_nmp = {2280	.divm_shift = 0,2281	.divm_width = 8,2282	.divn_shift = 8,2283	.divn_width = 8,2284	.divp_shift = 16,2285	.divp_width = 5,2286};2287 2288static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {2289	{ 12000000, 480000000, 40, 1, 1, 0 },2290	{ 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */2291	{ 38400000, 480000000, 25, 2, 1, 0 },2292	{        0,         0,  0, 0, 0, 0 },2293};2294 2295static struct tegra_clk_pll_params pll_u_vco_params = {2296	.input_min = 9600000,2297	.input_max = 800000000,2298	.cf_min = 9600000,2299	.cf_max = 19200000,2300	.vco_min = 350000000,2301	.vco_max = 700000000,2302	.base_reg = PLLU_BASE,2303	.misc_reg = PLLU_MISC0,2304	.lock_mask = PLL_BASE_LOCK,2305	.lock_delay = 1000,2306	.iddq_reg = PLLU_MISC0,2307	.iddq_bit_idx = PLLU_IDDQ_BIT,2308	.ext_misc_reg[0] = PLLU_MISC0,2309	.ext_misc_reg[1] = PLLU_MISC1,2310	.round_p_to_pdiv = pll_qlin_p_to_pdiv,2311	.pdiv_tohw = pll_qlin_pdiv_to_hw,2312	.div_nmp = &pllu_nmp,2313	.freq_table = pll_u_freq_table,2314	.flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,2315};2316 2317struct utmi_clk_param {2318	/* Oscillator Frequency in KHz */2319	u32 osc_frequency;2320	/* UTMIP PLL Enable Delay Count  */2321	u8 enable_delay_count;2322	/* UTMIP PLL Stable count */2323	u16 stable_count;2324	/*  UTMIP PLL Active delay count */2325	u8 active_delay_count;2326	/* UTMIP PLL Xtal frequency count */2327	u16 xtal_freq_count;2328};2329 2330static const struct utmi_clk_param utmi_parameters[] = {2331	{2332		.osc_frequency = 38400000, .enable_delay_count = 0x0,2333		.stable_count = 0x0, .active_delay_count = 0x6,2334		.xtal_freq_count = 0x802335	}, {2336		.osc_frequency = 13000000, .enable_delay_count = 0x02,2337		.stable_count = 0x33, .active_delay_count = 0x05,2338		.xtal_freq_count = 0x7f2339	}, {2340		.osc_frequency = 19200000, .enable_delay_count = 0x03,2341		.stable_count = 0x4b, .active_delay_count = 0x06,2342		.xtal_freq_count = 0xbb2343	}, {2344		.osc_frequency = 12000000, .enable_delay_count = 0x02,2345		.stable_count = 0x2f, .active_delay_count = 0x08,2346		.xtal_freq_count = 0x762347	}, {2348		.osc_frequency = 26000000, .enable_delay_count = 0x04,2349		.stable_count = 0x66, .active_delay_count = 0x09,2350		.xtal_freq_count = 0xfe2351	}, {2352		.osc_frequency = 16800000, .enable_delay_count = 0x03,2353		.stable_count = 0x41, .active_delay_count = 0x0a,2354		.xtal_freq_count = 0xa42355	},2356};2357 2358static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {2359	[tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },2360	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },2361	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },2362	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },2363	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },2364	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },2365	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },2366	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },2367	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },2368	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },2369	[tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },2370	[tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },2371	[tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },2372	[tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },2373	[tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },2374	[tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },2375	[tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },2376	[tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },2377	[tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },2378	[tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },2379	[tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },2380	[tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },2381	[tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },2382	[tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },2383	[tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },2384	[tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },2385	[tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },2386	[tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },2387	[tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },2388	[tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },2389	[tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },2390	[tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },2391	[tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },2392	[tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },2393	[tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },2394	[tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },2395	[tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },2396	[tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },2397	[tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },2398	[tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },2399	[tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },2400	[tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },2401	[tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },2402	[tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },2403	[tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },2404	[tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },2405	[tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },2406	[tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },2407	[tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },2408	[tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },2409	[tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },2410	[tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },2411	[tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },2412	[tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },2413	[tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },2414	[tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },2415	[tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },2416	[tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },2417	[tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },2418	[tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },2419	[tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },2420	[tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },2421	[tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },2422	[tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },2423	[tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },2424	[tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },2425	[tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },2426	[tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },2427	[tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },2428	[tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },2429	[tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },2430	[tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },2431	[tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },2432	[tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },2433	[tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },2434	[tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },2435	[tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },2436	[tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },2437	[tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },2438	[tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },2439	[tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },2440	[tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },2441	[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },2442	[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },2443	[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },2444	[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },2445	[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },2446	[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },2447	[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },2448	[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },2449	[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },2450	[tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },2451	[tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },2452	[tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },2453	[tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },2454	[tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },2455	[tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },2456	[tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },2457	[tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },2458	[tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },2459	[tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },2460	[tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },2461	[tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },2462	[tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },2463	[tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },2464	[tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },2465	[tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },2466	[tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },2467	[tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },2468	[tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },2469	[tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },2470	[tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },2471	[tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },2472	[tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },2473	[tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },2474	[tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },2475	[tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },2476	[tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },2477	[tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },2478	[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },2479	[tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },2480	[tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },2481	[tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },2482	[tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },2483	[tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },2484	[tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },2485	[tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },2486	[tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },2487	[tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },2488	[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },2489	[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },2490	[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },2491	[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },2492	[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },2493	[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },2494	[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },2495	[tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },2496	[tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },2497	[tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },2498	[tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },2499	[tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },2500	[tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },2501	[tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },2502	[tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },2503	[tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },2504	[tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },2505	[tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },2506	[tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },2507	[tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },2508	[tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },2509	[tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },2510	[tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },2511	[tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },2512	[tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },2513	[tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },2514	[tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },2515	[tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },2516	[tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },2517	[tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },2518	[tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },2519	[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },2520	[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },2521	[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },2522	[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },2523	[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },2524	[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },2525	[tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },2526	[tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },2527	[tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },2528	[tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },2529	[tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },2530	[tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },2531	[tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },2532	[tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },2533	[tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },2534	[tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },2535	[tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },2536	[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },2537	[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },2538	[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },2539	[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },2540	[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },2541	[tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },2542	[tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },2543	[tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },2544	[tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },2545	[tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },2546	[tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },2547	[tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },2548	[tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },2549	[tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },2550	[tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },2551	[tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },2552	[tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },2553	[tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },2554	[tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },2555	[tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },2556	[tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },2557	[tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },2558};2559 2560static struct tegra_devclk devclks[] __initdata = {2561	{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },2562	{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },2563	{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },2564	{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },2565	{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },2566	{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },2567	{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },2568	{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },2569	{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },2570	{ .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },2571	{ .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },2572	{ .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },2573	{ .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },2574	{ .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },2575	{ .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },2576	{ .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },2577	{ .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },2578	{ .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },2579	{ .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },2580	{ .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },2581	{ .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },2582	{ .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },2583	{ .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },2584	{ .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },2585	{ .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },2586	{ .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },2587	{ .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },2588	{ .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },2589	{ .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },2590	{ .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },2591	{ .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },2592	{ .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },2593	{ .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },2594	{ .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },2595	{ .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },2596	{ .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },2597	{ .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },2598	{ .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },2599	{ .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },2600	{ .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },2601	{ .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },2602	{ .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },2603	{ .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },2604	{ .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },2605	{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },2606	{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },2607	{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },2608	{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },2609	{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },2610	{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },2611	{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },2612	{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },2613	{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },2614	{ .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },2615	{ .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },2616	{ .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },2617	{ .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },2618	{ .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },2619	{ .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },2620	{ .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },2621	{ .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },2622	{ .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },2623	{ .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },2624};2625 2626static struct tegra_audio_clk_info tegra210_audio_plls[] = {2627	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },2628	{ "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },2629};2630 2631static const char * const aclk_parents[] = {2632	"pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",2633	"clk_m"2634};2635 2636static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };2637static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };2638static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,2639	TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };2640static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,2641	TEGRA210_CLK_HOST1X};2642static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,2643	TEGRA210_CLK_XUSB_DEV };2644static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,2645	TEGRA210_CLK_XUSB_SS };2646static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,2647	TEGRA210_CLK_XUSB_SS };2648static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,2649	TEGRA210_CLK_PLL_D };2650static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,2651	TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,2652	TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,2653	TEGRA210_CLK_D_AUDIO };2654static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };2655 2656static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {2657	[TEGRA_POWERGATE_VENC] = {2658		.handle_lvl2_ovr = tegra210_venc_mbist_war,2659		.num_clks = ARRAY_SIZE(venc_slcg_clkids),2660		.clk_init_data = venc_slcg_clkids,2661	},2662	[TEGRA_POWERGATE_SATA] = {2663		.handle_lvl2_ovr = tegra210_generic_mbist_war,2664		.lvl2_offset = LVL2_CLK_GATE_OVRC,2665		.lvl2_mask = BIT(0) | BIT(17) | BIT(19),2666	},2667	[TEGRA_POWERGATE_MPE] = {2668		.handle_lvl2_ovr = tegra210_generic_mbist_war,2669		.lvl2_offset = LVL2_CLK_GATE_OVRE,2670		.lvl2_mask = BIT(29),2671	},2672	[TEGRA_POWERGATE_SOR] = {2673		.handle_lvl2_ovr = tegra210_generic_mbist_war,2674		.num_clks = ARRAY_SIZE(sor_slcg_clkids),2675		.clk_init_data = sor_slcg_clkids,2676		.lvl2_offset = LVL2_CLK_GATE_OVRA,2677		.lvl2_mask = BIT(1) | BIT(2),2678	},2679	[TEGRA_POWERGATE_DIS] = {2680		.handle_lvl2_ovr = tegra210_disp_mbist_war,2681		.num_clks = ARRAY_SIZE(disp_slcg_clkids),2682		.clk_init_data = disp_slcg_clkids,2683	},2684	[TEGRA_POWERGATE_DISB] = {2685		.num_clks = ARRAY_SIZE(disp_slcg_clkids),2686		.clk_init_data = disp_slcg_clkids,2687		.handle_lvl2_ovr = tegra210_generic_mbist_war,2688		.lvl2_offset = LVL2_CLK_GATE_OVRA,2689		.lvl2_mask = BIT(2),2690	},2691	[TEGRA_POWERGATE_XUSBA] = {2692		.num_clks = ARRAY_SIZE(xusba_slcg_clkids),2693		.clk_init_data = xusba_slcg_clkids,2694		.handle_lvl2_ovr = tegra210_generic_mbist_war,2695		.lvl2_offset = LVL2_CLK_GATE_OVRC,2696		.lvl2_mask = BIT(30) | BIT(31),2697	},2698	[TEGRA_POWERGATE_XUSBB] = {2699		.num_clks = ARRAY_SIZE(xusbb_slcg_clkids),2700		.clk_init_data = xusbb_slcg_clkids,2701		.handle_lvl2_ovr = tegra210_generic_mbist_war,2702		.lvl2_offset = LVL2_CLK_GATE_OVRC,2703		.lvl2_mask = BIT(30) | BIT(31),2704	},2705	[TEGRA_POWERGATE_XUSBC] = {2706		.num_clks = ARRAY_SIZE(xusbc_slcg_clkids),2707		.clk_init_data = xusbc_slcg_clkids,2708		.handle_lvl2_ovr = tegra210_generic_mbist_war,2709		.lvl2_offset = LVL2_CLK_GATE_OVRC,2710		.lvl2_mask = BIT(30) | BIT(31),2711	},2712	[TEGRA_POWERGATE_VIC] = {2713		.num_clks = ARRAY_SIZE(vic_slcg_clkids),2714		.clk_init_data = vic_slcg_clkids,2715		.handle_lvl2_ovr = tegra210_vic_mbist_war,2716	},2717	[TEGRA_POWERGATE_NVDEC] = {2718		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),2719		.clk_init_data = nvdec_slcg_clkids,2720		.handle_lvl2_ovr = tegra210_generic_mbist_war,2721		.lvl2_offset = LVL2_CLK_GATE_OVRE,2722		.lvl2_mask = BIT(9) | BIT(31),2723	},2724	[TEGRA_POWERGATE_NVJPG] = {2725		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),2726		.clk_init_data = nvjpg_slcg_clkids,2727		.handle_lvl2_ovr = tegra210_generic_mbist_war,2728		.lvl2_offset = LVL2_CLK_GATE_OVRE,2729		.lvl2_mask = BIT(9) | BIT(31),2730	},2731	[TEGRA_POWERGATE_AUD] = {2732		.num_clks = ARRAY_SIZE(ape_slcg_clkids),2733		.clk_init_data = ape_slcg_clkids,2734		.handle_lvl2_ovr = tegra210_ape_mbist_war,2735	},2736	[TEGRA_POWERGATE_VE2] = {2737		.handle_lvl2_ovr = tegra210_generic_mbist_war,2738		.lvl2_offset = LVL2_CLK_GATE_OVRD,2739		.lvl2_mask = BIT(22),2740	},2741};2742 2743int tegra210_clk_handle_mbist_war(unsigned int id)2744{2745	int err;2746	struct tegra210_domain_mbist_war *mbist_war;2747 2748	if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {2749		WARN(1, "unknown domain id in MBIST WAR handler\n");2750		return -EINVAL;2751	}2752 2753	mbist_war = &tegra210_pg_mbist_war[id];2754	if (!mbist_war->handle_lvl2_ovr)2755		return 0;2756 2757	if (mbist_war->num_clks && !mbist_war->clks)2758		return -ENODEV;2759 2760	err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);2761	if (err < 0)2762		return err;2763 2764	mutex_lock(&lvl2_ovr_lock);2765 2766	mbist_war->handle_lvl2_ovr(mbist_war);2767 2768	mutex_unlock(&lvl2_ovr_lock);2769 2770	clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);2771 2772	return 0;2773}2774 2775void tegra210_put_utmipll_in_iddq(void)2776{2777	u32 reg;2778 2779	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2780 2781	if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {2782		pr_err("trying to assert IDDQ while UTMIPLL is locked\n");2783		return;2784	}2785 2786	reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;2787	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);2788}2789EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);2790 2791void tegra210_put_utmipll_out_iddq(void)2792{2793	u32 reg;2794 2795	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2796	reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;2797	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);2798}2799EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);2800 2801static void tegra210_utmi_param_configure(void)2802{2803	u32 reg;2804	int i;2805 2806	for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {2807		if (osc_freq == utmi_parameters[i].osc_frequency)2808			break;2809	}2810 2811	if (i >= ARRAY_SIZE(utmi_parameters)) {2812		pr_err("%s: Unexpected oscillator freq %lu\n", __func__,2813			osc_freq);2814		return;2815	}2816 2817	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2818	reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;2819	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);2820 2821	udelay(10);2822 2823	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);2824 2825	/* Program UTMIP PLL stable and active counts */2826	/* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */2827	reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);2828	reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);2829 2830	reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);2831	reg |=2832	UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);2833	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);2834 2835	/* Program UTMIP PLL delay and oscillator frequency counts */2836	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);2837 2838	reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);2839	reg |=2840	UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);2841 2842	reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);2843	reg |=2844	UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);2845 2846	reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;2847	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);2848 2849	/* Remove power downs from UTMIP PLL control bits */2850	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);2851	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;2852	reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;2853	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);2854 2855	udelay(20);2856 2857	/* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */2858	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);2859	reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;2860	reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;2861	reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;2862	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;2863	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;2864	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;2865	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);2866 2867	/* Setup HW control of UTMIPLL */2868	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);2869	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;2870	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;2871	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);2872 2873	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2874	reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;2875	reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;2876	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);2877 2878	udelay(1);2879 2880	reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);2881	reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;2882	writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);2883 2884	udelay(1);2885 2886	/* Enable HW control UTMIPLL */2887	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2888	reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;2889	writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);2890}2891 2892static int tegra210_enable_pllu(void)2893{2894	struct tegra_clk_pll_freq_table *fentry;2895	struct tegra_clk_pll pllu;2896	u32 reg;2897	int ret;2898 2899	for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {2900		if (fentry->input_rate == pll_ref_freq)2901			break;2902	}2903 2904	if (!fentry->input_rate) {2905		pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);2906		return -EINVAL;2907	}2908 2909	/* clear IDDQ bit */2910	pllu.params = &pll_u_vco_params;2911	reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);2912	reg &= ~BIT(pllu.params->iddq_bit_idx);2913	writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);2914	fence_udelay(5, clk_base);2915 2916	reg = readl_relaxed(clk_base + PLLU_BASE);2917	reg &= ~GENMASK(20, 0);2918	reg |= fentry->m;2919	reg |= fentry->n << 8;2920	reg |= fentry->p << 16;2921	writel(reg, clk_base + PLLU_BASE);2922	fence_udelay(1, clk_base);2923	reg |= PLL_ENABLE;2924	writel(reg, clk_base + PLLU_BASE);2925 2926	/*2927	 * During clocks resume, same PLLU init and enable sequence get2928	 * executed. So, readx_poll_timeout_atomic can't be used here as it2929	 * uses ktime_get() and timekeeping resume doesn't happen by that2930	 * time. So, using tegra210_wait_for_mask for PLL LOCK.2931	 */2932	ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);2933	if (ret) {2934		pr_err("Timed out waiting for PLL_U to lock\n");2935		return -ETIMEDOUT;2936	}2937 2938	return 0;2939}2940 2941static int tegra210_init_pllu(void)2942{2943	u32 reg;2944	int err;2945 2946	tegra210_pllu_set_defaults(&pll_u_vco_params);2947	/* skip initialization when pllu is in hw controlled mode */2948	reg = readl_relaxed(clk_base + PLLU_BASE);2949	if (reg & PLLU_BASE_OVERRIDE) {2950		if (!(reg & PLL_ENABLE)) {2951			err = tegra210_enable_pllu();2952			if (err < 0) {2953				WARN_ON(1);2954				return err;2955			}2956		}2957		/* enable hw controlled mode */2958		reg = readl_relaxed(clk_base + PLLU_BASE);2959		reg &= ~PLLU_BASE_OVERRIDE;2960		writel(reg, clk_base + PLLU_BASE);2961 2962		reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);2963		reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |2964		       PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |2965		       PLLU_HW_PWRDN_CFG0_USE_LOCKDET;2966		reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |2967			PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);2968		writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);2969 2970		reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);2971		reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;2972		writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);2973		fence_udelay(1, clk_base);2974 2975		reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);2976		reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;2977		writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);2978		fence_udelay(1, clk_base);2979 2980		reg = readl_relaxed(clk_base + PLLU_BASE);2981		reg &= ~PLLU_BASE_CLKENABLE_USB;2982		writel_relaxed(reg, clk_base + PLLU_BASE);2983	}2984 2985	/* enable UTMIPLL hw control if not yet done by the bootloader */2986	reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);2987	if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))2988		tegra210_utmi_param_configure();2989 2990	return 0;2991}2992 2993/*2994 * The SOR hardware blocks are driven by two clocks: a module clock that is2995 * used to access registers and a pixel clock that is sourced from the same2996 * pixel clock that also drives the head attached to the SOR. The module2997 * clock is typically called sorX (with X being the SOR instance) and the2998 * pixel clock is called sorX_out. The source for the SOR pixel clock is2999 * referred to as the "parent" clock.3000 *3001 * On Tegra186 and newer, clocks are provided by the BPMP. Unfortunately the3002 * BPMP implementation for the SOR clocks doesn't exactly match the above in3003 * some aspects. For example, the SOR module is really clocked by the pad or3004 * sor_safe clocks, but BPMP models the sorX clock as being sourced by the3005 * pixel clocks. Conversely the sorX_out clock is sourced by the sor_safe or3006 * pad clocks on BPMP.3007 *3008 * In order to allow the display driver to deal with all SoC generations in3009 * a unified way, implement the BPMP semantics in this driver.3010 */3011 3012static const char * const sor0_parents[] = {3013	"pll_d_out0",3014};3015 3016static const char * const sor0_out_parents[] = {3017	"sor_safe", "sor0_pad_clkout",3018};3019 3020static const char * const sor1_parents[] = {3021	"pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",3022};3023 3024static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };3025 3026static const struct clk_div_table mc_div_table_tegra210[] = {3027	{ .val = 0, .div = 2 },3028	{ .val = 1, .div = 4 },3029	{ .val = 2, .div = 1 },3030	{ .val = 3, .div = 2 },3031	{ .val = 0, .div = 0 },3032};3033 3034static void tegra210_clk_register_mc(const char *name,3035				     const char *parent_name)3036{3037	struct clk *clk;3038 3039	clk = clk_register_divider_table(NULL, name, parent_name,3040					 CLK_IS_CRITICAL,3041					 clk_base + CLK_SOURCE_EMC,3042					 15, 2, CLK_DIVIDER_READ_ONLY,3043					 mc_div_table_tegra210, &emc_lock);3044	clks[TEGRA210_CLK_MC] = clk;3045}3046 3047static const char * const sor1_out_parents[] = {3048	/*3049	 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so3050	 * the sor1_pad_clkout parent appears twice in the list below. This is3051	 * merely to support clk_get_parent() if firmware happened to set3052	 * these bits to 0b11. While not an invalid setting, code should3053	 * always set the bits to 0b01 to select sor1_pad_clkout.3054	 */3055	"sor_safe", "sor1_pad_clkout", "sor1_out", "sor1_pad_clkout",3056};3057 3058static struct tegra_periph_init_data tegra210_periph[] = {3059	/*3060	 * On Tegra210, the sor0 clock doesn't have a mux it bitfield 31:29,3061	 * but it is hardwired to the pll_d_out0 clock.3062	 */3063	TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,3064			      CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0,3065			      0, 182, 0, tegra_clk_sor0, NULL, 0,3066			      &sor0_lock),3067	TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,3068			      CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,3069			      0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,3070			      NULL, 0, &sor0_lock),3071	TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,3072			      CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,3073			      TEGRA_DIVIDER_ROUND_UP, 183, 0,3074			      tegra_clk_sor1, sor1_parents_idx, 0,3075			      &sor1_lock),3076	TEGRA_INIT_DATA_TABLE("sor1_out", NULL, NULL, sor1_out_parents,3077			      CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0,3078			      0, 0, TEGRA_PERIPH_NO_GATE,3079			      tegra_clk_sor1_out, NULL, 0, &sor1_lock),3080};3081 3082static const char * const la_parents[] = {3083	"pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"3084};3085 3086static struct tegra_clk_periph tegra210_la =3087	TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);3088 3089static __init void tegra210_periph_clk_init(struct device_node *np,3090					    void __iomem *clk_base,3091					    void __iomem *pmc_base)3092{3093	struct clk *clk;3094	unsigned int i;3095 3096	/* xusb_ss_div2 */3097	clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,3098					1, 2);3099	clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;3100 3101	clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,3102					      1, 17, 222);3103	clks[TEGRA210_CLK_SOR_SAFE] = clk;3104 3105	clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,3106					      1, 17, 181);3107	clks[TEGRA210_CLK_DPAUX] = clk;3108 3109	clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,3110					      1, 17, 207);3111	clks[TEGRA210_CLK_DPAUX1] = clk;3112 3113	/* pll_d_dsi_out */3114	clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,3115				clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);3116	clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;3117 3118	/* dsia */3119	clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,3120					     clk_base, 0, 48,3121					     periph_clk_enb_refcnt);3122	clks[TEGRA210_CLK_DSIA] = clk;3123 3124	/* dsib */3125	clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,3126					     clk_base, 0, 82,3127					     periph_clk_enb_refcnt);3128	clks[TEGRA210_CLK_DSIB] = clk;3129 3130	/* csi_tpg */3131	clk = clk_register_gate(NULL, "csi_tpg", "pll_d",3132				CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,3133				23, 0, &pll_d_lock);3134	clk_register_clkdev(clk, "csi_tpg", NULL);3135	clks[TEGRA210_CLK_CSI_TPG] = clk;3136 3137	/* la */3138	clk = tegra_clk_register_periph("la", la_parents,3139			ARRAY_SIZE(la_parents), &tegra210_la, clk_base,3140			CLK_SOURCE_LA, 0);3141	clks[TEGRA210_CLK_LA] = clk;3142 3143	/* cml0 */3144	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,3145				0, 0, &pll_e_lock);3146	clk_register_clkdev(clk, "cml0", NULL);3147	clks[TEGRA210_CLK_CML0] = clk;3148 3149	/* cml1 */3150	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,3151				1, 0, &pll_e_lock);3152	clk_register_clkdev(clk, "cml1", NULL);3153	clks[TEGRA210_CLK_CML1] = clk;3154 3155	clk = tegra_clk_register_super_clk("aclk", aclk_parents,3156				ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,3157				0, NULL);3158	clks[TEGRA210_CLK_ACLK] = clk;3159 3160	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,3161					    CLK_SOURCE_SDMMC2, 9,3162					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);3163	clks[TEGRA210_CLK_SDMMC2] = clk;3164 3165	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,3166					    CLK_SOURCE_SDMMC4, 15,3167					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);3168	clks[TEGRA210_CLK_SDMMC4] = clk;3169 3170	for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {3171		struct tegra_periph_init_data *init = &tegra210_periph[i];3172		struct clk **clkp;3173 3174		clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);3175		if (!clkp) {3176			pr_warn("clock %u not found\n", init->clk_id);3177			continue;3178		}3179 3180		clk = tegra_clk_register_periph_data(clk_base, init);3181		*clkp = clk;3182	}3183 3184	tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);3185 3186	/* emc */3187	clk = tegra210_clk_register_emc(np, clk_base);3188	clks[TEGRA210_CLK_EMC] = clk;3189 3190	/* mc */3191	tegra210_clk_register_mc("mc", "emc");3192}3193 3194static void __init tegra210_pll_init(void __iomem *clk_base,3195				     void __iomem *pmc)3196{3197	struct clk *clk;3198 3199	/* PLLC */3200	clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,3201			pmc, 0, &pll_c_params, NULL);3202	if (!WARN_ON(IS_ERR(clk)))3203		clk_register_clkdev(clk, "pll_c", NULL);3204	clks[TEGRA210_CLK_PLL_C] = clk;3205 3206	/* PLLC_OUT1 */3207	clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",3208			clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,3209			8, 8, 1, NULL);3210	clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",3211				clk_base + PLLC_OUT, 1, 0,3212				CLK_SET_RATE_PARENT, 0, NULL);3213	clk_register_clkdev(clk, "pll_c_out1", NULL);3214	clks[TEGRA210_CLK_PLL_C_OUT1] = clk;3215 3216	/* PLLC_UD */3217	clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",3218					CLK_SET_RATE_PARENT, 1, 1);3219	clk_register_clkdev(clk, "pll_c_ud", NULL);3220	clks[TEGRA210_CLK_PLL_C_UD] = clk;3221 3222	/* PLLC2 */3223	clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,3224			     pmc, 0, &pll_c2_params, NULL);3225	clk_register_clkdev(clk, "pll_c2", NULL);3226	clks[TEGRA210_CLK_PLL_C2] = clk;3227 3228	/* PLLC3 */3229	clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,3230			     pmc, 0, &pll_c3_params, NULL);3231	clk_register_clkdev(clk, "pll_c3", NULL);3232	clks[TEGRA210_CLK_PLL_C3] = clk;3233 3234	/* PLLM */3235	clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,3236			     CLK_SET_RATE_GATE, &pll_m_params, NULL);3237	clk_register_clkdev(clk, "pll_m", NULL);3238	clks[TEGRA210_CLK_PLL_M] = clk;3239 3240	/* PLLMB */3241	clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,3242			     CLK_SET_RATE_GATE, &pll_mb_params, NULL);3243	clk_register_clkdev(clk, "pll_mb", NULL);3244	clks[TEGRA210_CLK_PLL_MB] = clk;3245 3246	/* PLLM_UD */3247	clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",3248					CLK_SET_RATE_PARENT, 1, 1);3249	clk_register_clkdev(clk, "pll_m_ud", NULL);3250	clks[TEGRA210_CLK_PLL_M_UD] = clk;3251 3252	/* PLLMB_UD */3253	clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb",3254					CLK_SET_RATE_PARENT, 1, 1);3255	clk_register_clkdev(clk, "pll_mb_ud", NULL);3256	clks[TEGRA210_CLK_PLL_MB_UD] = clk;3257 3258	/* PLLP_UD */3259	clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p",3260					0, 1, 1);3261	clks[TEGRA210_CLK_PLL_P_UD] = clk;3262 3263	/* PLLU_VCO */3264	if (!tegra210_init_pllu()) {3265		clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,3266					      480*1000*1000);3267		clk_register_clkdev(clk, "pll_u_vco", NULL);3268		clks[TEGRA210_CLK_PLL_U] = clk;3269	}3270 3271	/* PLLU_OUT */3272	clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,3273					 clk_base + PLLU_BASE, 16, 4, 0,3274					 pll_vco_post_div_table, NULL);3275	clk_register_clkdev(clk, "pll_u_out", NULL);3276	clks[TEGRA210_CLK_PLL_U_OUT] = clk;3277 3278	/* PLLU_OUT1 */3279	clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",3280				clk_base + PLLU_OUTA, 0,3281				TEGRA_DIVIDER_ROUND_UP,3282				8, 8, 1, &pll_u_lock);3283	clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",3284				clk_base + PLLU_OUTA, 1, 0,3285				CLK_SET_RATE_PARENT, 0, &pll_u_lock);3286	clk_register_clkdev(clk, "pll_u_out1", NULL);3287	clks[TEGRA210_CLK_PLL_U_OUT1] = clk;3288 3289	/* PLLU_OUT2 */3290	clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",3291				clk_base + PLLU_OUTA, 0,3292				TEGRA_DIVIDER_ROUND_UP,3293				24, 8, 1, &pll_u_lock);3294	clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",3295				clk_base + PLLU_OUTA, 17, 16,3296				CLK_SET_RATE_PARENT, 0, &pll_u_lock);3297	clk_register_clkdev(clk, "pll_u_out2", NULL);3298	clks[TEGRA210_CLK_PLL_U_OUT2] = clk;3299 3300	/* PLLU_480M */3301	clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",3302				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,3303				22, 0, &pll_u_lock);3304	clk_register_clkdev(clk, "pll_u_480M", NULL);3305	clks[TEGRA210_CLK_PLL_U_480M] = clk;3306 3307	/* PLLU_60M */3308	clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",3309				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,3310				23, 0, &pll_u_lock);3311	clk_register_clkdev(clk, "pll_u_60M", NULL);3312	clks[TEGRA210_CLK_PLL_U_60M] = clk;3313 3314	/* PLLU_48M */3315	clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",3316				CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,3317				25, 0, &pll_u_lock);3318	clk_register_clkdev(clk, "pll_u_48M", NULL);3319	clks[TEGRA210_CLK_PLL_U_48M] = clk;3320 3321	/* PLLD */3322	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,3323			    &pll_d_params, &pll_d_lock);3324	clk_register_clkdev(clk, "pll_d", NULL);3325	clks[TEGRA210_CLK_PLL_D] = clk;3326 3327	/* PLLD_OUT0 */3328	clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",3329					CLK_SET_RATE_PARENT, 1, 2);3330	clk_register_clkdev(clk, "pll_d_out0", NULL);3331	clks[TEGRA210_CLK_PLL_D_OUT0] = clk;3332 3333	/* PLLRE */3334	clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",3335						clk_base, pmc, 0,3336						&pll_re_vco_params,3337						&pll_re_lock, pll_ref_freq);3338	clk_register_clkdev(clk, "pll_re_vco", NULL);3339	clks[TEGRA210_CLK_PLL_RE_VCO] = clk;3340 3341	clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,3342					 clk_base + PLLRE_BASE, 16, 5, 0,3343					 pll_vco_post_div_table, &pll_re_lock);3344	clk_register_clkdev(clk, "pll_re_out", NULL);3345	clks[TEGRA210_CLK_PLL_RE_OUT] = clk;3346 3347	clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",3348					 clk_base + PLLRE_OUT1, 0,3349					 TEGRA_DIVIDER_ROUND_UP,3350					 8, 8, 1, NULL);3351	clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",3352					 clk_base + PLLRE_OUT1, 1, 0,3353					 CLK_SET_RATE_PARENT, 0, NULL);3354	clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;3355 3356	/* PLLE */3357	clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",3358				      clk_base, 0, &pll_e_params, NULL);3359	clk_register_clkdev(clk, "pll_e", NULL);3360	clks[TEGRA210_CLK_PLL_E] = clk;3361 3362	/* PLLC4 */3363	clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,3364			     0, &pll_c4_vco_params, NULL, pll_ref_freq);3365	clk_register_clkdev(clk, "pll_c4_vco", NULL);3366	clks[TEGRA210_CLK_PLL_C4] = clk;3367 3368	/* PLLC4_OUT0 */3369	clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,3370					 clk_base + PLLC4_BASE, 19, 4, 0,3371					 pll_vco_post_div_table, NULL);3372	clk_register_clkdev(clk, "pll_c4_out0", NULL);3373	clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;3374 3375	/* PLLC4_OUT1 */3376	clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",3377					CLK_SET_RATE_PARENT, 1, 3);3378	clk_register_clkdev(clk, "pll_c4_out1", NULL);3379	clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;3380 3381	/* PLLC4_OUT2 */3382	clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",3383					CLK_SET_RATE_PARENT, 1, 5);3384	clk_register_clkdev(clk, "pll_c4_out2", NULL);3385	clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;3386 3387	/* PLLC4_OUT3 */3388	clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",3389			clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,3390			8, 8, 1, NULL);3391	clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",3392				clk_base + PLLC4_OUT, 1, 0,3393				CLK_SET_RATE_PARENT, 0, NULL);3394	clk_register_clkdev(clk, "pll_c4_out3", NULL);3395	clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;3396 3397	/* PLLDP */3398	clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,3399					0, &pll_dp_params, NULL);3400	clk_register_clkdev(clk, "pll_dp", NULL);3401	clks[TEGRA210_CLK_PLL_DP] = clk;3402 3403	/* PLLD2 */3404	clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,3405					0, &pll_d2_params, NULL);3406	clk_register_clkdev(clk, "pll_d2", NULL);3407	clks[TEGRA210_CLK_PLL_D2] = clk;3408 3409	/* PLLD2_OUT0 */3410	clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",3411					CLK_SET_RATE_PARENT, 1, 1);3412	clk_register_clkdev(clk, "pll_d2_out0", NULL);3413	clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;3414 3415	/* PLLP_OUT2 */3416	clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",3417					CLK_SET_RATE_PARENT, 1, 2);3418	clk_register_clkdev(clk, "pll_p_out2", NULL);3419	clks[TEGRA210_CLK_PLL_P_OUT2] = clk;3420 3421}3422 3423/* Tegra210 CPU clock and reset control functions */3424static void tegra210_wait_cpu_in_reset(u32 cpu)3425{3426	unsigned int reg;3427 3428	do {3429		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);3430		cpu_relax();3431	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */3432}3433 3434static void tegra210_disable_cpu_clock(u32 cpu)3435{3436	/* flow controller would take care in the power sequence. */3437}3438 3439#ifdef CONFIG_PM_SLEEP3440#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))3441#define car_writel(_val, _base, _off) \3442		writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))3443 3444static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;3445static u32 cpu_softrst_ctx[3];3446 3447static int tegra210_clk_suspend(void)3448{3449	unsigned int i;3450 3451	clk_save_context();3452 3453	/*3454	 * Save the bootloader configured clock registers SPARE_REG0,3455	 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL.3456	 */3457	spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);3458	misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);3459	clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);3460 3461	for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)3462		cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);3463 3464	tegra_clk_periph_suspend();3465	return 0;3466}3467 3468static void tegra210_clk_resume(void)3469{3470	unsigned int i;3471 3472	tegra_clk_osc_resume(clk_base);3473 3474	/*3475	 * Restore the bootloader configured clock registers SPARE_REG0,3476	 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.3477	 */3478	writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);3479	writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);3480	writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);3481 3482	for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)3483		car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);3484 3485	/*3486	 * Tegra clock programming sequence recommends peripheral clock to3487	 * be enabled prior to changing its clock source and divider to3488	 * prevent glitchless frequency switch.3489	 * So, enable all peripheral clocks before restoring their source3490	 * and dividers.3491	 */3492	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);3493	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);3494	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);3495	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);3496	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);3497	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);3498	writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);3499 3500	/* wait for all writes to happen to have all the clocks enabled */3501	fence_udelay(2, clk_base);3502 3503	/* restore PLLs and all peripheral clock rates */3504	tegra210_init_pllu();3505	clk_restore_context();3506 3507	/* restore saved context of peripheral clocks and reset state */3508	tegra_clk_periph_resume();3509}3510 3511static void tegra210_cpu_clock_suspend(void)3512{3513	/* switch coresite to clk_m, save off original source */3514	tegra210_cpu_clk_sctx.clk_csite_src =3515				readl(clk_base + CLK_SOURCE_CSITE);3516	writel(3 << 30, clk_base + CLK_SOURCE_CSITE);3517}3518 3519static void tegra210_cpu_clock_resume(void)3520{3521	writel(tegra210_cpu_clk_sctx.clk_csite_src,3522				clk_base + CLK_SOURCE_CSITE);3523}3524#endif3525 3526static struct syscore_ops tegra_clk_syscore_ops = {3527#ifdef CONFIG_PM_SLEEP3528	.suspend = tegra210_clk_suspend,3529	.resume = tegra210_clk_resume,3530#endif3531};3532 3533static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {3534	.wait_for_reset	= tegra210_wait_cpu_in_reset,3535	.disable_clock	= tegra210_disable_cpu_clock,3536#ifdef CONFIG_PM_SLEEP3537	.suspend	= tegra210_cpu_clock_suspend,3538	.resume		= tegra210_cpu_clock_resume,3539#endif3540};3541 3542static const struct of_device_id pmc_match[] __initconst = {3543	{ .compatible = "nvidia,tegra210-pmc" },3544	{ },3545};3546 3547static struct tegra_clk_init_table init_table[] __initdata = {3548	{ TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },3549	{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },3550	{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },3551	{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },3552	{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },3553	{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },3554	{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },3555	{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },3556	{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },3557	{ TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },3558	{ TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },3559	{ TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },3560	{ TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },3561	{ TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },3562	{ TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },3563	{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },3564	{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },3565	{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },3566	{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },3567	{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },3568	{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },3569	{ TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },3570	{ TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },3571	{ TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },3572	{ TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },3573	{ TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },3574	{ TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },3575	{ TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },3576	{ TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },3577	{ TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },3578	/* TODO find a way to enable this on-demand */3579	{ TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },3580	{ TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },3581	{ TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },3582	{ TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },3583	{ TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },3584	{ TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },3585	{ TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },3586	{ TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },3587	{ TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },3588	{ TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },3589	{ TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },3590	{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },3591	{ TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3592	{ TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3593	{ TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3594	{ TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3595	{ TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3596	{ TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3597	{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },3598	{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },3599	{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },3600	{ TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 },3601	/* This MUST be the last entry. */3602	{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },3603};3604 3605/**3606 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs3607 *3608 * Program an initial clock rate and enable or disable clocks needed3609 * by the rest of the kernel, for Tegra210 SoCs.  It is intended to be3610 * called by assigning a pointer to it to tegra_clk_apply_init_table -3611 * this will be called as an arch_initcall.  No return value.3612 */3613static void __init tegra210_clock_apply_init_table(void)3614{3615	tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);3616}3617 3618/**3619 * tegra210_car_barrier - wait for pending writes to the CAR to complete3620 *3621 * Wait for any outstanding writes to the CAR MMIO space from this CPU3622 * to complete before continuing execution.  No return value.3623 */3624static void tegra210_car_barrier(void)3625{3626	readl_relaxed(clk_base + RST_DFLL_DVCO);3627}3628 3629/**3630 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset3631 *3632 * Assert the reset line of the DFLL's DVCO.  No return value.3633 */3634static void tegra210_clock_assert_dfll_dvco_reset(void)3635{3636	u32 v;3637 3638	v = readl_relaxed(clk_base + RST_DFLL_DVCO);3639	v |= (1 << DVFS_DFLL_RESET_SHIFT);3640	writel_relaxed(v, clk_base + RST_DFLL_DVCO);3641	tegra210_car_barrier();3642}3643 3644/**3645 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset3646 *3647 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to3648 * operate.  No return value.3649 */3650static void tegra210_clock_deassert_dfll_dvco_reset(void)3651{3652	u32 v;3653 3654	v = readl_relaxed(clk_base + RST_DFLL_DVCO);3655	v &= ~(1 << DVFS_DFLL_RESET_SHIFT);3656	writel_relaxed(v, clk_base + RST_DFLL_DVCO);3657	tegra210_car_barrier();3658}3659 3660static int tegra210_reset_assert(unsigned long id)3661{3662	if (id == TEGRA210_RST_DFLL_DVCO)3663		tegra210_clock_assert_dfll_dvco_reset();3664	else if (id == TEGRA210_RST_ADSP)3665		writel(GENMASK(26, 21) | BIT(7),3666			clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);3667	else3668		return -EINVAL;3669 3670	return 0;3671}3672 3673static int tegra210_reset_deassert(unsigned long id)3674{3675	if (id == TEGRA210_RST_DFLL_DVCO)3676		tegra210_clock_deassert_dfll_dvco_reset();3677	else if (id == TEGRA210_RST_ADSP) {3678		writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);3679		/*3680		 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)3681		 * a delay of 5us ensures that it's at least3682		 * 6 * adsp_cpu_cycle_period long.3683		 */3684		udelay(5);3685		writel(GENMASK(26, 22) | BIT(7),3686			clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);3687	} else3688		return -EINVAL;3689 3690	return 0;3691}3692 3693static void tegra210_mbist_clk_init(void)3694{3695	unsigned int i, j;3696 3697	for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {3698		unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;3699		struct clk_bulk_data *clk_data;3700 3701		if (!num_clks)3702			continue;3703 3704		clk_data = kmalloc_array(num_clks, sizeof(*clk_data),3705					 GFP_KERNEL);3706		if (WARN_ON(!clk_data))3707			return;3708 3709		tegra210_pg_mbist_war[i].clks = clk_data;3710		for (j = 0; j < num_clks; j++) {3711			int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];3712			struct clk *clk = clks[clk_id];3713 3714			if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {3715				kfree(clk_data);3716				tegra210_pg_mbist_war[i].clks = NULL;3717				break;3718			}3719			clk_data[j].clk = clk;3720		}3721	}3722}3723 3724/**3725 * tegra210_clock_init - Tegra210-specific clock initialization3726 * @np: struct device_node * of the DT node for the SoC CAR IP block3727 *3728 * Register most SoC clocks for the Tegra210 system-on-chip.  Intended3729 * to be called by the OF init code when a DT node with the3730 * "nvidia,tegra210-car" string is encountered, and declared with3731 * CLK_OF_DECLARE.  No return value.3732 */3733static void __init tegra210_clock_init(struct device_node *np)3734{3735	struct device_node *node;3736	u32 value, clk_m_div;3737 3738	clk_base = of_iomap(np, 0);3739	if (!clk_base) {3740		pr_err("ioremap tegra210 CAR failed\n");3741		return;3742	}3743 3744	node = of_find_matching_node(NULL, pmc_match);3745	if (!node) {3746		pr_err("Failed to find pmc node\n");3747		WARN_ON(1);3748		return;3749	}3750 3751	pmc_base = of_iomap(node, 0);3752	of_node_put(node);3753	if (!pmc_base) {3754		pr_err("Can't map pmc registers\n");3755		WARN_ON(1);3756		return;3757	}3758 3759	ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);3760	if (!ahub_base) {3761		pr_err("ioremap tegra210 APE failed\n");3762		return;3763	}3764 3765	dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);3766	if (!dispa_base) {3767		pr_err("ioremap tegra210 DISPA failed\n");3768		return;3769	}3770 3771	vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);3772	if (!vic_base) {3773		pr_err("ioremap tegra210 VIC failed\n");3774		return;3775	}3776 3777	clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,3778			      TEGRA210_CAR_BANK_COUNT);3779	if (!clks)3780		return;3781 3782	value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;3783	clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;3784 3785	if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,3786			       ARRAY_SIZE(tegra210_input_freq), clk_m_div,3787			       &osc_freq, &pll_ref_freq) < 0)3788		return;3789 3790	tegra_fixed_clk_init(tegra210_clks);3791	tegra210_pll_init(clk_base, pmc_base);3792	tegra210_periph_clk_init(np, clk_base, pmc_base);3793	tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,3794			     tegra210_audio_plls,3795			     ARRAY_SIZE(tegra210_audio_plls), 24576000);3796 3797	/* For Tegra210, PLLD is the only source for DSIA & DSIB */3798	value = readl(clk_base + PLLD_BASE);3799	value &= ~BIT(25);3800	writel(value, clk_base + PLLD_BASE);3801 3802	tegra_clk_apply_init_table = tegra210_clock_apply_init_table;3803 3804	tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,3805				  &pll_x_params);3806	tegra_init_special_resets(2, tegra210_reset_assert,3807				  tegra210_reset_deassert);3808 3809	tegra_add_of_provider(np, of_clk_src_onecell_get);3810	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));3811 3812	tegra210_mbist_clk_init();3813 3814	tegra_cpu_car_ops = &tegra210_cpu_car_ops;3815 3816	register_syscore_ops(&tegra_clk_syscore_ops);3817}3818CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);3819