1422 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.4 */5 6#include <linux/io.h>7#include <linux/delay.h>8#include <linux/clk-provider.h>9#include <linux/clkdev.h>10#include <linux/init.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/platform_device.h>14#include <linux/clk/tegra.h>15 16#include <soc/tegra/pmc.h>17 18#include <dt-bindings/clock/tegra30-car.h>19 20#include "clk.h"21#include "clk-id.h"22 23#define OSC_CTRL 0x5024#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)25#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)26#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)27#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)28#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)29#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)30#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)31#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)32#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)33 34#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)35#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)36#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)37#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)38 39#define OSC_FREQ_DET 0x5840#define OSC_FREQ_DET_TRIG BIT(31)41 42#define OSC_FREQ_DET_STATUS 0x5c43#define OSC_FREQ_DET_BUSY BIT(31)44#define OSC_FREQ_DET_CNT_MASK 0xffff45 46#define CCLKG_BURST_POLICY 0x36847#define SUPER_CCLKG_DIVIDER 0x36c48#define CCLKLP_BURST_POLICY 0x37049#define SUPER_CCLKLP_DIVIDER 0x37450#define SCLK_BURST_POLICY 0x02851#define SUPER_SCLK_DIVIDER 0x02c52 53#define SYSTEM_CLK_RATE 0x03054 55#define TEGRA30_CLK_PERIPH_BANKS 556 57#define PLLC_BASE 0x8058#define PLLC_MISC 0x8c59#define PLLM_BASE 0x9060#define PLLM_MISC 0x9c61#define PLLP_BASE 0xa062#define PLLP_MISC 0xac63#define PLLX_BASE 0xe064#define PLLX_MISC 0xe465#define PLLD_BASE 0xd066#define PLLD_MISC 0xdc67#define PLLD2_BASE 0x4b868#define PLLD2_MISC 0x4bc69#define PLLE_BASE 0xe870#define PLLE_MISC 0xec71#define PLLA_BASE 0xb072#define PLLA_MISC 0xbc73#define PLLU_BASE 0xc074#define PLLU_MISC 0xcc75 76#define PLL_MISC_LOCK_ENABLE 1877#define PLLDU_MISC_LOCK_ENABLE 2278#define PLLE_MISC_LOCK_ENABLE 979 80#define PLL_BASE_LOCK BIT(27)81#define PLLE_MISC_LOCK BIT(11)82 83#define PLLE_AUX 0x48c84#define PLLC_OUT 0x8485#define PLLM_OUT 0x9486#define PLLP_OUTA 0xa487#define PLLP_OUTB 0xa888#define PLLA_OUT 0xb489 90#define AUDIO_SYNC_CLK_I2S0 0x4a091#define AUDIO_SYNC_CLK_I2S1 0x4a492#define AUDIO_SYNC_CLK_I2S2 0x4a893#define AUDIO_SYNC_CLK_I2S3 0x4ac94#define AUDIO_SYNC_CLK_I2S4 0x4b095#define AUDIO_SYNC_CLK_SPDIF 0x4b496 97#define CLK_SOURCE_SPDIF_OUT 0x10898#define CLK_SOURCE_PWM 0x11099#define CLK_SOURCE_D_AUDIO 0x3d0100#define CLK_SOURCE_DAM0 0x3d8101#define CLK_SOURCE_DAM1 0x3dc102#define CLK_SOURCE_DAM2 0x3e0103#define CLK_SOURCE_3D2 0x3b0104#define CLK_SOURCE_2D 0x15c105#define CLK_SOURCE_HDMI 0x18c106#define CLK_SOURCE_DSIB 0xd0107#define CLK_SOURCE_SE 0x42c108#define CLK_SOURCE_EMC 0x19c109 110#define AUDIO_SYNC_DOUBLER 0x49c111 112/* Tegra CPU clock and reset control regs */113#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c114#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340115#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344116#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c117#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470118 119#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))120#define CPU_RESET(cpu) (0x1111ul << (cpu))121 122#define CLK_RESET_CCLK_BURST 0x20123#define CLK_RESET_CCLK_DIVIDER 0x24124#define CLK_RESET_PLLX_BASE 0xe0125#define CLK_RESET_PLLX_MISC 0xe4126 127#define CLK_RESET_SOURCE_CSITE 0x1d4128 129#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28130#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4131#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0132#define CLK_RESET_CCLK_IDLE_POLICY 1133#define CLK_RESET_CCLK_RUN_POLICY 2134#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8135 136/* PLLM override registers */137#define PMC_PLLM_WB0_OVERRIDE 0x1dc138 139#ifdef CONFIG_PM_SLEEP140static struct cpu_clk_suspend_context {141 u32 pllx_misc;142 u32 pllx_base;143 144 u32 cpu_burst;145 u32 clk_csite_src;146 u32 cclk_divider;147} tegra30_cpu_clk_sctx;148#endif149 150static void __iomem *clk_base;151static void __iomem *pmc_base;152static unsigned long input_freq;153 154static DEFINE_SPINLOCK(cml_lock);155static DEFINE_SPINLOCK(pll_d_lock);156 157#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \158 _clk_num, _gate_flags, _clk_id) \159 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \160 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \161 _clk_num, _gate_flags, _clk_id)162 163#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \164 _clk_num, _gate_flags, _clk_id) \165 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \166 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \167 _clk_num, _gate_flags, _clk_id)168 169#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \170 _clk_num, _gate_flags, _clk_id) \171 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \172 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \173 TEGRA_DIVIDER_ROUND_UP, _clk_num, \174 _gate_flags, _clk_id)175 176#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \177 _mux_shift, _mux_width, _clk_num, \178 _gate_flags, _clk_id) \179 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \180 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\181 _clk_num, _gate_flags, \182 _clk_id)183 184static struct clk **clks;185 186static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {187 { 12000000, 1040000000, 520, 6, 1, 8 },188 { 13000000, 1040000000, 480, 6, 1, 8 },189 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */190 { 19200000, 1040000000, 325, 6, 1, 6 },191 { 26000000, 1040000000, 520, 13, 1, 8 },192 { 12000000, 832000000, 416, 6, 1, 8 },193 { 13000000, 832000000, 832, 13, 1, 8 },194 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */195 { 19200000, 832000000, 260, 6, 1, 8 },196 { 26000000, 832000000, 416, 13, 1, 8 },197 { 12000000, 624000000, 624, 12, 1, 8 },198 { 13000000, 624000000, 624, 13, 1, 8 },199 { 16800000, 600000000, 520, 14, 1, 8 },200 { 19200000, 624000000, 520, 16, 1, 8 },201 { 26000000, 624000000, 624, 26, 1, 8 },202 { 12000000, 600000000, 600, 12, 1, 8 },203 { 13000000, 600000000, 600, 13, 1, 8 },204 { 16800000, 600000000, 500, 14, 1, 8 },205 { 19200000, 600000000, 375, 12, 1, 6 },206 { 26000000, 600000000, 600, 26, 1, 8 },207 { 12000000, 520000000, 520, 12, 1, 8 },208 { 13000000, 520000000, 520, 13, 1, 8 },209 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */210 { 19200000, 520000000, 325, 12, 1, 6 },211 { 26000000, 520000000, 520, 26, 1, 8 },212 { 12000000, 416000000, 416, 12, 1, 8 },213 { 13000000, 416000000, 416, 13, 1, 8 },214 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */215 { 19200000, 416000000, 260, 12, 1, 6 },216 { 26000000, 416000000, 416, 26, 1, 8 },217 { 0, 0, 0, 0, 0, 0 },218};219 220static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {221 { 12000000, 666000000, 666, 12, 1, 8 },222 { 13000000, 666000000, 666, 13, 1, 8 },223 { 16800000, 666000000, 555, 14, 1, 8 },224 { 19200000, 666000000, 555, 16, 1, 8 },225 { 26000000, 666000000, 666, 26, 1, 8 },226 { 12000000, 600000000, 600, 12, 1, 8 },227 { 13000000, 600000000, 600, 13, 1, 8 },228 { 16800000, 600000000, 500, 14, 1, 8 },229 { 19200000, 600000000, 375, 12, 1, 6 },230 { 26000000, 600000000, 600, 26, 1, 8 },231 { 0, 0, 0, 0, 0, 0 },232};233 234static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {235 { 12000000, 216000000, 432, 12, 2, 8 },236 { 13000000, 216000000, 432, 13, 2, 8 },237 { 16800000, 216000000, 360, 14, 2, 8 },238 { 19200000, 216000000, 360, 16, 2, 8 },239 { 26000000, 216000000, 432, 26, 2, 8 },240 { 0, 0, 0, 0, 0, 0 },241};242 243static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {244 { 9600000, 564480000, 294, 5, 1, 4 },245 { 9600000, 552960000, 288, 5, 1, 4 },246 { 9600000, 24000000, 5, 2, 1, 1 },247 { 28800000, 56448000, 49, 25, 1, 1 },248 { 28800000, 73728000, 64, 25, 1, 1 },249 { 28800000, 24000000, 5, 6, 1, 1 },250 { 0, 0, 0, 0, 0, 0 },251};252 253static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {254 { 12000000, 216000000, 216, 12, 1, 4 },255 { 13000000, 216000000, 216, 13, 1, 4 },256 { 16800000, 216000000, 180, 14, 1, 4 },257 { 19200000, 216000000, 180, 16, 1, 4 },258 { 26000000, 216000000, 216, 26, 1, 4 },259 { 12000000, 594000000, 594, 12, 1, 8 },260 { 13000000, 594000000, 594, 13, 1, 8 },261 { 16800000, 594000000, 495, 14, 1, 8 },262 { 19200000, 594000000, 495, 16, 1, 8 },263 { 26000000, 594000000, 594, 26, 1, 8 },264 { 12000000, 1000000000, 1000, 12, 1, 12 },265 { 13000000, 1000000000, 1000, 13, 1, 12 },266 { 19200000, 1000000000, 625, 12, 1, 8 },267 { 26000000, 1000000000, 1000, 26, 1, 12 },268 { 0, 0, 0, 0, 0, 0 },269};270 271static const struct pdiv_map pllu_p[] = {272 { .pdiv = 1, .hw_val = 1 },273 { .pdiv = 2, .hw_val = 0 },274 { .pdiv = 0, .hw_val = 0 },275};276 277static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {278 { 12000000, 480000000, 960, 12, 2, 12 },279 { 13000000, 480000000, 960, 13, 2, 12 },280 { 16800000, 480000000, 400, 7, 2, 5 },281 { 19200000, 480000000, 200, 4, 2, 3 },282 { 26000000, 480000000, 960, 26, 2, 12 },283 { 0, 0, 0, 0, 0, 0 },284};285 286static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {287 /* 1.7 GHz */288 { 12000000, 1700000000, 850, 6, 1, 8 },289 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */290 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */291 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */292 { 26000000, 1700000000, 850, 13, 1, 8 },293 /* 1.6 GHz */294 { 12000000, 1600000000, 800, 6, 1, 8 },295 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */296 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */297 { 19200000, 1600000000, 500, 6, 1, 8 },298 { 26000000, 1600000000, 800, 13, 1, 8 },299 /* 1.5 GHz */300 { 12000000, 1500000000, 750, 6, 1, 8 },301 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */302 { 16800000, 1500000000, 625, 7, 1, 8 },303 { 19200000, 1500000000, 625, 8, 1, 8 },304 { 26000000, 1500000000, 750, 13, 1, 8 },305 /* 1.4 GHz */306 { 12000000, 1400000000, 700, 6, 1, 8 },307 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */308 { 16800000, 1400000000, 1000, 12, 1, 8 },309 { 19200000, 1400000000, 875, 12, 1, 8 },310 { 26000000, 1400000000, 700, 13, 1, 8 },311 /* 1.3 GHz */312 { 12000000, 1300000000, 975, 9, 1, 8 },313 { 13000000, 1300000000, 1000, 10, 1, 8 },314 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */315 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */316 { 26000000, 1300000000, 650, 13, 1, 8 },317 /* 1.2 GHz */318 { 12000000, 1200000000, 1000, 10, 1, 8 },319 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */320 { 16800000, 1200000000, 1000, 14, 1, 8 },321 { 19200000, 1200000000, 1000, 16, 1, 8 },322 { 26000000, 1200000000, 600, 13, 1, 8 },323 /* 1.1 GHz */324 { 12000000, 1100000000, 825, 9, 1, 8 },325 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */326 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */327 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */328 { 26000000, 1100000000, 550, 13, 1, 8 },329 /* 1 GHz */330 { 12000000, 1000000000, 1000, 12, 1, 8 },331 { 13000000, 1000000000, 1000, 13, 1, 8 },332 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */333 { 19200000, 1000000000, 625, 12, 1, 8 },334 { 26000000, 1000000000, 1000, 26, 1, 8 },335 { 0, 0, 0, 0, 0, 0 },336};337 338static const struct pdiv_map plle_p[] = {339 { .pdiv = 18, .hw_val = 18 },340 { .pdiv = 24, .hw_val = 24 },341 { .pdiv = 0, .hw_val = 0 },342};343 344static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {345 /* PLLE special case: use cpcon field to store cml divider value */346 { 12000000, 100000000, 150, 1, 18, 11 },347 { 216000000, 100000000, 200, 18, 24, 13 },348 { 0, 0, 0, 0, 0, 0 },349};350 351/* PLL parameters */352static struct tegra_clk_pll_params pll_c_params __ro_after_init = {353 .input_min = 2000000,354 .input_max = 31000000,355 .cf_min = 1000000,356 .cf_max = 6000000,357 .vco_min = 20000000,358 .vco_max = 1400000000,359 .base_reg = PLLC_BASE,360 .misc_reg = PLLC_MISC,361 .lock_mask = PLL_BASE_LOCK,362 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,363 .lock_delay = 300,364 .freq_table = pll_c_freq_table,365 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |366 TEGRA_PLL_HAS_LOCK_ENABLE,367};368 369static struct div_nmp pllm_nmp = {370 .divn_shift = 8,371 .divn_width = 10,372 .override_divn_shift = 5,373 .divm_shift = 0,374 .divm_width = 5,375 .override_divm_shift = 0,376 .divp_shift = 20,377 .divp_width = 3,378 .override_divp_shift = 15,379};380 381static struct tegra_clk_pll_params pll_m_params __ro_after_init = {382 .input_min = 2000000,383 .input_max = 31000000,384 .cf_min = 1000000,385 .cf_max = 6000000,386 .vco_min = 20000000,387 .vco_max = 1200000000,388 .base_reg = PLLM_BASE,389 .misc_reg = PLLM_MISC,390 .lock_mask = PLL_BASE_LOCK,391 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,392 .lock_delay = 300,393 .div_nmp = &pllm_nmp,394 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,395 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,396 .freq_table = pll_m_freq_table,397 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |398 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |399 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,400};401 402static struct tegra_clk_pll_params pll_p_params __ro_after_init = {403 .input_min = 2000000,404 .input_max = 31000000,405 .cf_min = 1000000,406 .cf_max = 6000000,407 .vco_min = 20000000,408 .vco_max = 1400000000,409 .base_reg = PLLP_BASE,410 .misc_reg = PLLP_MISC,411 .lock_mask = PLL_BASE_LOCK,412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,413 .lock_delay = 300,414 .freq_table = pll_p_freq_table,415 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |416 TEGRA_PLL_HAS_LOCK_ENABLE,417 .fixed_rate = 408000000,418};419 420static struct tegra_clk_pll_params pll_a_params = {421 .input_min = 2000000,422 .input_max = 31000000,423 .cf_min = 1000000,424 .cf_max = 6000000,425 .vco_min = 20000000,426 .vco_max = 1400000000,427 .base_reg = PLLA_BASE,428 .misc_reg = PLLA_MISC,429 .lock_mask = PLL_BASE_LOCK,430 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,431 .lock_delay = 300,432 .freq_table = pll_a_freq_table,433 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |434 TEGRA_PLL_HAS_LOCK_ENABLE,435};436 437static struct tegra_clk_pll_params pll_d_params __ro_after_init = {438 .input_min = 2000000,439 .input_max = 40000000,440 .cf_min = 1000000,441 .cf_max = 6000000,442 .vco_min = 40000000,443 .vco_max = 1000000000,444 .base_reg = PLLD_BASE,445 .misc_reg = PLLD_MISC,446 .lock_mask = PLL_BASE_LOCK,447 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,448 .lock_delay = 1000,449 .freq_table = pll_d_freq_table,450 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |451 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,452};453 454static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {455 .input_min = 2000000,456 .input_max = 40000000,457 .cf_min = 1000000,458 .cf_max = 6000000,459 .vco_min = 40000000,460 .vco_max = 1000000000,461 .base_reg = PLLD2_BASE,462 .misc_reg = PLLD2_MISC,463 .lock_mask = PLL_BASE_LOCK,464 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,465 .lock_delay = 1000,466 .freq_table = pll_d_freq_table,467 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |468 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,469};470 471static struct tegra_clk_pll_params pll_u_params __ro_after_init = {472 .input_min = 2000000,473 .input_max = 40000000,474 .cf_min = 1000000,475 .cf_max = 6000000,476 .vco_min = 48000000,477 .vco_max = 960000000,478 .base_reg = PLLU_BASE,479 .misc_reg = PLLU_MISC,480 .lock_mask = PLL_BASE_LOCK,481 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,482 .lock_delay = 1000,483 .pdiv_tohw = pllu_p,484 .freq_table = pll_u_freq_table,485 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |486 TEGRA_PLL_HAS_LOCK_ENABLE,487};488 489static struct tegra_clk_pll_params pll_x_params __ro_after_init = {490 .input_min = 2000000,491 .input_max = 31000000,492 .cf_min = 1000000,493 .cf_max = 6000000,494 .vco_min = 20000000,495 .vco_max = 1700000000,496 .base_reg = PLLX_BASE,497 .misc_reg = PLLX_MISC,498 .lock_mask = PLL_BASE_LOCK,499 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,500 .lock_delay = 300,501 .freq_table = pll_x_freq_table,502 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |503 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,504 .pre_rate_change = tegra_cclk_pre_pllx_rate_change,505 .post_rate_change = tegra_cclk_post_pllx_rate_change,506};507 508static struct tegra_clk_pll_params pll_e_params __ro_after_init = {509 .input_min = 12000000,510 .input_max = 216000000,511 .cf_min = 12000000,512 .cf_max = 12000000,513 .vco_min = 1200000000,514 .vco_max = 2400000000U,515 .base_reg = PLLE_BASE,516 .misc_reg = PLLE_MISC,517 .lock_mask = PLLE_MISC_LOCK,518 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,519 .lock_delay = 300,520 .pdiv_tohw = plle_p,521 .freq_table = pll_e_freq_table,522 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |523 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,524 .fixed_rate = 100000000,525};526 527static unsigned long tegra30_input_freq[] = {528 [ 0] = 13000000,529 [ 1] = 16800000,530 [ 4] = 19200000,531 [ 5] = 38400000,532 [ 8] = 12000000,533 [ 9] = 48000000,534 [12] = 26000000,535};536 537static struct tegra_devclk devclks[] = {538 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },539 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },540 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },541 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },542 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },543 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },544 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },545 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },546 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },547 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },548 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },549 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },550 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },551 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },552 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },553 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },554 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },555 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },556 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },557 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },558 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },559 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },560 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },561 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },562 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },563 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },564 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },565 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },566 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },567 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },568 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },569 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },570 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },571 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },572 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },573 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },574 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },575 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },576 { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },577 { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },578 { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },579 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },580 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },581 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },582 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },583 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },584 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },585 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },586 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },587 { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },588 { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },589 { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },590 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },591 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },592 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },593 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },594 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },595 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },596 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },597 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },598 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },599 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },600 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },601 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },602 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },603 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },604 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },605 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },606 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },607 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },608 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },609 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },610 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },611 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },612 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },613 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },614 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },615 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },616 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },617 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },618 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },619 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },620 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },621 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },622 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },623 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },624 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },625 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },626 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },627 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },628 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },629 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },630 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },631 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },632 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },633 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },634 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },635 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },636 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },637 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },638 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },639 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },640 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },641 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },642 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },643 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },644 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },645 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },646 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },647 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },648 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },649 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },650 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },651 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },652 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },653 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },654 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },655 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },656 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },657 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },658 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },659 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },660 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },661 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },662 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },663 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },664 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },665 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },666 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },667 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },668 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },669 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },670 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },671 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },672 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },673 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },674 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },675 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },676 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },677 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },678 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },679 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },680 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },681 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },682 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },683 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },684 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },685};686 687static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {688 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },689 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },690 [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },691 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },692 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },693 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },694 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },695 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },696 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },697 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },698 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },699 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },700 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },701 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },702 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },703 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },704 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },705 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },706 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },707 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },708 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },709 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },710 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },711 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },712 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },713 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },714 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },715 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },716 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },717 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },718 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },719 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },720 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },721 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },722 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },723 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },724 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },725 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },726 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },727 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },728 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },729 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },730 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },731 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },732 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },733 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },734 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },735 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },736 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },737 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },738 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },739 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },740 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },741 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },742 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },743 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },744 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },745 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },746 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },747 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },748 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },749 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },750 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },751 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },752 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },753 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },754 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },755 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },756 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },757 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },758 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },759 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },760 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },761 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },762 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },763 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },764 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },765 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },766 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },767 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },768 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },769 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },770 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },771 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },772 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },773 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },774 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },775 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },776 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },777 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },778 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },779 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },780 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },781 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },782 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },783 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },784 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },785 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },786 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },787 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },788 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },789 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },790 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },791 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },792 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },793 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },794 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },795 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },796 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },797 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },798 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },799 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },800 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },801 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },802 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },803 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },804 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },805 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },806 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },807 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },808 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },809};810 811static const char *pll_e_parents[] = { "pll_ref", "pll_p" };812 813static void __init tegra30_pll_init(void)814{815 struct clk *clk;816 817 /* PLLC_OUT1 */818 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",819 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,820 8, 8, 1, NULL);821 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",822 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,823 0, NULL);824 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;825 826 /* PLLM_OUT1 */827 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",828 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,829 8, 8, 1, NULL);830 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",831 clk_base + PLLM_OUT, 1, 0,832 CLK_SET_RATE_PARENT, 0, NULL);833 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;834 835 /* PLLX */836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,837 &pll_x_params, NULL);838 clks[TEGRA30_CLK_PLL_X] = clk;839 840 /* PLLX_OUT0 */841 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",842 CLK_SET_RATE_PARENT, 1, 2);843 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;844 845 /* PLLU */846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,847 &pll_u_params, NULL);848 clks[TEGRA30_CLK_PLL_U] = clk;849 850 /* PLLD */851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,852 &pll_d_params, &pll_d_lock);853 clks[TEGRA30_CLK_PLL_D] = clk;854 855 /* PLLD_OUT0 */856 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",857 CLK_SET_RATE_PARENT, 1, 2);858 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;859 860 /* PLLD2 */861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,862 &pll_d2_params, NULL);863 clks[TEGRA30_CLK_PLL_D2] = clk;864 865 /* PLLD2_OUT0 */866 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",867 CLK_SET_RATE_PARENT, 1, 2);868 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;869 870 /* PLLE */871 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,872 ARRAY_SIZE(pll_e_parents),873 CLK_SET_RATE_NO_REPARENT,874 clk_base + PLLE_AUX, 2, 1, 0, NULL);875}876 877static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",878 "pll_p_cclkg", "pll_p_out4_cclkg",879 "pll_p_out3_cclkg", "unused", "pll_x" };880static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",881 "pll_p_cclklp", "pll_p_out4_cclklp",882 "pll_p_out3_cclklp", "unused", "pll_x",883 "pll_x_out0" };884static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",885 "pll_p_out3", "pll_p_out2", "unused",886 "clk_32k", "pll_m_out1" };887 888static void __init tegra30_super_clk_init(void)889{890 struct clk *clk;891 892 /*893 * Clock input to cclk_g divided from pll_p using894 * U71 divider of cclk_g.895 */896 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",897 clk_base + SUPER_CCLKG_DIVIDER, 0,898 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);899 clk_register_clkdev(clk, "pll_p_cclkg", NULL);900 901 /*902 * Clock input to cclk_g divided from pll_p_out3 using903 * U71 divider of cclk_g.904 */905 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",906 clk_base + SUPER_CCLKG_DIVIDER, 0,907 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);908 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);909 910 /*911 * Clock input to cclk_g divided from pll_p_out4 using912 * U71 divider of cclk_g.913 */914 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",915 clk_base + SUPER_CCLKG_DIVIDER, 0,916 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);917 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);918 919 /* CCLKG */920 clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,921 ARRAY_SIZE(cclk_g_parents),922 CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,923 clk_base + CCLKG_BURST_POLICY,924 0, NULL);925 clks[TEGRA30_CLK_CCLK_G] = clk;926 927 /*928 * Clock input to cclk_lp divided from pll_p using929 * U71 divider of cclk_lp.930 */931 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",932 clk_base + SUPER_CCLKLP_DIVIDER, 0,933 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);934 clk_register_clkdev(clk, "pll_p_cclklp", NULL);935 936 /*937 * Clock input to cclk_lp divided from pll_p_out3 using938 * U71 divider of cclk_lp.939 */940 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",941 clk_base + SUPER_CCLKLP_DIVIDER, 0,942 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);943 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);944 945 /*946 * Clock input to cclk_lp divided from pll_p_out4 using947 * U71 divider of cclk_lp.948 */949 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",950 clk_base + SUPER_CCLKLP_DIVIDER, 0,951 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);952 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);953 954 /* CCLKLP */955 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,956 ARRAY_SIZE(cclk_lp_parents),957 CLK_SET_RATE_PARENT,958 clk_base + CCLKLP_BURST_POLICY,959 TEGRA_DIVIDER_2, 4, 8, 9,960 NULL);961 clks[TEGRA30_CLK_CCLK_LP] = clk;962 963 /* twd */964 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",965 CLK_SET_RATE_PARENT, 1, 2);966 clks[TEGRA30_CLK_TWD] = clk;967 968 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);969}970 971static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",972 "clk_m" };973static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };974static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",975 "clk_m" };976static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };977static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",978 "pll_a_out0", "pll_c",979 "pll_d2_out0", "clk_m" };980static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",981 "pll_d2_out0" };982static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };983 984static struct tegra_periph_init_data tegra_periph_clk_list[] = {985 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),986 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),987 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),988 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),989 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),990 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2),991 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),992 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),993 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),994};995 996static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {997 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),998};999 1000static void __init tegra30_periph_clk_init(void)1001{1002 struct tegra_periph_init_data *data;1003 struct clk *clk;1004 unsigned int i;1005 1006 /* dsia */1007 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,1008 0, 48, periph_clk_enb_refcnt);1009 clks[TEGRA30_CLK_DSIA] = clk;1010 1011 /* pcie */1012 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,1013 70, periph_clk_enb_refcnt);1014 clks[TEGRA30_CLK_PCIE] = clk;1015 1016 /* afi */1017 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,1018 periph_clk_enb_refcnt);1019 clks[TEGRA30_CLK_AFI] = clk;1020 1021 /* emc */1022 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);1023 1024 clks[TEGRA30_CLK_EMC] = clk;1025 1026 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,1027 NULL);1028 clks[TEGRA30_CLK_MC] = clk;1029 1030 /* cml0 */1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,1032 0, 0, &cml_lock);1033 clks[TEGRA30_CLK_CML0] = clk;1034 1035 /* cml1 */1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,1037 1, 0, &cml_lock);1038 clks[TEGRA30_CLK_CML1] = clk;1039 1040 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {1041 data = &tegra_periph_clk_list[i];1042 clk = tegra_clk_register_periph_data(clk_base, data);1043 clks[data->clk_id] = clk;1044 }1045 1046 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {1047 data = &tegra_periph_nodiv_clk_list[i];1048 clk = tegra_clk_register_periph_nodiv(data->name,1049 data->p.parent_names,1050 data->num_parents, &data->periph,1051 clk_base, data->offset);1052 clks[data->clk_id] = clk;1053 }1054 1055 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);1056}1057 1058/* Tegra30 CPU clock and reset control functions */1059static void tegra30_wait_cpu_in_reset(u32 cpu)1060{1061 unsigned int reg;1062 1063 do {1064 reg = readl(clk_base +1065 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);1066 cpu_relax();1067 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */1068 1069 return;1070}1071 1072static void tegra30_put_cpu_in_reset(u32 cpu)1073{1074 writel(CPU_RESET(cpu),1075 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);1076 dmb();1077}1078 1079static void tegra30_cpu_out_of_reset(u32 cpu)1080{1081 writel(CPU_RESET(cpu),1082 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);1083 wmb();1084}1085 1086static void tegra30_enable_cpu_clock(u32 cpu)1087{1088 writel(CPU_CLOCK(cpu),1089 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);1090 readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);1091}1092 1093static void tegra30_disable_cpu_clock(u32 cpu)1094{1095 unsigned int reg;1096 1097 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);1098 writel(reg | CPU_CLOCK(cpu),1099 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);1100}1101 1102#ifdef CONFIG_PM_SLEEP1103static bool tegra30_cpu_rail_off_ready(void)1104{1105 unsigned int cpu_rst_status;1106 int cpu_pwr_status;1107 1108 cpu_rst_status = readl(clk_base +1109 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);1110 cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||1111 tegra_pmc_cpu_is_powered(2) ||1112 tegra_pmc_cpu_is_powered(3);1113 1114 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)1115 return false;1116 1117 return true;1118}1119 1120static void tegra30_cpu_clock_suspend(void)1121{1122 /* switch coresite to clk_m, save off original source */1123 tegra30_cpu_clk_sctx.clk_csite_src =1124 readl(clk_base + CLK_RESET_SOURCE_CSITE);1125 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);1126 1127 tegra30_cpu_clk_sctx.cpu_burst =1128 readl(clk_base + CLK_RESET_CCLK_BURST);1129 tegra30_cpu_clk_sctx.pllx_base =1130 readl(clk_base + CLK_RESET_PLLX_BASE);1131 tegra30_cpu_clk_sctx.pllx_misc =1132 readl(clk_base + CLK_RESET_PLLX_MISC);1133 tegra30_cpu_clk_sctx.cclk_divider =1134 readl(clk_base + CLK_RESET_CCLK_DIVIDER);1135}1136 1137static void tegra30_cpu_clock_resume(void)1138{1139 unsigned int reg, policy;1140 u32 misc, base;1141 1142 /* Is CPU complex already running on PLLX? */1143 reg = readl(clk_base + CLK_RESET_CCLK_BURST);1144 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;1145 1146 if (policy == CLK_RESET_CCLK_IDLE_POLICY)1147 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;1148 else if (policy == CLK_RESET_CCLK_RUN_POLICY)1149 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;1150 else1151 BUG();1152 1153 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {1154 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);1155 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);1156 1157 if (misc != tegra30_cpu_clk_sctx.pllx_misc ||1158 base != tegra30_cpu_clk_sctx.pllx_base) {1159 /* restore PLLX settings if CPU is on different PLL */1160 writel(tegra30_cpu_clk_sctx.pllx_misc,1161 clk_base + CLK_RESET_PLLX_MISC);1162 writel(tegra30_cpu_clk_sctx.pllx_base,1163 clk_base + CLK_RESET_PLLX_BASE);1164 1165 /* wait for PLL stabilization if PLLX was enabled */1166 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))1167 udelay(300);1168 }1169 }1170 1171 /*1172 * Restore original burst policy setting for calls resulting from CPU1173 * LP2 in idle or system suspend.1174 */1175 writel(tegra30_cpu_clk_sctx.cclk_divider,1176 clk_base + CLK_RESET_CCLK_DIVIDER);1177 writel(tegra30_cpu_clk_sctx.cpu_burst,1178 clk_base + CLK_RESET_CCLK_BURST);1179 1180 writel(tegra30_cpu_clk_sctx.clk_csite_src,1181 clk_base + CLK_RESET_SOURCE_CSITE);1182}1183#endif1184 1185static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {1186 .wait_for_reset = tegra30_wait_cpu_in_reset,1187 .put_in_reset = tegra30_put_cpu_in_reset,1188 .out_of_reset = tegra30_cpu_out_of_reset,1189 .enable_clock = tegra30_enable_cpu_clock,1190 .disable_clock = tegra30_disable_cpu_clock,1191#ifdef CONFIG_PM_SLEEP1192 .rail_off_ready = tegra30_cpu_rail_off_ready,1193 .suspend = tegra30_cpu_clock_suspend,1194 .resume = tegra30_cpu_clock_resume,1195#endif1196};1197 1198static struct tegra_clk_init_table init_table[] = {1199 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },1200 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },1201 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },1202 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },1203 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },1204 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },1205 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },1206 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },1207 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },1208 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },1209 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },1210 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },1211 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },1212 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },1213 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },1214 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },1215 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },1216 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },1217 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },1218 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },1219 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },1220 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },1221 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },1222 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },1223 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },1224 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },1225 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },1226 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },1227 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },1228 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },1229 { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },1230 { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1231 { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1232 { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1233 { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1234 { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1235 { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1236 { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },1237 { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },1238 { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },1239 { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },1240 /* must be the last entry */1241 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },1242};1243 1244/*1245 * Some clocks may be used by different drivers depending on the board1246 * configuration. List those here to register them twice in the clock lookup1247 * table under two names.1248 */1249static struct tegra_clk_duplicate tegra_clk_duplicates[] = {1250 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),1251 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),1252 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),1253 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),1254 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),1255 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),1256 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),1257 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),1258 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),1259 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),1260 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),1261 /* must be the last entry */1262 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),1263};1264 1265static const struct of_device_id pmc_match[] __initconst = {1266 { .compatible = "nvidia,tegra30-pmc" },1267 { },1268};1269 1270static struct tegra_audio_clk_info tegra30_audio_plls[] = {1271 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },1272};1273 1274static bool tegra30_car_initialized;1275 1276static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,1277 void *data)1278{1279 struct clk_hw *hw;1280 struct clk *clk;1281 1282 /*1283 * Timer clocks are needed early, the rest of the clocks shouldn't be1284 * available to device drivers until clock tree is fully initialized.1285 */1286 if (clkspec->args[0] != TEGRA30_CLK_RTC &&1287 clkspec->args[0] != TEGRA30_CLK_TWD &&1288 clkspec->args[0] != TEGRA30_CLK_TIMER &&1289 !tegra30_car_initialized)1290 return ERR_PTR(-EPROBE_DEFER);1291 1292 clk = of_clk_src_onecell_get(clkspec, data);1293 if (IS_ERR(clk))1294 return clk;1295 1296 hw = __clk_get_hw(clk);1297 1298 if (clkspec->args[0] == TEGRA30_CLK_EMC) {1299 if (!tegra20_clk_emc_driver_available(hw))1300 return ERR_PTR(-EPROBE_DEFER);1301 }1302 1303 return clk;1304}1305 1306static void __init tegra30_clock_init(struct device_node *np)1307{1308 struct device_node *node;1309 1310 clk_base = of_iomap(np, 0);1311 if (!clk_base) {1312 pr_err("ioremap tegra30 CAR failed\n");1313 return;1314 }1315 1316 node = of_find_matching_node(NULL, pmc_match);1317 if (!node) {1318 pr_err("Failed to find pmc node\n");1319 BUG();1320 }1321 1322 pmc_base = of_iomap(node, 0);1323 of_node_put(node);1324 if (!pmc_base) {1325 pr_err("Can't map pmc registers\n");1326 BUG();1327 }1328 1329 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,1330 TEGRA30_CLK_PERIPH_BANKS);1331 if (!clks)1332 return;1333 1334 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,1335 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,1336 NULL) < 0)1337 return;1338 1339 tegra_fixed_clk_init(tegra30_clks);1340 tegra30_pll_init();1341 tegra30_super_clk_init();1342 tegra30_periph_clk_init();1343 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,1344 tegra30_audio_plls,1345 ARRAY_SIZE(tegra30_audio_plls), 24000000);1346 1347 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);1348 1349 tegra_add_of_provider(np, tegra30_clk_src_onecell_get);1350 1351 tegra_cpu_car_ops = &tegra30_cpu_car_ops;1352}1353CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);1354 1355/*1356 * Clocks that use runtime PM can't be created at the tegra30_clock_init1357 * time because drivers' base isn't initialized yet, and thus platform1358 * devices can't be created for the clocks. Hence we need to split the1359 * registration of the clocks into two phases. The first phase registers1360 * essential clocks which don't require RPM and are actually used during1361 * early boot. The second phase registers clocks which use RPM and this1362 * is done when device drivers' core API is ready.1363 */1364static int tegra30_car_probe(struct platform_device *pdev)1365{1366 struct clk *clk;1367 1368 /* PLLC */1369 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,1370 &pll_c_params, NULL);1371 clks[TEGRA30_CLK_PLL_C] = clk;1372 1373 /* PLLE */1374 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,1375 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);1376 clks[TEGRA30_CLK_PLL_E] = clk;1377 1378 /* PLLM */1379 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,1380 CLK_SET_RATE_GATE, &pll_m_params, NULL);1381 clks[TEGRA30_CLK_PLL_M] = clk;1382 1383 /* SCLK */1384 clk = tegra_clk_register_super_mux("sclk", sclk_parents,1385 ARRAY_SIZE(sclk_parents),1386 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,1387 clk_base + SCLK_BURST_POLICY,1388 0, 4, 0, 0, NULL);1389 clks[TEGRA30_CLK_SCLK] = clk;1390 1391 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));1392 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);1393 tegra30_car_initialized = true;1394 1395 return 0;1396}1397 1398static const struct of_device_id tegra30_car_match[] = {1399 { .compatible = "nvidia,tegra30-car" },1400 { }1401};1402 1403static struct platform_driver tegra30_car_driver = {1404 .driver = {1405 .name = "tegra30-car",1406 .of_match_table = tegra30_car_match,1407 .suppress_bind_attrs = true,1408 },1409 .probe = tegra30_car_probe,1410};1411 1412/*1413 * Clock driver must be registered before memory controller driver,1414 * which doesn't support deferred probing for today and is registered1415 * from arch init-level.1416 */1417static int tegra30_car_init(void)1418{1419 return platform_driver_register(&tegra30_car_driver);1420}1421postcore_initcall(tegra30_car_init);1422