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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * DRA7 Clock init4 *5 * Copyright (C) 2013 Texas Instruments, Inc.6 *7 * Tero Kristo (t-kristo@ti.com)8 */9 10#include <linux/kernel.h>11#include <linux/list.h>12#include <linux/clk.h>13#include <linux/clkdev.h>14#include <linux/clk/ti.h>15#include <dt-bindings/clock/dra7.h>16 17#include "clock.h"18 19#define DRA7_DPLL_GMAC_DEFFREQ 100000000020#define DRA7_DPLL_USB_DEFFREQ 96000000021 22static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {23 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },24 { 0 },25};26 27static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {28 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },29 { 0 },30};31 32static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {33 "dpll_abe_m2x2_ck",34 "dpll_core_h22x2_ck",35 NULL,36};37 38static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },40 { 0 },41};42 43static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {44 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },45 { 0 },46};47 48static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {49 "per_abe_x1_gfclk2_div",50 "video1_clk2_div",51 "video2_clk2_div",52 "hdmi_clk2_div",53 NULL,54};55 56static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {57 "abe_24m_fclk",58 "abe_sys_clk_div",59 "func_24m_clk",60 "atl_clkin3_ck",61 "atl_clkin2_ck",62 "atl_clkin1_ck",63 "atl_clkin0_ck",64 "sys_clkin2",65 "ref_clkin0_ck",66 "ref_clkin1_ck",67 "ref_clkin2_ck",68 "ref_clkin3_ck",69 "mlb_clk",70 "mlbp_clk",71 NULL,72};73 74static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },78 { 0 },79};80 81static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {82 "timer_sys_clk_div",83 "sys_32k_ck",84 "sys_clkin2",85 "ref_clkin0_ck",86 "ref_clkin1_ck",87 "ref_clkin2_ck",88 "ref_clkin3_ck",89 "abe_giclk_div",90 "video1_div_clk",91 "video2_div_clk",92 "hdmi_div_clk",93 "clkoutmux0_clk_mux",94 NULL,95};96 97static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },99 { 0 },100};101 102static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },104 { 0 },105};106 107static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },109 { 0 },110};111 112static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },114 { 0 },115};116 117static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {118 "func_48m_fclk",119 "dpll_per_m2x2_ck",120 NULL,121};122 123static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },125 { 0 },126};127 128static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },134 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },136 { 0 },137};138 139static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {140 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },141 { 0 },142};143 144static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {145 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },146 { 0 },147};148 149static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {150 "l3_iclk_div",151 "core_iss_main_clk",152 NULL,153};154 155static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },157 { 0 },158};159 160static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {161 { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },162 { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },163 { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },164 { 0 },165};166 167static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {168 { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },169 { 0 },170};171 172static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {173 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },174 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },175 { 0 },176};177 178static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {179 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },180 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },181 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },182 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },183 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },184 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },185 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },186 { 0 },187};188 189static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {190 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },191 { 0 },192};193 194static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {195 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },196 { 0 },197};198 199static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {200 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },201 { 0 },202};203 204static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {205 "sys_32k_ck",206 "video1_clkin_ck",207 "video2_clkin_ck",208 "hdmi_clkin_ck",209 NULL,210};211 212static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {213 "l3_iclk_div",214 "dpll_abe_m2_ck",215 "atl-clkctrl:0000:24",216 NULL,217};218 219static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },222 { 0 },223};224 225static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {226 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },227 { 0 },228};229 230static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {231 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },232 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },233 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },234 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },235 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },236 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },237 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },238 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },239 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },240 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },241 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },242 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },243 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },244 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },245 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },246 { 0 },247};248 249static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {250 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },251 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },252 { 0 },253};254 255static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {256 { DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },257 { DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },258 { 0 },259};260 261static const char * const dra7_dss_dss_clk_parents[] __initconst = {262 "dpll_per_h12x2_ck",263 NULL,264};265 266static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {267 "func_48m_fclk",268 NULL,269};270 271static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {272 "hdmi_dpll_clk_mux",273 NULL,274};275 276static const char * const dra7_dss_32khz_clk_parents[] __initconst = {277 "sys_32k_ck",278 NULL,279};280 281static const char * const dra7_dss_video1_clk_parents[] __initconst = {282 "video1_dpll_clk_mux",283 NULL,284};285 286static const char * const dra7_dss_video2_clk_parents[] __initconst = {287 "video2_dpll_clk_mux",288 NULL,289};290 291static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {292 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },293 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },294 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },295 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },296 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },297 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },298 { 0 },299};300 301static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {302 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },303 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },304 { 0 },305};306 307static const char * const dra7_gpu_core_mux_parents[] __initconst = {308 "dpll_core_h14x2_ck",309 "dpll_per_h14x2_ck",310 "dpll_gpu_m2_ck",311 NULL,312};313 314static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {315 "dpll_core_h14x2_ck",316 "dpll_per_h14x2_ck",317 "dpll_gpu_m2_ck",318 NULL,319};320 321static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {322 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },323 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },324 { 0 },325};326 327static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {328 { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },329 { 0 },330};331 332static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {333 "func_128m_clk",334 "dpll_per_m2x2_ck",335 NULL,336};337 338static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {339 "l3init-clkctrl:0008:24",340 NULL,341};342 343static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {344 .max_div = 4,345 .flags = CLK_DIVIDER_POWER_OF_TWO,346};347 348static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {349 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },350 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },351 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },352 { 0 },353};354 355static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {356 "l3init-clkctrl:0010:24",357 NULL,358};359 360static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {361 .max_div = 4,362 .flags = CLK_DIVIDER_POWER_OF_TWO,363};364 365static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {366 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },367 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },368 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },369 { 0 },370};371 372static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {373 "l3init_960m_gfclk",374 NULL,375};376 377static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {378 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },379 { 0 },380};381 382static const char * const dra7_sata_ref_clk_parents[] __initconst = {383 "sys_clkin1",384 NULL,385};386 387static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {388 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },389 { 0 },390};391 392static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {393 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },394 { 0 },395};396 397static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {398 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },399 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },400 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },401 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },402 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },403 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },404 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },405 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },406 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },407 { 0 },408};409 410static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {411 "apll_pcie_ck",412 NULL,413};414 415static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {416 "optfclk_pciephy_div",417 NULL,418};419 420static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {421 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },422 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },423 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },424 { 0 },425};426 427static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {428 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },429 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },430 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },431 { 0 },432};433 434static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {435 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },436 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },437 { 0 },438};439 440static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {441 "dpll_gmac_h11x2_ck",442 "rmii_clk_ck",443 NULL,444};445 446static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {447 "video1_clkin_ck",448 "video2_clkin_ck",449 "dpll_abe_m2_ck",450 "hdmi_clkin_ck",451 "l3_iclk_div",452 NULL,453};454 455static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {456 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },457 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },458 { 0 },459};460 461static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {462 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },463 { 0 },464};465 466static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {467 "timer_sys_clk_div",468 "sys_32k_ck",469 "sys_clkin2",470 "ref_clkin0_ck",471 "ref_clkin1_ck",472 "ref_clkin2_ck",473 "ref_clkin3_ck",474 "abe_giclk_div",475 "video1_div_clk",476 "video2_div_clk",477 "hdmi_div_clk",478 NULL,479};480 481static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {482 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },483 { 0 },484};485 486static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {487 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },488 { 0 },489};490 491static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {492 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },493 { 0 },494};495 496static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {497 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },498 { 0 },499};500 501static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {502 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },503 { 0 },504};505 506static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {507 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },508 { 0 },509};510 511static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {512 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },513 { 0 },514};515 516static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {517 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },518 { 0 },519};520 521static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {522 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },523 { 0 },524};525 526static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {527 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },528 { 0 },529};530 531static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {532 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },533 { 0 },534};535 536static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {537 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },538 { 0 },539};540 541static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {542 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },543 { 0 },544};545 546static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {547 "l4per-clkctrl:00f8:24",548 NULL,549};550 551static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {552 .max_div = 4,553 .flags = CLK_DIVIDER_POWER_OF_TWO,554};555 556static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {557 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },558 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },559 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },560 { 0 },561};562 563static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {564 "l4per-clkctrl:0100:24",565 NULL,566};567 568static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {569 .max_div = 4,570 .flags = CLK_DIVIDER_POWER_OF_TWO,571};572 573static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {574 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },576 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },577 { 0 },578};579 580static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {581 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },582 { 0 },583};584 585static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },587 { 0 },588};589 590static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },592 { 0 },593};594 595static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },597 { 0 },598};599 600static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {601 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },602 { 0 },603};604 605static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {606 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },607 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },608 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },609 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },610 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },611 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },612 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },613 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },614 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },615 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },616 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },617 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },618 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },619 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },620 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },621 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },622 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },623 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },624 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },625 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },626 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },627 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },628 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },629 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },630 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },631 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },632 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },633 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },634 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },635 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },636 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },637 { 0 },638};639 640static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {641 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },642 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },643 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },644 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },645 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },646 { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },647 { 0 },648};649 650static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {651 "func_128m_clk",652 "dpll_per_h13x2_ck",653 NULL,654};655 656static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {657 "l4per2-clkctrl:012c:24",658 NULL,659};660 661static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {662 .max_div = 4,663 .flags = CLK_DIVIDER_POWER_OF_TWO,664};665 666static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {667 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },668 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },669 { 0 },670};671 672static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {673 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },674 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },675 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },676 { 0 },677};678 679static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },682 { 0 },683};684 685static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },688 { 0 },689};690 691static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },694 { 0 },695};696 697static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {698 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },699 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },700 { 0 },701};702 703static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {704 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },705 { 0 },706};707 708static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {709 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },710 { 0 },711};712 713static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {714 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },715 { 0 },716};717 718static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },721 { 0 },722};723 724static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {725 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },726 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },727 { 0 },728};729 730static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {731 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },732 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },733 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },734 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },735 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },736 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },737 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },738 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },739 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },740 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },741 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },742 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },743 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },744 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },745 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },746 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },747 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },748 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },749 { 0 },750};751 752static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {753 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },754 { 0 },755};756 757static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {758 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },759 { 0 },760};761 762static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {763 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },764 { 0 },765};766 767static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {768 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },769 { 0 },770};771 772static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {773 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },774 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },775 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },776 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },777 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },778 { 0 },779};780 781static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {782 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },783 { 0 },784};785 786static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {787 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },788 { 0 },789};790 791static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {792 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },793 { 0 },794};795 796static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {797 "sys_clkin1",798 "sys_clkin2",799 NULL,800};801 802static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {803 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },804 { 0 },805};806 807static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {808 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },809 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },810 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },811 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },812 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },813 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },814 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },815 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },816 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },817 { 0 },818};819 820const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {821 { 0x4a005320, dra7_mpu_clkctrl_regs },822 { 0x4a005420, dra7_dsp1_clkctrl_regs },823 { 0x4a005520, dra7_ipu1_clkctrl_regs },824 { 0x4a005550, dra7_ipu_clkctrl_regs },825 { 0x4a005620, dra7_dsp2_clkctrl_regs },826 { 0x4a005720, dra7_rtc_clkctrl_regs },827 { 0x4a005760, dra7_vpe_clkctrl_regs },828 { 0x4a008620, dra7_coreaon_clkctrl_regs },829 { 0x4a008720, dra7_l3main1_clkctrl_regs },830 { 0x4a008920, dra7_ipu2_clkctrl_regs },831 { 0x4a008a20, dra7_dma_clkctrl_regs },832 { 0x4a008b20, dra7_emif_clkctrl_regs },833 { 0x4a008c00, dra7_atl_clkctrl_regs },834 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },835 { 0x4a008e20, dra7_l3instr_clkctrl_regs },836 { 0x4a008f20, dra7_iva_clkctrl_regs },837 { 0x4a009020, dra7_cam_clkctrl_regs },838 { 0x4a009120, dra7_dss_clkctrl_regs },839 { 0x4a009220, dra7_gpu_clkctrl_regs },840 { 0x4a009320, dra7_l3init_clkctrl_regs },841 { 0x4a0093b0, dra7_pcie_clkctrl_regs },842 { 0x4a0093d0, dra7_gmac_clkctrl_regs },843 { 0x4a009728, dra7_l4per_clkctrl_regs },844 { 0x4a0098a0, dra7_l4sec_clkctrl_regs },845 { 0x4a00970c, dra7_l4per2_clkctrl_regs },846 { 0x4a009714, dra7_l4per3_clkctrl_regs },847 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },848 { 0 },849};850 851static struct ti_dt_clk dra7xx_clks[] = {852 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),853 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),854 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),855 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),856 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),857 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),858 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),859 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),860 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),861 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),862 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),863 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),864 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),865 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),866 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),867 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),868 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),869 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),870 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),871 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),872 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),873 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),874 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),875 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),876 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),877 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),878 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),879 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),880 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),881 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),882 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),883 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),884 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),885 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),886 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),887 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),888 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),889 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),890 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),891 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),892 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),893 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),894 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),895 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),896 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),897 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),898 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),899 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),900 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),901 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),902 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),903 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),904 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),905 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),906 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),907 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),908 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),909 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),910 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),911 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),912 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),913 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),914 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),915 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),916 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),917 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),918 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),919 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),920 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),921 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),922 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),923 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),924 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),925 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),926 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),927 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),928 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),929 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),930 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),931 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),932 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),933 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),934 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),935 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),936 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),937 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),938 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),939 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),940 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),941 { .node_name = NULL },942};943 944int __init dra7xx_dt_clk_init(void)945{946 int rc;947 struct clk *dpll_ck, *hdcp_ck;948 949 ti_dt_clocks_register(dra7xx_clks);950 951 omap2_clk_disable_autoidle_all();952 953 ti_clk_add_aliases();954 955 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");956 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);957 if (rc)958 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);959 960 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");961 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);962 if (rc)963 pr_err("%s: failed to configure USB DPLL!\n", __func__);964 965 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");966 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);967 if (rc)968 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);969 970 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");971 rc = clk_prepare_enable(hdcp_ck);972 if (rc)973 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);974 975 return rc;976}977