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1// SPDX-License-Identifier: GPL-2.0-only2 3#include <linux/kernel.h>4#include <linux/list.h>5#include <linux/clk-provider.h>6#include <linux/clk/ti.h>7#include <dt-bindings/clock/dm816.h>8 9#include "clock.h"10 11static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {12 { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },13 { 0 },14};15 16static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {17 { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },18 { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },19 { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },20 { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },21 { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },22 { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },23 { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },24 { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },25 { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },26 { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },27 { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },28 { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },29 { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },30 { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },31 { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },32 { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },33 { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },34 { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },35 { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },36 { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },37 { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },38 { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },39 { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },40 { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },41 { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },42 { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },43 { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },44 { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },45 { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },46 { 0 },47};48 49const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {50 { 0x48180500, dm816_default_clkctrl_regs },51 { 0x48181400, dm816_alwon_clkctrl_regs },52 { 0 },53};54 55static struct ti_dt_clk dm816x_clks[] = {56 DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),57 DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),58 DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),59 DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),60 { .node_name = NULL },61};62 63static const char *enable_init_clks[] = {64 "ddr_pll_clk1",65 "ddr_pll_clk2",66 "ddr_pll_clk3",67 "sysclk6_ck",68};69 70int __init dm816x_dt_clk_init(void)71{72 ti_dt_clocks_register(dm816x_clks);73 omap2_clk_disable_autoidle_all();74 ti_clk_add_aliases();75 omap2_clk_enable_init_clocks(enable_init_clks,76 ARRAY_SIZE(enable_init_clks));77 78 return 0;79}80