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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * OMAP2/3/4 DPLL clock functions4 *5 * Copyright (C) 2005-2008 Texas Instruments, Inc.6 * Copyright (C) 2004-2010 Nokia Corporation7 *8 * Contacts:9 * Richard Woodruff <r-woodruff2@ti.com>10 * Paul Walmsley11 */12#undef DEBUG13 14#include <linux/kernel.h>15#include <linux/errno.h>16#include <linux/clk.h>17#include <linux/clk-provider.h>18#include <linux/io.h>19#include <linux/clk/ti.h>20 21#include <asm/div64.h>22 23#include "clock.h"24 25/* DPLL rate rounding: minimum DPLL multiplier, divider values */26#define DPLL_MIN_MULTIPLIER 227#define DPLL_MIN_DIVIDER 128 29/* Possible error results from _dpll_test_mult */30#define DPLL_MULT_UNDERFLOW -131 32/*33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.34 * The higher the scale factor, the greater the risk of arithmetic overflow,35 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR36 * must be a power of DPLL_SCALE_BASE.37 */38#define DPLL_SCALE_FACTOR 6439#define DPLL_SCALE_BASE 240#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \41 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))42 43/*44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.45 * From device data manual section 4.3 "DPLL and DLL Specifications".46 */47#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 50000048#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 250000049 50/* _dpll_test_fint() return codes */51#define DPLL_FINT_UNDERFLOW -152#define DPLL_FINT_INVALID -253 54/* Private functions */55 56/*57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL58 * @clk: DPLL struct clk to test59 * @n: divider value (N) to test60 *61 * Tests whether a particular divider @n will result in a valid DPLL62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter63 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate64 * (assuming that it is counting N upwards), or -2 if the enclosing loop65 * should skip to the next iteration (again assuming N is increasing).66 */67static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n)68{69 struct dpll_data *dd;70 long fint, fint_min, fint_max;71 int ret = 0;72 73 dd = clk->dpll_data;74 75 /* DPLL divider must result in a valid jitter correction val */76 fint = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)) / n;77 78 if (dd->flags & DPLL_J_TYPE) {79 fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;80 fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;81 } else {82 fint_min = ti_clk_get_features()->fint_min;83 fint_max = ti_clk_get_features()->fint_max;84 }85 86 if (!fint_min || !fint_max) {87 WARN(1, "No fint limits available!\n");88 return DPLL_FINT_INVALID;89 }90 91 if (fint < ti_clk_get_features()->fint_min) {92 pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",93 n);94 dd->max_divider = n;95 ret = DPLL_FINT_UNDERFLOW;96 } else if (fint > ti_clk_get_features()->fint_max) {97 pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",98 n);99 dd->min_divider = n;100 ret = DPLL_FINT_INVALID;101 } else if (fint > ti_clk_get_features()->fint_band1_max &&102 fint < ti_clk_get_features()->fint_band2_min) {103 pr_debug("rejecting n=%d due to Fint failure\n", n);104 ret = DPLL_FINT_INVALID;105 }106 107 return ret;108}109 110static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,111 unsigned int m, unsigned int n)112{113 unsigned long long num;114 115 num = (unsigned long long)parent_rate * m;116 do_div(num, n);117 return num;118}119 120/*121 * _dpll_test_mult - test a DPLL multiplier value122 * @m: pointer to the DPLL m (multiplier) value under test123 * @n: current DPLL n (divider) value under test124 * @new_rate: pointer to storage for the resulting rounded rate125 * @target_rate: the desired DPLL rate126 * @parent_rate: the DPLL's parent clock rate127 *128 * This code tests a DPLL multiplier value, ensuring that the129 * resulting rate will not be higher than the target_rate, and that130 * the multiplier value itself is valid for the DPLL. Initially, the131 * integer pointed to by the m argument should be prescaled by132 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with133 * a non-scaled m upon return. This non-scaled m will result in a134 * new_rate as close as possible to target_rate (but not greater than135 * target_rate) given the current (parent_rate, n, prescaled m)136 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the137 * non-scaled m attempted to underflow, which can allow the calling138 * function to bail out early; or 0 upon success.139 */140static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,141 unsigned long target_rate,142 unsigned long parent_rate)143{144 int r = 0, carry = 0;145 146 /* Unscale m and round if necessary */147 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)148 carry = 1;149 *m = (*m / DPLL_SCALE_FACTOR) + carry;150 151 /*152 * The new rate must be <= the target rate to avoid programming153 * a rate that is impossible for the hardware to handle154 */155 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);156 if (*new_rate > target_rate) {157 (*m)--;158 *new_rate = 0;159 }160 161 /* Guard against m underflow */162 if (*m < DPLL_MIN_MULTIPLIER) {163 *m = DPLL_MIN_MULTIPLIER;164 *new_rate = 0;165 r = DPLL_MULT_UNDERFLOW;166 }167 168 if (*new_rate == 0)169 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);170 171 return r;172}173 174/**175 * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not176 * @v: bitfield value of the DPLL enable177 *178 * Checks given DPLL enable bitfield to see whether the DPLL is in bypass179 * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise.180 */181static int _omap2_dpll_is_in_bypass(u32 v)182{183 u8 mask, val;184 185 mask = ti_clk_get_features()->dpll_bypass_vals;186 187 /*188 * Each set bit in the mask corresponds to a bypass value equal189 * to the bitshift. Go through each set-bit in the mask and190 * compare against the given register value.191 */192 while (mask) {193 val = __ffs(mask);194 mask ^= (1 << val);195 if (v == val)196 return 1;197 }198 199 return 0;200}201 202/* Public functions */203u8 omap2_init_dpll_parent(struct clk_hw *hw)204{205 struct clk_hw_omap *clk = to_clk_hw_omap(hw);206 u32 v;207 struct dpll_data *dd;208 209 dd = clk->dpll_data;210 if (!dd)211 return -EINVAL;212 213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);214 v &= dd->enable_mask;215 v >>= __ffs(dd->enable_mask);216 217 /* Reparent the struct clk in case the dpll is in bypass */218 if (_omap2_dpll_is_in_bypass(v))219 return 1;220 221 return 0;222}223 224/**225 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate226 * @clk: struct clk * of a DPLL227 *228 * DPLLs can be locked or bypassed - basically, enabled or disabled.229 * When locked, the DPLL output depends on the M and N values. When230 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock231 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and232 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively233 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.234 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is235 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0236 * if the clock @clk is not a DPLL.237 */238unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)239{240 u64 dpll_clk;241 u32 dpll_mult, dpll_div, v;242 struct dpll_data *dd;243 244 dd = clk->dpll_data;245 if (!dd)246 return 0;247 248 /* Return bypass rate if DPLL is bypassed */249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);250 v &= dd->enable_mask;251 v >>= __ffs(dd->enable_mask);252 253 if (_omap2_dpll_is_in_bypass(v))254 return clk_hw_get_rate(dd->clk_bypass);255 256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);257 dpll_mult = v & dd->mult_mask;258 dpll_mult >>= __ffs(dd->mult_mask);259 dpll_div = v & dd->div1_mask;260 dpll_div >>= __ffs(dd->div1_mask);261 262 dpll_clk = (u64)clk_hw_get_rate(dd->clk_ref) * dpll_mult;263 do_div(dpll_clk, dpll_div + 1);264 265 return dpll_clk;266}267 268/* DPLL rate rounding code */269 270/**271 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL272 * @hw: struct clk_hw containing the struct clk * for a DPLL273 * @target_rate: desired DPLL clock rate274 * @parent_rate: parent's DPLL clock rate275 *276 * Given a DPLL and a desired target rate, round the target rate to a277 * possible, programmable rate for this DPLL. Attempts to select the278 * minimum possible n. Stores the computed (m, n) in the DPLL's279 * dpll_data structure so set_rate() will not need to call this280 * (expensive) function again. Returns ~0 if the target rate cannot281 * be rounded, or the rounded rate upon success.282 */283long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,284 unsigned long *parent_rate)285{286 struct clk_hw_omap *clk = to_clk_hw_omap(hw);287 int m, n, r, scaled_max_m;288 int min_delta_m = INT_MAX, min_delta_n = INT_MAX;289 unsigned long scaled_rt_rp;290 unsigned long new_rate = 0;291 struct dpll_data *dd;292 unsigned long ref_rate;293 long delta;294 long prev_min_delta = LONG_MAX;295 const char *clk_name;296 297 if (!clk || !clk->dpll_data)298 return ~0;299 300 dd = clk->dpll_data;301 302 if (dd->max_rate && target_rate > dd->max_rate)303 target_rate = dd->max_rate;304 305 ref_rate = clk_hw_get_rate(dd->clk_ref);306 clk_name = clk_hw_get_name(hw);307 pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",308 clk_name, target_rate);309 310 scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);311 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;312 313 dd->last_rounded_rate = 0;314 315 for (n = dd->min_divider; n <= dd->max_divider; n++) {316 /* Is the (input clk, divider) pair valid for the DPLL? */317 r = _dpll_test_fint(clk, n);318 if (r == DPLL_FINT_UNDERFLOW)319 break;320 else if (r == DPLL_FINT_INVALID)321 continue;322 323 /* Compute the scaled DPLL multiplier, based on the divider */324 m = scaled_rt_rp * n;325 326 /*327 * Since we're counting n up, a m overflow means we328 * can bail out completely (since as n increases in329 * the next iteration, there's no way that m can330 * increase beyond the current m)331 */332 if (m > scaled_max_m)333 break;334 335 r = _dpll_test_mult(&m, n, &new_rate, target_rate,336 ref_rate);337 338 /* m can't be set low enough for this n - try with a larger n */339 if (r == DPLL_MULT_UNDERFLOW)340 continue;341 342 /* skip rates above our target rate */343 delta = target_rate - new_rate;344 if (delta < 0)345 continue;346 347 if (delta < prev_min_delta) {348 prev_min_delta = delta;349 min_delta_m = m;350 min_delta_n = n;351 }352 353 pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",354 clk_name, m, n, new_rate);355 356 if (delta == 0)357 break;358 }359 360 if (prev_min_delta == LONG_MAX) {361 pr_debug("clock: %s: cannot round to rate %lu\n",362 clk_name, target_rate);363 return ~0;364 }365 366 dd->last_rounded_m = min_delta_m;367 dd->last_rounded_n = min_delta_n;368 dd->last_rounded_rate = target_rate - prev_min_delta;369 370 return dd->last_rounded_rate;371}372