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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (C) 2016 Socionext Inc.4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>5 */6 7#include <linux/stddef.h>8 9#include "clk-uniphier.h"10 11#define UNIPHIER_LD4_SYS_CLK_SD \12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)14 15#define UNIPHIER_PRO5_SYS_CLK_SD \16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)18 19#define UNIPHIER_LD20_SYS_CLK_SD \20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)22 23#define UNIPHIER_NX1_SYS_CLK_SD \24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)26 27#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)30 31#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)34 35#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)38 39#define UNIPHIER_SYS_CLK_NAND_4X(idx) \40 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)41 42#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)44 45#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)47 48#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)50 51#define UNIPHIER_LD11_SYS_CLK_HSC(idx) \52 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)53 54#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)56 57#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))59 60#define UNIPHIER_PRO4_SYS_CLK_AIO(idx) \61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)63 64#define UNIPHIER_PRO5_SYS_CLK_AIO(idx) \65 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)67 68#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \69 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \70 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)71 72#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \73 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \74 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)75 76#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \77 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)79 80#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \81 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)82 83#define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \84 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)85 86const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */91 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),92 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),93 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),94 UNIPHIER_LD4_SYS_CLK_NAND(2),95 UNIPHIER_SYS_CLK_NAND_4X(3),96 UNIPHIER_LD4_SYS_CLK_SD,97 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),98 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */99 { /* sentinel */ }100};101 102const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */108 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),109 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),110 UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),111 UNIPHIER_LD4_SYS_CLK_NAND(2),112 UNIPHIER_SYS_CLK_NAND_4X(3),113 UNIPHIER_LD4_SYS_CLK_SD,114 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),115 UNIPHIER_PRO4_SYS_CLK_ETHER(6),116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),117 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */118 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),119 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */120 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),121 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),122 UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),123 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),124 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),125 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),126 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),127 UNIPHIER_PRO4_SYS_CLK_AIO(40),128 { /* sentinel */ }129};130 131const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */133 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */134 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */135 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),136 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),137 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),138 UNIPHIER_LD4_SYS_CLK_NAND(2),139 UNIPHIER_SYS_CLK_NAND_4X(3),140 UNIPHIER_LD4_SYS_CLK_SD,141 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),142 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */143 { /* sentinel */ }144};145 146const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {147 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */148 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */149 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */150 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),151 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),152 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),153 UNIPHIER_PRO5_SYS_CLK_NAND(2),154 UNIPHIER_SYS_CLK_NAND_4X(3),155 UNIPHIER_PRO5_SYS_CLK_SD,156 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */157 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */158 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),159 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),160 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),161 UNIPHIER_PRO5_SYS_CLK_AIO(40),162 { /* sentinel */ }163};164 165const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {166 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */167 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),168 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),169 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),170 UNIPHIER_PRO5_SYS_CLK_NAND(2),171 UNIPHIER_SYS_CLK_NAND_4X(3),172 UNIPHIER_PRO5_SYS_CLK_SD,173 UNIPHIER_PRO4_SYS_CLK_ETHER(6),174 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */175 /* GIO is always clock-enabled: no function for 0x2104 bit6 */176 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),177 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),178 /* The document mentions 0x2104 bit 18, but not functional */179 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),180 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),181 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),182 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),183 UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),184 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),185 UNIPHIER_PRO5_SYS_CLK_AIO(40),186 { /* sentinel */ }187};188 189const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {190 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */191 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */192 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */193 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */194 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),195 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),196 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),197 UNIPHIER_LD11_SYS_CLK_NAND(2),198 UNIPHIER_SYS_CLK_NAND_4X(3),199 UNIPHIER_LD11_SYS_CLK_EMMC(4),200 /* Index 5 reserved for eMMC PHY */201 UNIPHIER_LD11_SYS_CLK_ETHER(6),202 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */203 UNIPHIER_LD11_SYS_CLK_HSC(9),204 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),205 UNIPHIER_LD11_SYS_CLK_AIO(40),206 UNIPHIER_LD11_SYS_CLK_EVEA(41),207 UNIPHIER_LD11_SYS_CLK_EXIV(42),208 /* CPU gears */209 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),210 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),211 UNIPHIER_CLK_DIV3("spll", 3, 4, 8),212 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */213 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,214 "cpll/2", "spll/4", "cpll/3", "spll/3",215 "spll/4", "spll/8", "cpll/4", "cpll/8"),216 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,217 "mpll/2", "spll/4", "mpll/3", "spll/3",218 "spll/4", "spll/8", "mpll/4", "mpll/8"),219 { /* sentinel */ }220};221 222const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {223 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */224 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */225 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */226 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */227 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */228 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */229 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),230 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),231 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),232 UNIPHIER_LD11_SYS_CLK_NAND(2),233 UNIPHIER_SYS_CLK_NAND_4X(3),234 UNIPHIER_LD11_SYS_CLK_EMMC(4),235 /* Index 5 reserved for eMMC PHY */236 UNIPHIER_LD20_SYS_CLK_SD,237 UNIPHIER_LD11_SYS_CLK_ETHER(6),238 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */239 UNIPHIER_LD11_SYS_CLK_HSC(9),240 /* GIO is always clock-enabled: no function for 0x210c bit5 */241 /*242 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.243 * We do not use bit 15 here.244 */245 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),246 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),247 UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),248 UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),249 UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),250 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),251 UNIPHIER_LD11_SYS_CLK_AIO(40),252 UNIPHIER_LD11_SYS_CLK_EVEA(41),253 UNIPHIER_LD11_SYS_CLK_EXIV(42),254 /* CPU gears */255 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),256 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),257 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),258 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,259 "cpll/2", "spll/2", "cpll/3", "spll/3",260 "spll/4", "spll/8", "cpll/4", "cpll/8"),261 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,262 "cpll/2", "spll/2", "cpll/3", "spll/3",263 "spll/4", "spll/8", "cpll/4", "cpll/8"),264 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,265 "s2pll/2", "spll/2", "s2pll/3", "spll/3",266 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),267 { /* sentinel */ }268};269 270const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {271 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */272 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */273 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */274 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),275 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),276 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),277 UNIPHIER_LD20_SYS_CLK_SD,278 UNIPHIER_LD11_SYS_CLK_NAND(2),279 UNIPHIER_SYS_CLK_NAND_4X(3),280 UNIPHIER_LD11_SYS_CLK_EMMC(4),281 UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),282 UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),283 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */284 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */285 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */286 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),287 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),288 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),289 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),290 UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),291 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),292 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),293 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),294 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),295 UNIPHIER_LD11_SYS_CLK_AIO(40),296 UNIPHIER_LD11_SYS_CLK_EXIV(42),297 /* CPU gears */298 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),299 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),300 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),301 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,302 "cpll/2", "spll/2", "cpll/3", "spll/3",303 "spll/4", "spll/8", "cpll/4", "cpll/8"),304 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,305 "s2pll/2", "spll/2", "s2pll/3", "spll/3",306 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),307 { /* sentinel */ }308};309 310const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = {311 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 100, 1), /* ARM: 2500 MHz */312 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 32, 1), /* 800 MHz */313 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),314 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),315 UNIPHIER_NX1_SYS_CLK_SD,316 UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),317 UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0),318 UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */319 UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */320 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),321 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),322 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),323 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8),324 UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0),325 UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8),326 /* CPU gears */327 UNIPHIER_CLK_DIV5("cpll", 2, 4, 8, 16, 32),328 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,329 "cpll/2", "cpll/4", "cpll/8", "cpll/16",330 "cpll/32"),331 { /* sentinel */ }332};333 334const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = {335 UNIPHIER_CLK_DIV("gpll", 4),336 {337 .name = "sata-ref",338 .type = UNIPHIER_CLK_TYPE_MUX,339 .idx = 0,340 .data.mux = {341 .parent_names = { "gpll/4", "ref", },342 .num_parents = 2,343 .reg = 0x1a28,344 .masks = { 0x1, 0x1, },345 .vals = { 0x0, 0x1, },346 },347 },348 { /* sentinel */ }349};350