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1// SPDX-License-Identifier: GPL-2.02/*3 * J-Core SoC PIT/clocksource driver4 *5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.6 */7 8#include <linux/kernel.h>9#include <linux/slab.h>10#include <linux/interrupt.h>11#include <linux/clockchips.h>12#include <linux/clocksource.h>13#include <linux/sched_clock.h>14#include <linux/cpu.h>15#include <linux/cpuhotplug.h>16#include <linux/of_address.h>17#include <linux/of_irq.h>18 19#define PIT_IRQ_SHIFT 1220#define PIT_PRIO_SHIFT 2021#define PIT_ENABLE_SHIFT 2622#define PIT_PRIO_MASK 0xf23 24#define REG_PITEN 0x0025#define REG_THROT 0x1026#define REG_COUNT 0x1427#define REG_BUSPD 0x1828#define REG_SECHI 0x2029#define REG_SECLO 0x2430#define REG_NSEC 0x2831 32struct jcore_pit {33 struct clock_event_device ced;34 void __iomem *base;35 unsigned long periodic_delta;36 u32 enable_val;37};38 39static void __iomem *jcore_pit_base;40static struct jcore_pit __percpu *jcore_pit_percpu;41 42static notrace u64 jcore_sched_clock_read(void)43{44 u32 seclo, nsec, seclo0;45 __iomem void *base = jcore_pit_base;46 47 seclo = readl(base + REG_SECLO);48 do {49 seclo0 = seclo;50 nsec = readl(base + REG_NSEC);51 seclo = readl(base + REG_SECLO);52 } while (seclo0 != seclo);53 54 return seclo * NSEC_PER_SEC + nsec;55}56 57static u64 jcore_clocksource_read(struct clocksource *cs)58{59 return jcore_sched_clock_read();60}61 62static int jcore_pit_disable(struct jcore_pit *pit)63{64 writel(0, pit->base + REG_PITEN);65 return 0;66}67 68static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)69{70 jcore_pit_disable(pit);71 writel(delta, pit->base + REG_THROT);72 writel(pit->enable_val, pit->base + REG_PITEN);73 return 0;74}75 76static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)77{78 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);79 80 return jcore_pit_disable(pit);81}82 83static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)84{85 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);86 87 return jcore_pit_disable(pit);88}89 90static int jcore_pit_set_state_periodic(struct clock_event_device *ced)91{92 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);93 94 return jcore_pit_set(pit->periodic_delta, pit);95}96 97static int jcore_pit_set_next_event(unsigned long delta,98 struct clock_event_device *ced)99{100 struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);101 102 return jcore_pit_set(delta, pit);103}104 105static int jcore_pit_local_init(unsigned cpu)106{107 struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);108 unsigned buspd, freq;109 110 pr_info("Local J-Core PIT init on cpu %u\n", cpu);111 112 buspd = readl(pit->base + REG_BUSPD);113 freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);114 pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);115 116 clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);117 118 return 0;119}120 121static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)122{123 struct jcore_pit *pit = dev_id;124 125 if (clockevent_state_oneshot(&pit->ced))126 jcore_pit_disable(pit);127 128 pit->ced.event_handler(&pit->ced);129 130 return IRQ_HANDLED;131}132 133static int __init jcore_pit_init(struct device_node *node)134{135 int err;136 unsigned pit_irq, cpu;137 unsigned long hwirq;138 u32 irqprio, enable_val;139 140 jcore_pit_base = of_iomap(node, 0);141 if (!jcore_pit_base) {142 pr_err("Error: Cannot map base address for J-Core PIT\n");143 return -ENXIO;144 }145 146 pit_irq = irq_of_parse_and_map(node, 0);147 if (!pit_irq) {148 pr_err("Error: J-Core PIT has no IRQ\n");149 return -ENXIO;150 }151 152 pr_info("Initializing J-Core PIT at %p IRQ %d\n",153 jcore_pit_base, pit_irq);154 155 err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",156 NSEC_PER_SEC, 400, 32,157 jcore_clocksource_read);158 if (err) {159 pr_err("Error registering clocksource device: %d\n", err);160 return err;161 }162 163 sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);164 165 jcore_pit_percpu = alloc_percpu(struct jcore_pit);166 if (!jcore_pit_percpu) {167 pr_err("Failed to allocate memory for clock event device\n");168 return -ENOMEM;169 }170 171 err = request_percpu_irq(pit_irq, jcore_timer_interrupt,172 "jcore_pit", jcore_pit_percpu);173 if (err) {174 pr_err("pit irq request failed: %d\n", err);175 free_percpu(jcore_pit_percpu);176 return err;177 }178 179 /*180 * The J-Core PIT is not hard-wired to a particular IRQ, but181 * integrated with the interrupt controller such that the IRQ it182 * generates is programmable, as follows:183 *184 * The bit layout of the PIT enable register is:185 *186 * .....e..ppppiiiiiiii............187 *188 * where the .'s indicate unrelated/unused bits, e is enable,189 * p is priority, and i is hard irq number.190 *191 * For the PIT included in AIC1 (obsolete but still in use),192 * any hard irq (trap number) can be programmed via the 8193 * iiiiiiii bits, and a priority (0-15) is programmable194 * separately in the pppp bits.195 *196 * For the PIT included in AIC2 (current), the programming197 * interface is equivalent modulo interrupt mapping. This is198 * why a different compatible tag was not used. However only199 * traps 64-127 (the ones actually intended to be used for200 * interrupts, rather than syscalls/exceptions/etc.) can be201 * programmed (the high 2 bits of i are ignored) and the202 * priority pppp is <<2'd and or'd onto the irq number. This203 * choice seems to have been made on the hardware engineering204 * side under an assumption that preserving old AIC1 priority205 * mappings was important. Future models will likely ignore206 * the pppp field.207 */208 hwirq = irq_get_irq_data(pit_irq)->hwirq;209 irqprio = (hwirq >> 2) & PIT_PRIO_MASK;210 enable_val = (1U << PIT_ENABLE_SHIFT)211 | (hwirq << PIT_IRQ_SHIFT)212 | (irqprio << PIT_PRIO_SHIFT);213 214 for_each_present_cpu(cpu) {215 struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);216 217 pit->base = of_iomap(node, cpu);218 if (!pit->base) {219 pr_err("Unable to map PIT for cpu %u\n", cpu);220 continue;221 }222 223 pit->ced.name = "jcore_pit";224 pit->ced.features = CLOCK_EVT_FEAT_PERIODIC225 | CLOCK_EVT_FEAT_ONESHOT226 | CLOCK_EVT_FEAT_PERCPU;227 pit->ced.cpumask = cpumask_of(cpu);228 pit->ced.rating = 400;229 pit->ced.irq = pit_irq;230 pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;231 pit->ced.set_state_periodic = jcore_pit_set_state_periodic;232 pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;233 pit->ced.set_next_event = jcore_pit_set_next_event;234 235 pit->enable_val = enable_val;236 }237 238 cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,239 "clockevents/jcore:starting",240 jcore_pit_local_init, NULL);241 242 return 0;243}244 245TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);246