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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * This file contains driver for the Cadence Triple Timer Counter Rev 064 *5 * Copyright (C) 2011-2013 Xilinx6 *7 * based on arch/mips/kernel/time.c timer driver8 */9 10#include <linux/clk.h>11#include <linux/interrupt.h>12#include <linux/clockchips.h>13#include <linux/clocksource.h>14#include <linux/of_address.h>15#include <linux/of_irq.h>16#include <linux/platform_device.h>17#include <linux/slab.h>18#include <linux/sched_clock.h>19#include <linux/module.h>20#include <linux/of_platform.h>21 22/*23 * This driver configures the 2 16/32-bit count-up timers as follows:24 *25 * T1: Timer 1, clocksource for generic timekeeping26 * T2: Timer 2, clockevent source for hrtimers27 * T3: Timer 3, <unused>28 *29 * The input frequency to the timer module for emulation is 2.5MHz which is30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,31 * the timers are clocked at 78.125KHz (12.8 us resolution).32 33 * The input frequency to the timer module in silicon is configurable and34 * obtained from device tree. The pre-scaler of 32 is used.35 */36 37/*38 * Timer Register Offset Definitions of Timer 1, Increment base address by 439 * and use same offsets for Timer 240 */41#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */42#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */43#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */44#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */45#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */46#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */47 48#define TTC_CNT_CNTRL_DISABLE_MASK 0x149 50#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */51#define TTC_CLK_CNTRL_PSV_MASK 0x1e52#define TTC_CLK_CNTRL_PSV_SHIFT 153 54/*55 * Setup the timers to use pre-scaling, using a fixed value for now that will56 * work across most input frequency, but it may need to be more dynamic57 */58#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */59#define PRESCALE 2048 /* The exponent must match this */60#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)61#define CLK_CNTRL_PRESCALE_EN 162#define CNT_CNTRL_RESET (1 << 4)63 64#define MAX_F_ERR 5065 66/**67 * struct ttc_timer - This definition defines local timer structure68 *69 * @base_addr: Base address of timer70 * @freq: Timer input clock frequency71 * @clk: Associated clock source72 * @clk_rate_change_nb: Notifier block for clock rate changes73 */74struct ttc_timer {75 void __iomem *base_addr;76 unsigned long freq;77 struct clk *clk;78 struct notifier_block clk_rate_change_nb;79};80 81#define to_ttc_timer(x) \82 container_of(x, struct ttc_timer, clk_rate_change_nb)83 84struct ttc_timer_clocksource {85 u32 scale_clk_ctrl_reg_old;86 u32 scale_clk_ctrl_reg_new;87 struct ttc_timer ttc;88 struct clocksource cs;89};90 91#define to_ttc_timer_clksrc(x) \92 container_of(x, struct ttc_timer_clocksource, cs)93 94struct ttc_timer_clockevent {95 struct ttc_timer ttc;96 struct clock_event_device ce;97};98 99#define to_ttc_timer_clkevent(x) \100 container_of(x, struct ttc_timer_clockevent, ce)101 102static void __iomem *ttc_sched_clock_val_reg;103 104/**105 * ttc_set_interval - Set the timer interval value106 *107 * @timer: Pointer to the timer instance108 * @cycles: Timer interval ticks109 **/110static void ttc_set_interval(struct ttc_timer *timer,111 unsigned long cycles)112{113 u32 ctrl_reg;114 115 /* Disable the counter, set the counter value and re-enable counter */116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);119 120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);121 122 /*123 * Reset the counter (0x10) so that it starts from 0, one-shot124 * mode makes this needed for timing to be right.125 */126 ctrl_reg |= CNT_CNTRL_RESET;127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);129}130 131/**132 * ttc_clock_event_interrupt - Clock event timer interrupt handler133 *134 * @irq: IRQ number of the Timer135 * @dev_id: void pointer to the ttc_timer instance136 *137 * Returns: Always IRQ_HANDLED - success138 **/139static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)140{141 struct ttc_timer_clockevent *ttce = dev_id;142 struct ttc_timer *timer = &ttce->ttc;143 144 /* Acknowledge the interrupt and call event handler */145 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);146 147 ttce->ce.event_handler(&ttce->ce);148 149 return IRQ_HANDLED;150}151 152/**153 * __ttc_clocksource_read - Reads the timer counter register154 * @cs: &clocksource to read from155 *156 * Returns: Current timer counter register value157 **/158static u64 __ttc_clocksource_read(struct clocksource *cs)159{160 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;161 162 return (u64)readl_relaxed(timer->base_addr +163 TTC_COUNT_VAL_OFFSET);164}165 166static u64 notrace ttc_sched_clock_read(void)167{168 return readl_relaxed(ttc_sched_clock_val_reg);169}170 171/**172 * ttc_set_next_event - Sets the time interval for next event173 *174 * @cycles: Timer interval ticks175 * @evt: Address of clock event instance176 *177 * Returns: Always %0 - success178 **/179static int ttc_set_next_event(unsigned long cycles,180 struct clock_event_device *evt)181{182 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);183 struct ttc_timer *timer = &ttce->ttc;184 185 ttc_set_interval(timer, cycles);186 return 0;187}188 189/**190 * ttc_shutdown - Sets the state of timer191 * @evt: Address of clock event instance192 *193 * Used for shutdown or oneshot.194 *195 * Returns: Always %0 - success196 **/197static int ttc_shutdown(struct clock_event_device *evt)198{199 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);200 struct ttc_timer *timer = &ttce->ttc;201 u32 ctrl_reg;202 203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);204 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);206 return 0;207}208 209/**210 * ttc_set_periodic - Sets the state of timer211 * @evt: Address of clock event instance212 *213 * Returns: Always %0 - success214 */215static int ttc_set_periodic(struct clock_event_device *evt)216{217 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);218 struct ttc_timer *timer = &ttce->ttc;219 220 ttc_set_interval(timer,221 DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));222 return 0;223}224 225static int ttc_resume(struct clock_event_device *evt)226{227 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);228 struct ttc_timer *timer = &ttce->ttc;229 u32 ctrl_reg;230 231 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);232 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;233 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);234 return 0;235}236 237static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,238 unsigned long event, void *data)239{240 struct clk_notifier_data *ndata = data;241 struct ttc_timer *ttc = to_ttc_timer(nb);242 struct ttc_timer_clocksource *ttccs = container_of(ttc,243 struct ttc_timer_clocksource, ttc);244 245 switch (event) {246 case PRE_RATE_CHANGE:247 {248 u32 psv;249 unsigned long factor, rate_low, rate_high;250 251 if (ndata->new_rate > ndata->old_rate) {252 factor = DIV_ROUND_CLOSEST(ndata->new_rate,253 ndata->old_rate);254 rate_low = ndata->old_rate;255 rate_high = ndata->new_rate;256 } else {257 factor = DIV_ROUND_CLOSEST(ndata->old_rate,258 ndata->new_rate);259 rate_low = ndata->new_rate;260 rate_high = ndata->old_rate;261 }262 263 if (!is_power_of_2(factor))264 return NOTIFY_BAD;265 266 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)267 return NOTIFY_BAD;268 269 factor = __ilog2_u32(factor);270 271 /*272 * store timer clock ctrl register so we can restore it in case273 * of an abort.274 */275 ttccs->scale_clk_ctrl_reg_old =276 readl_relaxed(ttccs->ttc.base_addr +277 TTC_CLK_CNTRL_OFFSET);278 279 psv = (ttccs->scale_clk_ctrl_reg_old &280 TTC_CLK_CNTRL_PSV_MASK) >>281 TTC_CLK_CNTRL_PSV_SHIFT;282 if (ndata->new_rate < ndata->old_rate)283 psv -= factor;284 else285 psv += factor;286 287 /* prescaler within legal range? */288 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))289 return NOTIFY_BAD;290 291 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &292 ~TTC_CLK_CNTRL_PSV_MASK;293 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;294 295 296 /* scale down: adjust divider in post-change notification */297 if (ndata->new_rate < ndata->old_rate)298 return NOTIFY_DONE;299 300 /* scale up: adjust divider now - before frequency change */301 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,302 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);303 break;304 }305 case POST_RATE_CHANGE:306 /* scale up: pre-change notification did the adjustment */307 if (ndata->new_rate > ndata->old_rate)308 return NOTIFY_OK;309 310 /* scale down: adjust divider now - after frequency change */311 writel_relaxed(ttccs->scale_clk_ctrl_reg_new,312 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);313 break;314 315 case ABORT_RATE_CHANGE:316 /* we have to undo the adjustment in case we scale up */317 if (ndata->new_rate < ndata->old_rate)318 return NOTIFY_OK;319 320 /* restore original register value */321 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,322 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);323 fallthrough;324 default:325 return NOTIFY_DONE;326 }327 328 return NOTIFY_DONE;329}330 331static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,332 u32 timer_width)333{334 struct ttc_timer_clocksource *ttccs;335 int err;336 337 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);338 if (!ttccs)339 return -ENOMEM;340 341 ttccs->ttc.clk = clk;342 343 err = clk_prepare_enable(ttccs->ttc.clk);344 if (err) {345 kfree(ttccs);346 return err;347 }348 349 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);350 351 ttccs->ttc.clk_rate_change_nb.notifier_call =352 ttc_rate_change_clocksource_cb;353 ttccs->ttc.clk_rate_change_nb.next = NULL;354 355 err = clk_notifier_register(ttccs->ttc.clk,356 &ttccs->ttc.clk_rate_change_nb);357 if (err)358 pr_warn("Unable to register clock notifier.\n");359 360 ttccs->ttc.base_addr = base;361 ttccs->cs.name = "ttc_clocksource";362 ttccs->cs.rating = 200;363 ttccs->cs.read = __ttc_clocksource_read;364 ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);365 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;366 367 /*368 * Setup the clock source counter to be an incrementing counter369 * with no interrupt and it rolls over at 0xFFFF. Pre-scale370 * it by 32 also. Let it start running now.371 */372 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);373 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,374 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);375 writel_relaxed(CNT_CNTRL_RESET,376 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);377 378 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);379 if (err) {380 kfree(ttccs);381 return err;382 }383 384 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;385 sched_clock_register(ttc_sched_clock_read, timer_width,386 ttccs->ttc.freq / PRESCALE);387 388 return 0;389}390 391static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,392 unsigned long event, void *data)393{394 struct clk_notifier_data *ndata = data;395 struct ttc_timer *ttc = to_ttc_timer(nb);396 struct ttc_timer_clockevent *ttcce = container_of(ttc,397 struct ttc_timer_clockevent, ttc);398 399 switch (event) {400 case POST_RATE_CHANGE:401 /* update cached frequency */402 ttc->freq = ndata->new_rate;403 404 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);405 406 fallthrough;407 case PRE_RATE_CHANGE:408 case ABORT_RATE_CHANGE:409 default:410 return NOTIFY_DONE;411 }412}413 414static int __init ttc_setup_clockevent(struct clk *clk,415 void __iomem *base, u32 irq)416{417 struct ttc_timer_clockevent *ttcce;418 int err;419 420 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);421 if (!ttcce)422 return -ENOMEM;423 424 ttcce->ttc.clk = clk;425 426 err = clk_prepare_enable(ttcce->ttc.clk);427 if (err)428 goto out_kfree;429 430 ttcce->ttc.clk_rate_change_nb.notifier_call =431 ttc_rate_change_clockevent_cb;432 ttcce->ttc.clk_rate_change_nb.next = NULL;433 434 err = clk_notifier_register(ttcce->ttc.clk,435 &ttcce->ttc.clk_rate_change_nb);436 if (err) {437 pr_warn("Unable to register clock notifier.\n");438 goto out_clk_unprepare;439 }440 441 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);442 443 ttcce->ttc.base_addr = base;444 ttcce->ce.name = "ttc_clockevent";445 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;446 ttcce->ce.set_next_event = ttc_set_next_event;447 ttcce->ce.set_state_shutdown = ttc_shutdown;448 ttcce->ce.set_state_periodic = ttc_set_periodic;449 ttcce->ce.set_state_oneshot = ttc_shutdown;450 ttcce->ce.tick_resume = ttc_resume;451 ttcce->ce.rating = 200;452 ttcce->ce.irq = irq;453 ttcce->ce.cpumask = cpu_possible_mask;454 455 /*456 * Setup the clock event timer to be an interval timer which457 * is prescaled by 32 using the interval interrupt. Leave it458 * disabled for now.459 */460 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);461 writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,462 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);463 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);464 465 err = request_irq(irq, ttc_clock_event_interrupt,466 IRQF_TIMER, ttcce->ce.name, ttcce);467 if (err)468 goto out_clk_unprepare;469 470 clockevents_config_and_register(&ttcce->ce,471 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);472 473 return 0;474 475out_clk_unprepare:476 clk_disable_unprepare(ttcce->ttc.clk);477out_kfree:478 kfree(ttcce);479 return err;480}481 482static int __init ttc_timer_probe(struct platform_device *pdev)483{484 unsigned int irq;485 void __iomem *timer_baseaddr;486 struct clk *clk_cs, *clk_ce;487 static int initialized;488 int clksel, ret;489 u32 timer_width = 16;490 struct device_node *timer = pdev->dev.of_node;491 492 if (initialized)493 return 0;494 495 initialized = 1;496 497 /*498 * Get the 1st Triple Timer Counter (TTC) block from the device tree499 * and use it. Note that the event timer uses the interrupt and it's the500 * 2nd TTC hence the irq_of_parse_and_map(,1)501 */502 timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL);503 if (IS_ERR(timer_baseaddr)) {504 pr_err("ERROR: invalid timer base address\n");505 return PTR_ERR(timer_baseaddr);506 }507 508 irq = irq_of_parse_and_map(timer, 1);509 if (irq <= 0) {510 pr_err("ERROR: invalid interrupt number\n");511 return -EINVAL;512 }513 514 of_property_read_u32(timer, "timer-width", &timer_width);515 516 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);517 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);518 clk_cs = of_clk_get(timer, clksel);519 if (IS_ERR(clk_cs)) {520 pr_err("ERROR: timer input clock not found\n");521 return PTR_ERR(clk_cs);522 }523 524 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);525 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);526 clk_ce = of_clk_get(timer, clksel);527 if (IS_ERR(clk_ce)) {528 pr_err("ERROR: timer input clock not found\n");529 ret = PTR_ERR(clk_ce);530 goto put_clk_cs;531 }532 533 ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);534 if (ret)535 goto put_clk_ce;536 537 ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);538 if (ret)539 goto put_clk_ce;540 541 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);542 543 return 0;544 545put_clk_ce:546 clk_put(clk_ce);547put_clk_cs:548 clk_put(clk_cs);549 return ret;550}551 552static const struct of_device_id ttc_timer_of_match[] = {553 {.compatible = "cdns,ttc"},554 {},555};556 557MODULE_DEVICE_TABLE(of, ttc_timer_of_match);558 559static struct platform_driver ttc_timer_driver = {560 .driver = {561 .name = "cdns_ttc_timer",562 .of_match_table = ttc_timer_of_match,563 },564};565builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);566