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1// SPDX-License-Identifier: GPL-2.02/*3 * STM32 Timer Encoder and Counter driver4 *5 * Copyright (C) STMicroelectronics 20186 *7 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>8 *9 */10#include <linux/counter.h>11#include <linux/interrupt.h>12#include <linux/mfd/stm32-timers.h>13#include <linux/mod_devicetable.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/pinctrl/consumer.h>17#include <linux/platform_device.h>18#include <linux/types.h>19 20#define TIM_CCMR_CCXS (BIT(8) | BIT(0))21#define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \22 TIM_CCMR_IC1F | TIM_CCMR_IC2F)23#define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \24 TIM_CCER_CC2P | TIM_CCER_CC2NP)25 26#define STM32_CH1_SIG 027#define STM32_CH2_SIG 128#define STM32_CLOCK_SIG 229#define STM32_CH3_SIG 330#define STM32_CH4_SIG 431 32struct stm32_timer_regs {33 u32 cr1;34 u32 cnt;35 u32 smcr;36 u32 arr;37};38 39struct stm32_timer_cnt {40 struct regmap *regmap;41 struct clk *clk;42 u32 max_arr;43 bool enabled;44 struct stm32_timer_regs bak;45 bool has_encoder;46 unsigned int nchannels;47 unsigned int nr_irqs;48 spinlock_t lock; /* protects nb_ovf */49 u64 nb_ovf;50};51 52static const enum counter_function stm32_count_functions[] = {53 COUNTER_FUNCTION_INCREASE,54 COUNTER_FUNCTION_QUADRATURE_X2_A,55 COUNTER_FUNCTION_QUADRATURE_X2_B,56 COUNTER_FUNCTION_QUADRATURE_X4,57};58 59static int stm32_count_read(struct counter_device *counter,60 struct counter_count *count, u64 *val)61{62 struct stm32_timer_cnt *const priv = counter_priv(counter);63 u32 cnt;64 65 regmap_read(priv->regmap, TIM_CNT, &cnt);66 *val = cnt;67 68 return 0;69}70 71static int stm32_count_write(struct counter_device *counter,72 struct counter_count *count, const u64 val)73{74 struct stm32_timer_cnt *const priv = counter_priv(counter);75 u32 ceiling;76 77 regmap_read(priv->regmap, TIM_ARR, &ceiling);78 if (val > ceiling)79 return -EINVAL;80 81 return regmap_write(priv->regmap, TIM_CNT, val);82}83 84static int stm32_count_function_read(struct counter_device *counter,85 struct counter_count *count,86 enum counter_function *function)87{88 struct stm32_timer_cnt *const priv = counter_priv(counter);89 u32 smcr;90 91 regmap_read(priv->regmap, TIM_SMCR, &smcr);92 93 switch (smcr & TIM_SMCR_SMS) {94 case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:95 *function = COUNTER_FUNCTION_INCREASE;96 return 0;97 case TIM_SMCR_SMS_ENCODER_MODE_1:98 *function = COUNTER_FUNCTION_QUADRATURE_X2_A;99 return 0;100 case TIM_SMCR_SMS_ENCODER_MODE_2:101 *function = COUNTER_FUNCTION_QUADRATURE_X2_B;102 return 0;103 case TIM_SMCR_SMS_ENCODER_MODE_3:104 *function = COUNTER_FUNCTION_QUADRATURE_X4;105 return 0;106 default:107 return -EINVAL;108 }109}110 111static int stm32_count_function_write(struct counter_device *counter,112 struct counter_count *count,113 enum counter_function function)114{115 struct stm32_timer_cnt *const priv = counter_priv(counter);116 u32 cr1, sms;117 118 switch (function) {119 case COUNTER_FUNCTION_INCREASE:120 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;121 break;122 case COUNTER_FUNCTION_QUADRATURE_X2_A:123 if (!priv->has_encoder)124 return -EOPNOTSUPP;125 sms = TIM_SMCR_SMS_ENCODER_MODE_1;126 break;127 case COUNTER_FUNCTION_QUADRATURE_X2_B:128 if (!priv->has_encoder)129 return -EOPNOTSUPP;130 sms = TIM_SMCR_SMS_ENCODER_MODE_2;131 break;132 case COUNTER_FUNCTION_QUADRATURE_X4:133 if (!priv->has_encoder)134 return -EOPNOTSUPP;135 sms = TIM_SMCR_SMS_ENCODER_MODE_3;136 break;137 default:138 return -EINVAL;139 }140 141 /* Store enable status */142 regmap_read(priv->regmap, TIM_CR1, &cr1);143 144 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);145 146 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);147 148 /* Make sure that registers are updated */149 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);150 151 /* Restore the enable status */152 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);153 154 return 0;155}156 157static int stm32_count_direction_read(struct counter_device *counter,158 struct counter_count *count,159 enum counter_count_direction *direction)160{161 struct stm32_timer_cnt *const priv = counter_priv(counter);162 u32 cr1;163 164 regmap_read(priv->regmap, TIM_CR1, &cr1);165 *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :166 COUNTER_COUNT_DIRECTION_FORWARD;167 168 return 0;169}170 171static int stm32_count_ceiling_read(struct counter_device *counter,172 struct counter_count *count, u64 *ceiling)173{174 struct stm32_timer_cnt *const priv = counter_priv(counter);175 u32 arr;176 177 regmap_read(priv->regmap, TIM_ARR, &arr);178 179 *ceiling = arr;180 181 return 0;182}183 184static int stm32_count_ceiling_write(struct counter_device *counter,185 struct counter_count *count, u64 ceiling)186{187 struct stm32_timer_cnt *const priv = counter_priv(counter);188 189 if (ceiling > priv->max_arr)190 return -ERANGE;191 192 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */193 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);194 regmap_write(priv->regmap, TIM_ARR, ceiling);195 196 return 0;197}198 199static int stm32_count_enable_read(struct counter_device *counter,200 struct counter_count *count, u8 *enable)201{202 struct stm32_timer_cnt *const priv = counter_priv(counter);203 u32 cr1;204 205 regmap_read(priv->regmap, TIM_CR1, &cr1);206 207 *enable = cr1 & TIM_CR1_CEN;208 209 return 0;210}211 212static int stm32_count_enable_write(struct counter_device *counter,213 struct counter_count *count, u8 enable)214{215 struct stm32_timer_cnt *const priv = counter_priv(counter);216 u32 cr1;217 218 if (enable) {219 regmap_read(priv->regmap, TIM_CR1, &cr1);220 if (!(cr1 & TIM_CR1_CEN))221 clk_enable(priv->clk);222 223 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,224 TIM_CR1_CEN);225 } else {226 regmap_read(priv->regmap, TIM_CR1, &cr1);227 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);228 if (cr1 & TIM_CR1_CEN)229 clk_disable(priv->clk);230 }231 232 /* Keep enabled state to properly handle low power states */233 priv->enabled = enable;234 235 return 0;236}237 238static int stm32_count_prescaler_read(struct counter_device *counter,239 struct counter_count *count, u64 *prescaler)240{241 struct stm32_timer_cnt *const priv = counter_priv(counter);242 u32 psc;243 244 regmap_read(priv->regmap, TIM_PSC, &psc);245 246 *prescaler = psc + 1;247 248 return 0;249}250 251static int stm32_count_prescaler_write(struct counter_device *counter,252 struct counter_count *count, u64 prescaler)253{254 struct stm32_timer_cnt *const priv = counter_priv(counter);255 u32 psc;256 257 if (!prescaler || prescaler > MAX_TIM_PSC + 1)258 return -ERANGE;259 260 psc = prescaler - 1;261 262 return regmap_write(priv->regmap, TIM_PSC, psc);263}264 265static int stm32_count_cap_read(struct counter_device *counter,266 struct counter_count *count,267 size_t ch, u64 *cap)268{269 struct stm32_timer_cnt *const priv = counter_priv(counter);270 u32 ccrx;271 272 if (ch >= priv->nchannels)273 return -EOPNOTSUPP;274 275 switch (ch) {276 case 0:277 regmap_read(priv->regmap, TIM_CCR1, &ccrx);278 break;279 case 1:280 regmap_read(priv->regmap, TIM_CCR2, &ccrx);281 break;282 case 2:283 regmap_read(priv->regmap, TIM_CCR3, &ccrx);284 break;285 case 3:286 regmap_read(priv->regmap, TIM_CCR4, &ccrx);287 break;288 default:289 return -EINVAL;290 }291 292 dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx);293 294 *cap = ccrx;295 296 return 0;297}298 299static int stm32_count_nb_ovf_read(struct counter_device *counter,300 struct counter_count *count, u64 *val)301{302 struct stm32_timer_cnt *const priv = counter_priv(counter);303 unsigned long irqflags;304 305 spin_lock_irqsave(&priv->lock, irqflags);306 *val = priv->nb_ovf;307 spin_unlock_irqrestore(&priv->lock, irqflags);308 309 return 0;310}311 312static int stm32_count_nb_ovf_write(struct counter_device *counter,313 struct counter_count *count, u64 val)314{315 struct stm32_timer_cnt *const priv = counter_priv(counter);316 unsigned long irqflags;317 318 spin_lock_irqsave(&priv->lock, irqflags);319 priv->nb_ovf = val;320 spin_unlock_irqrestore(&priv->lock, irqflags);321 322 return 0;323}324 325static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4);326 327static struct counter_comp stm32_count_ext[] = {328 COUNTER_COMP_DIRECTION(stm32_count_direction_read),329 COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),330 COUNTER_COMP_CEILING(stm32_count_ceiling_read,331 stm32_count_ceiling_write),332 COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read,333 stm32_count_prescaler_write),334 COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array),335 COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write),336};337 338static const enum counter_synapse_action stm32_clock_synapse_actions[] = {339 COUNTER_SYNAPSE_ACTION_RISING_EDGE,340};341 342static const enum counter_synapse_action stm32_synapse_actions[] = {343 COUNTER_SYNAPSE_ACTION_NONE,344 COUNTER_SYNAPSE_ACTION_BOTH_EDGES345};346 347static int stm32_action_read(struct counter_device *counter,348 struct counter_count *count,349 struct counter_synapse *synapse,350 enum counter_synapse_action *action)351{352 enum counter_function function;353 int err;354 355 err = stm32_count_function_read(counter, count, &function);356 if (err)357 return err;358 359 switch (function) {360 case COUNTER_FUNCTION_INCREASE:361 /* counts on internal clock when CEN=1 */362 if (synapse->signal->id == STM32_CLOCK_SIG)363 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;364 else365 *action = COUNTER_SYNAPSE_ACTION_NONE;366 return 0;367 case COUNTER_FUNCTION_QUADRATURE_X2_A:368 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */369 if (synapse->signal->id == STM32_CH1_SIG)370 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;371 else372 *action = COUNTER_SYNAPSE_ACTION_NONE;373 return 0;374 case COUNTER_FUNCTION_QUADRATURE_X2_B:375 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */376 if (synapse->signal->id == STM32_CH2_SIG)377 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;378 else379 *action = COUNTER_SYNAPSE_ACTION_NONE;380 return 0;381 case COUNTER_FUNCTION_QUADRATURE_X4:382 /* counts up/down on both TI1FP1 and TI2FP2 edges */383 if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG)384 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;385 else386 *action = COUNTER_SYNAPSE_ACTION_NONE;387 return 0;388 default:389 return -EINVAL;390 }391}392 393struct stm32_count_cc_regs {394 u32 ccmr_reg;395 u32 ccmr_mask;396 u32 ccmr_bits;397 u32 ccer_bits;398};399 400static const struct stm32_count_cc_regs stm32_cc[] = {401 { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1,402 TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP },403 { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2,404 TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP },405 { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3,406 TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP },407 { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4,408 TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP },409};410 411static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch,412 bool enable)413{414 struct stm32_timer_cnt *const priv = counter_priv(counter);415 const struct stm32_count_cc_regs *cc;416 u32 ccmr, ccer;417 418 if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) {419 dev_err(counter->parent, "invalid ch: %d\n", ch);420 return -EINVAL;421 }422 423 cc = &stm32_cc[ch];424 425 /*426 * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2...427 * Select both edges / non-inverted to trigger a capture.428 */429 if (enable) {430 /* first clear possibly latched capture flag upon enabling */431 if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits))432 regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch));433 regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask,434 cc->ccmr_bits);435 regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits);436 } else {437 regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits);438 regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask);439 }440 441 regmap_read(priv->regmap, cc->ccmr_reg, &ccmr);442 regmap_read(priv->regmap, TIM_CCER, &ccer);443 dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis",444 ch, ccmr, ccer);445 446 return 0;447}448 449static int stm32_count_events_configure(struct counter_device *counter)450{451 struct stm32_timer_cnt *const priv = counter_priv(counter);452 struct counter_event_node *event_node;453 u32 dier = 0;454 int i, ret;455 456 list_for_each_entry(event_node, &counter->events_list, l) {457 switch (event_node->event) {458 case COUNTER_EVENT_OVERFLOW_UNDERFLOW:459 /* first clear possibly latched UIF before enabling */460 if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE))461 regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF);462 dier |= TIM_DIER_UIE;463 break;464 case COUNTER_EVENT_CAPTURE:465 ret = stm32_count_capture_configure(counter, event_node->channel, true);466 if (ret)467 return ret;468 dier |= TIM_DIER_CCxIE(event_node->channel + 1);469 break;470 default:471 /* should never reach this path */472 return -EINVAL;473 }474 }475 476 /* Enable / disable all events at once, from events_list, so write all DIER bits */477 regmap_write(priv->regmap, TIM_DIER, dier);478 479 /* check for disabled capture events */480 for (i = 0 ; i < priv->nchannels; i++) {481 if (!(dier & TIM_DIER_CCxIE(i + 1))) {482 ret = stm32_count_capture_configure(counter, i, false);483 if (ret)484 return ret;485 }486 }487 488 return 0;489}490 491static int stm32_count_watch_validate(struct counter_device *counter,492 const struct counter_watch *watch)493{494 struct stm32_timer_cnt *const priv = counter_priv(counter);495 496 /* Interrupts are optional */497 if (!priv->nr_irqs)498 return -EOPNOTSUPP;499 500 switch (watch->event) {501 case COUNTER_EVENT_CAPTURE:502 if (watch->channel >= priv->nchannels) {503 dev_err(counter->parent, "Invalid channel %d\n", watch->channel);504 return -EINVAL;505 }506 return 0;507 case COUNTER_EVENT_OVERFLOW_UNDERFLOW:508 return 0;509 default:510 return -EINVAL;511 }512}513 514static const struct counter_ops stm32_timer_cnt_ops = {515 .count_read = stm32_count_read,516 .count_write = stm32_count_write,517 .function_read = stm32_count_function_read,518 .function_write = stm32_count_function_write,519 .action_read = stm32_action_read,520 .events_configure = stm32_count_events_configure,521 .watch_validate = stm32_count_watch_validate,522};523 524static int stm32_count_clk_get_freq(struct counter_device *counter,525 struct counter_signal *signal, u64 *freq)526{527 struct stm32_timer_cnt *const priv = counter_priv(counter);528 529 *freq = clk_get_rate(priv->clk);530 531 return 0;532}533 534static struct counter_comp stm32_count_clock_ext[] = {535 COUNTER_COMP_FREQUENCY(stm32_count_clk_get_freq),536};537 538static struct counter_signal stm32_signals[] = {539 /*540 * Need to declare all the signals as a static array, and keep the signals order here,541 * even if they're unused or unexisting on some timer instances. It's an abstraction,542 * e.g. high level view of the counter features.543 *544 * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2",545 * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used,546 * to indicate that a signal doesn't affect the counter.547 */548 {549 .id = STM32_CH1_SIG,550 .name = "Channel 1"551 },552 {553 .id = STM32_CH2_SIG,554 .name = "Channel 2"555 },556 {557 .id = STM32_CLOCK_SIG,558 .name = "Clock",559 .ext = stm32_count_clock_ext,560 .num_ext = ARRAY_SIZE(stm32_count_clock_ext),561 },562 {563 .id = STM32_CH3_SIG,564 .name = "Channel 3"565 },566 {567 .id = STM32_CH4_SIG,568 .name = "Channel 4"569 },570};571 572static struct counter_synapse stm32_count_synapses[] = {573 {574 .actions_list = stm32_synapse_actions,575 .num_actions = ARRAY_SIZE(stm32_synapse_actions),576 .signal = &stm32_signals[STM32_CH1_SIG]577 },578 {579 .actions_list = stm32_synapse_actions,580 .num_actions = ARRAY_SIZE(stm32_synapse_actions),581 .signal = &stm32_signals[STM32_CH2_SIG]582 },583 {584 .actions_list = stm32_clock_synapse_actions,585 .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions),586 .signal = &stm32_signals[STM32_CLOCK_SIG]587 },588 {589 .actions_list = stm32_synapse_actions,590 .num_actions = ARRAY_SIZE(stm32_synapse_actions),591 .signal = &stm32_signals[STM32_CH3_SIG]592 },593 {594 .actions_list = stm32_synapse_actions,595 .num_actions = ARRAY_SIZE(stm32_synapse_actions),596 .signal = &stm32_signals[STM32_CH4_SIG]597 },598};599 600static struct counter_count stm32_counts = {601 .id = 0,602 .name = "STM32 Timer Counter",603 .functions_list = stm32_count_functions,604 .num_functions = ARRAY_SIZE(stm32_count_functions),605 .synapses = stm32_count_synapses,606 .num_synapses = ARRAY_SIZE(stm32_count_synapses),607 .ext = stm32_count_ext,608 .num_ext = ARRAY_SIZE(stm32_count_ext)609};610 611static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr)612{613 struct counter_device *counter = ptr;614 struct stm32_timer_cnt *const priv = counter_priv(counter);615 u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */616 u32 sr, dier;617 int i;618 619 regmap_read(priv->regmap, TIM_SR, &sr);620 regmap_read(priv->regmap, TIM_DIER, &dier);621 /*622 * Some status bits in SR don't match with the enable bits in DIER. Only take care of623 * the possibly enabled bits in DIER (that matches in between SR and DIER).624 */625 dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE);626 sr &= dier;627 628 if (sr & TIM_SR_UIF) {629 spin_lock(&priv->lock);630 priv->nb_ovf++;631 spin_unlock(&priv->lock);632 counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0);633 dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n");634 /* SR flags can be cleared by writing 0, only clear relevant flag */635 clr &= ~TIM_SR_UIF;636 }637 638 /* Check capture events */639 for (i = 0 ; i < priv->nchannels; i++) {640 if (sr & TIM_SR_CC_IF(i)) {641 counter_push_event(counter, COUNTER_EVENT_CAPTURE, i);642 clr &= ~TIM_SR_CC_IF(i);643 dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i);644 }645 }646 647 regmap_write(priv->regmap, TIM_SR, clr);648 649 return IRQ_HANDLED;650};651 652static void stm32_timer_cnt_detect_channels(struct device *dev,653 struct stm32_timer_cnt *priv)654{655 u32 ccer, ccer_backup;656 657 regmap_read(priv->regmap, TIM_CCER, &ccer_backup);658 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE);659 regmap_read(priv->regmap, TIM_CCER, &ccer);660 regmap_write(priv->regmap, TIM_CCER, ccer_backup);661 priv->nchannels = hweight32(ccer & TIM_CCER_CCXE);662 663 dev_dbg(dev, "has %d cc channels\n", priv->nchannels);664}665 666/* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 */667#define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7))668 669static const char * const stm32_timer_trigger_compat[] = {670 "st,stm32-timer-trigger",671 "st,stm32h7-timer-trigger",672};673 674static int stm32_timer_cnt_probe_encoder(struct device *dev,675 struct stm32_timer_cnt *priv)676{677 struct device *parent = dev->parent;678 struct device_node *tnode = NULL, *pnode = parent->of_node;679 int i, ret;680 u32 idx;681 682 /*683 * Need to retrieve the trigger node index from DT, to be able684 * to determine if the counter supports encoder mode. It also685 * enforce backward compatibility, and allow to support other686 * counter modes in this driver (when the timer doesn't support687 * encoder).688 */689 for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++)690 tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]);691 if (!tnode) {692 dev_err(dev, "Can't find trigger node\n");693 return -ENODATA;694 }695 696 ret = of_property_read_u32(tnode, "reg", &idx);697 if (ret) {698 dev_err(dev, "Can't get index (%d)\n", ret);699 return ret;700 }701 702 priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx));703 704 dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no");705 706 return 0;707}708 709static int stm32_timer_cnt_probe(struct platform_device *pdev)710{711 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);712 struct device *dev = &pdev->dev;713 struct stm32_timer_cnt *priv;714 struct counter_device *counter;715 int i, ret;716 717 if (IS_ERR_OR_NULL(ddata))718 return -EINVAL;719 720 counter = devm_counter_alloc(dev, sizeof(*priv));721 if (!counter)722 return -ENOMEM;723 724 priv = counter_priv(counter);725 726 priv->regmap = ddata->regmap;727 priv->clk = ddata->clk;728 priv->max_arr = ddata->max_arr;729 priv->nr_irqs = ddata->nr_irqs;730 731 ret = stm32_timer_cnt_probe_encoder(dev, priv);732 if (ret)733 return ret;734 735 stm32_timer_cnt_detect_channels(dev, priv);736 737 counter->name = dev_name(dev);738 counter->parent = dev;739 counter->ops = &stm32_timer_cnt_ops;740 counter->counts = &stm32_counts;741 counter->num_counts = 1;742 counter->signals = stm32_signals;743 counter->num_signals = ARRAY_SIZE(stm32_signals);744 745 spin_lock_init(&priv->lock);746 747 platform_set_drvdata(pdev, priv);748 749 /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */750 if (priv->nr_irqs == 1) {751 /* All events reported through the global interrupt */752 ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr,753 0, dev_name(dev), counter);754 if (ret) {755 dev_err(dev, "Failed to request irq %d (err %d)\n",756 ddata->irq[0], ret);757 return ret;758 }759 } else {760 for (i = 0; i < priv->nr_irqs; i++) {761 /*762 * Only take care of update IRQ for overflow events, and cc for763 * capture events.764 */765 if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC)766 continue;767 768 ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr,769 0, dev_name(dev), counter);770 if (ret) {771 dev_err(dev, "Failed to request irq %d (err %d)\n",772 ddata->irq[i], ret);773 return ret;774 }775 }776 }777 778 /* Reset input selector to its default input */779 regmap_write(priv->regmap, TIM_TISEL, 0x0);780 781 /* Register Counter device */782 ret = devm_counter_add(dev, counter);783 if (ret < 0)784 dev_err_probe(dev, ret, "Failed to add counter\n");785 786 return ret;787}788 789static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)790{791 struct stm32_timer_cnt *priv = dev_get_drvdata(dev);792 793 /* Only take care of enabled counter: don't disturb other MFD child */794 if (priv->enabled) {795 /* Backup registers that may get lost in low power mode */796 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);797 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);798 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);799 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);800 801 /* Disable the counter */802 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);803 clk_disable(priv->clk);804 }805 806 return pinctrl_pm_select_sleep_state(dev);807}808 809static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)810{811 struct stm32_timer_cnt *priv = dev_get_drvdata(dev);812 int ret;813 814 ret = pinctrl_pm_select_default_state(dev);815 if (ret)816 return ret;817 818 if (priv->enabled) {819 clk_enable(priv->clk);820 821 /* Restore registers that may have been lost */822 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);823 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);824 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);825 826 /* Also re-enables the counter */827 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);828 }829 830 return 0;831}832 833static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,834 stm32_timer_cnt_resume);835 836static const struct of_device_id stm32_timer_cnt_of_match[] = {837 { .compatible = "st,stm32-timer-counter", },838 {},839};840MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);841 842static struct platform_driver stm32_timer_cnt_driver = {843 .probe = stm32_timer_cnt_probe,844 .driver = {845 .name = "stm32-timer-counter",846 .of_match_table = stm32_timer_cnt_of_match,847 .pm = &stm32_timer_cnt_pm_ops,848 },849};850module_platform_driver(stm32_timer_cnt_driver);851 852MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");853MODULE_ALIAS("platform:stm32-timer-counter");854MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");855MODULE_LICENSE("GPL v2");856MODULE_IMPORT_NS(COUNTER);857