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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2012-2013 Xilinx4 *5 * CPU idle support for Xilinx Zynq6 *7 * based on arch/arm/mach-at91/cpuidle.c8 *9 * The cpu idle uses wait-for-interrupt and RAM self refresh in order10 * to implement two idle states -11 * #1 wait-for-interrupt12 * #2 wait-for-interrupt and RAM self refresh13 *14 * Maintainer: Michal Simek <michal.simek@xilinx.com>15 */16 17#include <linux/init.h>18#include <linux/cpuidle.h>19#include <linux/platform_device.h>20#include <asm/cpuidle.h>21 22#define ZYNQ_MAX_STATES 223 24/* Actual code that puts the SoC in different idle states */25static int zynq_enter_idle(struct cpuidle_device *dev,26 struct cpuidle_driver *drv, int index)27{28 /* Add code for DDR self refresh start */29 cpu_do_idle();30 31 return index;32}33 34static struct cpuidle_driver zynq_idle_driver = {35 .name = "zynq_idle",36 .owner = THIS_MODULE,37 .states = {38 ARM_CPUIDLE_WFI_STATE,39 {40 .enter = zynq_enter_idle,41 .exit_latency = 10,42 .target_residency = 10000,43 .name = "RAM_SR",44 .desc = "WFI and RAM Self Refresh",45 },46 },47 .safe_state_index = 0,48 .state_count = ZYNQ_MAX_STATES,49};50 51/* Initialize CPU idle by registering the idle states */52static int zynq_cpuidle_probe(struct platform_device *pdev)53{54 pr_info("Xilinx Zynq CpuIdle Driver started\n");55 56 return cpuidle_register(&zynq_idle_driver, NULL);57}58 59static struct platform_driver zynq_cpuidle_driver = {60 .driver = {61 .name = "cpuidle-zynq",62 },63 .probe = zynq_cpuidle_probe,64};65builtin_platform_driver(zynq_cpuidle_driver);66